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*   HqFpga-XIST Seal Beta Build Release Note
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* UPDATE HISTORY *

[03/27/2021] V2.9.8 BETA032721 <===========================

- Device update
  Add param WRITE_LEVEING support for Seal DQSBUF
- Downloader
  Update for 30K MPW device
- GUI
  resolve issue of wrongly turning on LE level packing/placement 
  in multiple device run  

(V2.9.8 FT032521)
- Placer
  Correct problem of PT7A/B/C/D bank number for 30K device
- Packing/Bitgen
  Updated parameters (PHASE_SHIFT, WRITE_LEVELING, ...etc) for IODDR cells

(V2.9.8 FT032421)
- Seal 30K PIO PG NG fuse support
  With GUI updated
- Seal mpw ebr 72-bit PDP EBR support

(V2.9.7 FT031621)
- Bitgen
  Fix PLL Refclk4 typo
  MPW IMUX21 and BYP2 share fuse
- Placement
  Refined set_global_attr by considering VCCIO
- Packing
  Fixed ODDR71 related issue
- RTL synthesis
  Fixed a bug in FSM extraction related with decoder.

(V2.9.7 FT031121)
- RTL synthesis
  Updated INIT value handling for Seal device
  Fixed a corner issue related with string parameter using ?: operator
- Routing
  Fixed DCS-SEL routing fail for Seal 100 device
- Constraint
  Support ioh.set_global_attr -unused_io tie_z for seal device
- 
(V2.9.7 FT031021)
- Routing
  Fixed a bug for DCS-SEL CIB clk_cs_1/clk_cs_3
- ECO
  Fixed a bug related with TIEOFF in signal-probe.
  Refined for X4 test pattern
  Fixed issue related with EBR input.

(V2.9.7 FT030921)
- ECO
  Initial signal probe support for seal device
  
(V2.9.7 FT030521)
- Clock TAP index constraint support :
  phycst.net.set <net> -index <clock_index> -tapidx <tap_index>
- Bitgen
  CIBTEST support update
  DCS support update
  
(V2.9.7 FT030421)
- Seal EFB support refine

(V2.9.7 FT030221)
- Placement
  Fixed PIO2PCLK clock counting issue (issue from Guowei)
  Fixed PIO2ECLK dedicated connection issue (issue from Huifen)
- PLL IPGEN update for CLKOS3_FRAC_DIV support (req. by WenQin)
- Bitgen : DSP dyn_opr_inv fuse invert for mpw

(V2.9.7 FT030221)
- PLL IPGEN update for trim and interanl-feedback support, for sealion and seal devices
- Routing bug-fix for DDRCTRL of Seal 100K device
- Seal CIBTEST intitial flow support

[02/26/2021] V2.9.7 BETA022621 <===========================
- PLL IP Creator update for RESET/STDBY/CLKISEL/DPHASE/FBMODE
- PLLREFCS support update
(V2.9.7 FT022521)
- Packing
  Prevent dropping user contraint when doing LUT input redundency removal
- Routing
  Support disabling tiles for routing 
  ECLK bridge bug-fixes for sealion devices

[02/23/2021] V2.9.6 BETA022321 <===========================
> Seal IP Creator refactor 
> Incorporated FT021921 update
- Bitgen
  bitgen "ctrl0" update for Seal 30K devices
- Placement
  Fixed global net assignment win/linux difference issue 

[02/10/2021] V2.9.6 BETA021021 <===========================
- Placement
  Fixed issues related with SLICEM carry chain placement
  Fixed issues related with PCLK assignment
  Fixed several functional issues in LE packing
  Enhance DSP support related with SIGNED/SOURCEA/B ports
- Routing
  Fixed dedicated clock-to-PLL input routing error.
- Bitgen/Downloader
  Fixed extra leading 0000 issue in bin file generation for 30K devices
  Support 30K devices.

[01/24/2021] V2.9.6 BETA012421
- Initial beta version for Seal device support.