*******************************************************************
*
*   HqFpga-XIST V2.10.4 Release Note
*
*******************************************************************
* UPDATE HISTORY *

[07/30/2021]  V2.10.4 Update Build 073021
- Sealion 7K device support update
  DQSI, DQSDLL, BCLVDSO related updates.
- RTL Synthesis
  Refine Pseudo dual port RAM mapping
  Refine ROM infer/map
- Downloader
  Update 7K device ID

[07/28/2021]  V2.10.4 Update Build 072821
- Re-enable ECLKBRIDGE resources in looptdo routing
  (Previously disabled during the period of fixing ECLKBRIDGE bugs)

[07/24/2021]  V2.10.4 Update Build 072421
- RTL synthesis
  Fix a corner bug in MUX optimization for sealion family
- HqInsight
  Refine design hierarchy display
  Fix a bug related with same signal name with different bit width
     in different module.
  Refine message prompt for invalid decimal constant

[07/17/2021]  V2.10.4 <============================================
- Sealion 7K device related updates
  Fix issues in bitstream generation, related with RPLL/FIBMEM/B8CMD.
  Bitstream generation update related with XFG file and PGNG support.
  Downloader update
  Fix DQS0.DQSI connection issue.
- RTL synthesis
  Fix FSM-mux judge regression issue
  Fix a FSM crash issue, related with loop back accumulator as FSM input
  Remove no-use nodes generated by FSM optimization to avoid un-necessary warning.
- GUI
  Refine RTL file dependency check.
  Fix a problem that debug mode run affects normal mode run
  Fix a bug updating <auto> top module after RTL synthesis
- HqInsight
  Refine instrumented signal change based on file change.
  Fix signal name conflict issue
  Fix trigger timeout issue.
  Fix regression issue caused by IP obfuscation
  Refine waveform display
     Auto center of trigger event
     Show sample clock number in decimal format
  Refine debug-IP generation to avoid compile warnings.
- IP Creator
  Updated PLL IPGEN for 5k/7k devices
- Other
  Restructure simulation model files : from all-in-one file to primitive based.

[06/11/2021]  V2.10.3 <============================================
- Device/package update
  SL2-7E-8U400 renames to SL2E-7V-8U400
  Fix a bug related with flash control for 7K devices.
- RTL synthesis
  Fix a bug related with invalid/initial state in FSM optimization
  Refine message prompt related with latch, port-width mistach,...etc
- HqInsight
  Resolve issues related with mix-EOL in source RTL files
  Resolve issues related with marking signals
  Auto add signal list to display when opening waveform viewer
  Retain project seeting when there's sntax error in source files.
- IP Creator
  Add UFM control for 7k devcies

[05/17/2021]  V2.10.2 <============================================
- New package support
  SL2-7E-8U400
  SL2E-5E-8WE81
- HqInsight
  Support force-trigger feature
  Solve issue related with system function $signed and $unsigned
- IP Creator
  Fix regression issues related with FIFO full/empty flag and data_width
- Placement
  Fix auto-placement issue related with irregular use of CLKDIV
  Refine message related with in-compatible IO_TYPE/bankvcc
- RTL Synthesis
  Fix message prompt exception related with black-box parameter binding by order

[05/03/2021]  V2.10.1 <============================================
- IP Creator
  Fix issues related with FIFO full/empty flag
  Fix data_width issues related with PDP-EBR
- HqInsigth
  Fix IO standard issue related with auto-inserted JTAG IOs for SL2E
    and SL2D devices (with SDRAM/DDRAM packaged)
- GUI
  Fixed Sealion 12k EA176 bank issue
  Fix crash problem related with delay calcuation for paths between
     unconstrained IO and registers.
  Fix issue related with dangling port-net
- RTL synthesis
  Fix a bug in module instantiation when neither instance name nor
    dot in formal port anmes is specified.

[04/17/2021]  V2.9.9 <=============================================
- IP Creator
  Fix SPROM/FIFO issue related with address less than 9 bits
- RTL Synthesis
  Fix some corner issues, e.g. infinite loop caused by typo "cnt<=cnt+0"
- HqInsight
  Save trigger condition in debugger
- Design Explorer
  Fix bugs related with empty file

[03/20/2021]  V2.9.8 <=============================================
- RTL Synthesis
  Fixed a bug in FF synchronous set/reset extraction
  Fixed a bug in FSM optimization related with memory address decoder.
- Packing
  Prevent dropping user constraint when doing LUT input redundancy removal
  Updated default BANK VCC for LVDS25 standard.
- Placement
  Fix PLLREFCS related issue for Sealion 5K/25K devices
- Routing
  ClockIO-to-ECLKBRIDGE bug-fixes for Sealion devices
- IP Creator
  PLL IPGEN update for RESET/STDBY/CLKISEL/DPHASE/FBMODE/TRIM/INT_FEEDBACK
- Misc.
  Refine project path support

[02/19/2021]  V2.9.7 <=============================================
- Placement
  Enhanced Bank IO VCC compatibilty checking
- Routing
  Fixed dedicated clock-to-PLL input routing error in some 12k/25k devices.
- HqInsight
  Support relative path in project file
- IP Creator
  Fixed issues in DSP IPGEN, related with data-width and control signals

[01/24/2021]  V2.9.6 <=============================================
- IP Creator
  Fixed an error in DSP 18x18 IP generation.
- GUI
  Fixed an issue in constraint editor related with port OPENDRAIN
  property setting.

[01/21/2021]  V2.9.5 <=============================================
- Sealion 25K EA176 device update

[01/17/2021]  V2.9.4 <=============================================
- IP Creator
  Updated support for UFM Flash control IP for sealion 5K devices
  Refined latency support for DSP IPs
  Fixed a bug in PDP-EBR IP with read address depth 512
- HqInsight
  Fixed a bug of display blank for files with mass encoded characters
- Bitgen
  Update for UFM Flash control IP for sealion 5K devices
- RTL synthesis
  Fixed a bug in module instantiation related with non-existing port
  Fixed a bug in RAM-based shift register handling which causes conflict
     with normal RAM handling

[01/10/2021]  V2.9.3 <=============================================
- GUI
  Added option to specifiy Verilog include paths.
  Fixed a problem that RTL-synthesis-STA report wrongly overwrites
  Place-and-route-STA report.
- IP creator
  Fixed a text typo for DP-EBR IP.
- RTL synthesis
  Message refine.

[12/29/2020]  V2.9.2 <=============================================
- OSC support update for 25K devices
- Bitgen update for EBR with read-before-write mode
- HqInsight
  Speed up signal intrumenting in netlist flow
  Optionally add pipeline register for sample/trigger signals
- Downloader
  Add SVF2MJA function
  Updates related with flash control and download modes.
  (cable v1.5)

[12/05/2020]  V2.9.1 UPD120520
- Place-and-route
  Fixed issues related with MULT9 and MULT18 placement.
  Enhance user clock net constraint handling in extra-mode routing.
- RTL synthesis
  Fixed a bug in FSM optimization, related with symbolic state coding.
- STA
  Consider false paths when reporting FMAX.
- Downloader
  Updates related with flash control and download modes.
  (MCU v1.7, cable v1.4)

[11/20/2020]  V2.9.1 <=============================================
- New device/package support
  Sealion 25k EA176 Package(SL2S-25E-EA176)
- Place-and-route
  Extra-mode router runtime reduction
  Refined congestion handling of placement.
  *****
  Total runtime reduces by ~40% with enhanced routability
  *****
- Device modeling
  Fixed a bug of timing model for wide-data-width EBR
- HqInsight
  Unified user experiences of RTL and netlist level debugging
  Enhanced display of instrumented signals
  Refined support for signal selection
  Fixed bugs related with special signal names

*******************************************************************

[10/28/2020]  V2.8.6 UPD102920
- Device modeling
  Fixing timing-arc-missing problem for MULT9/ALU24
- IP Creator
  Add support to specify PLL LOCK accuracy
- Placement
  Fixed a bug of (wrongly) same-location-positioning of a standalone
  MULT9 and a MULT9 in ALU24 group
- RTL synthesis
  Support global setting of register power-up value (Experimental!)

[10/18/2020]  V2.8.6 <=============================================
- HqInsight
  Support (EDIF) netlist level debugging
- IP Creator
  Fixed bugs in EBR-DP IPGEN

[10/12/2020]  V2.8.5 Update Build 101220
- Packing/placement
  Update for IOREG with reset/reset contronl
  Refined message prompting

[09/25/2020]  V2.8.5 <=============================================
- New device/package support
  SL2E-5E-W81
- RTL synthesis
  Refined shift register optimzation
  Refined FSM optimization
- IP Creator
  PLL IP generation update for clock phase shift, RESET and LOCK customization
- HqInsight
  Improved stablity
- Design interface
  Fixed a problem related with importing 3rd-party pseudo dual port RAM

[08/30/2020]  V2.8.4 <=============================================
- Bitgen/Downloader
  Support frame-wide CRC for Sealion devices
  MIPI related (LVDS trim) update for Sealion 5K device
- RTL synthesis
  Fixed a bug related with synchronous set/reset handling.
  Fixed a bug related with ROM inference
- IP Creator
  Add divider IP support

[08/01/2020]  V2.8.3 Update Build 080120
- HqInsight
  Refined hierarchy and generate statement handling.
  Refined GUI look and improved interactivity
  Bug-fixes:
     Power-off causing false-triggering
     defparam dump issue related with '.' in instance name
- Design Explorer
  Fixed editor crash problem related with GB2312 text coding
- Main program
  Exception checking and handling for implementing (IP) netlist without IO cells

[07/25/2020]  V2.8.3 Update Build 072520
- Packing
  Refined PLL support
- Placement
  Fixed an issue related with auto-placement of DQSBUF
- RTL synthesis
  Refined RAM-based shift register handling
- HqInsight
  Fixed a problem of writing debug-purpose file on D:\
[07/20/2020]  V2.8.3 Update Build 072020
- Updated OSC support

[07/18/2020]  V2.8.3  <=============================================
- New package support
  Sealion 5K QFN84 package (SL2-5E-8N84)
- HqInsight
  Support stop waiting for signal triggering.
  Fixed background printing issue after program exist abnormally
  Refined waveform display
- IP Creator
  Fixed an issue related with PLLof 25K/5K devices (CLKOPD_DLY parameter).
  Update for Block-RAM IP generation, related with PDP 32bit data width.
- Main GUI
  Support interruption of flow execution
  Added asynchronous set/reset-to-output handling option
- Main program
  Fix a bug related with byte enable on wide PDP EBR.

[07/03/2020]  V2.8.2  Update Build 070320
- RTL synthesis
  Fixed a bug in shfit register inference
- IpCreator
  Support BlockRAM with more shape (width/depth ratio)
  Update support for initializing BRAM with file.
- HqInsight
  Refine waveform display
  Add vcd2prn data conversion function

[07/01/2020]  V2.8.2  Update Build 070120
- Place and Route
  Refined delay estimation to/from BRAM/DSP
  Increase extra-mode routability
  Delay annotation after normal-mode router

[06/28/2020]  V2.8.2  <=============================================
- Device model
  Deployed 20200601 calibrated timing data
      mainly including update for SLICE and interconnect routing resources.
  Updated delay calcuation based on piecewise linear fanout model
  Updated delay annotation with four value format (minr,maxr, minf,maxf)
- STA
  Optionally handle asynchronous set/reset-to-q timing arc/path
  Fixed issues in handling set_max/min_delay -from/to clock situation
- Placement & Routing
  QoR improvement
  Optionally disabling SCLK/ECLK resources.


[06/05/2020]  V2.8.1  <=============================================

- Downloader
  Update WHQL cable driver
- RTL synthesis
  Fix a bug in accumulator inference when a maxium unsigned constant number
  Fix a bug in pre-processor, related with netsted macro handling with comments
- HqInsight
  Fix a issue when data width is not an integer multiple of 8 bits
- GUI
  Support of add/remove/set top module in design explorer
  Better synchronization between main UI and design explorer
- Device modeling
  Update JTAG timing arcs
  Fix typos in SLICE asynchronous recovery/removal
- Packing
  Fix an issue related with BRAM write-mode configuration (N_EDGE)


[05/15/2020]  V2.7.10 <=============================================
- Bitgen, Downloader
  Update for 12K RevC devices

[05/09/2020]  V2.7.9  <=============================================
- Packing, routing and bitgen
  Update related with ECLKBRIDGE
- IP Creator
  Add Flash UFM control IP
- GUI
  retain physical constraint as much as possible when soruce file change
- Others
  Include downloader cable driver

[04/30/2020]  V2.7.8 Update Build 043020
- Router
  Refined routability for secondary clocks

[04/28/2020]  V2.7.8  <=============================================
- Device support update
  Fix DQS1 group issue
- IP Creator
  updated for FIFO 9x16 mode
  update for Block-RAM initialization file support

[04/16/2020]  V2.7.7  Update Build 041620
- Bitgen
  Support 20M MCLK Frequency in AS mode
- IP Creator
  Fixed a bug in single port ROM

[03/27/2020]  V2.7.7  <=============================================
- New package support for 12K device : SL2S-12E-EA176
  Rename SL2S-12E-Q176 to SL2S-12E-E176

[03/21/2020]  V2.7.6  Update Build 032120
- RTL synthesis
  Refined FF inference
  Refined support to registers with asynchronous load
- Design explorer
  Refined editor related with both encoding and EOL

[03/15/2020]  V2.7.6  Update Build 031520
- Routing
  Refined clock assignment in related with PLL input

[03/04/2020]  V2.7.6  <=============================================
- Packing
  Refine area optimization for small (5K) device
- RTL synthesis
  Refine suport of RAM-based shift register
  Fixe multiplier mapping issue related with sign/unsigned data.
- HqInsight
  Fixed a bug realted with memory-read error
- IP Creator
  Updated FIFO IP generation

[01/23/2020]  V2.7.5  <=============================================
- RTL Synthesis
  Added basic support for RAM-based shift register
- Placer
  More strict user constraint checking.
  Fixed an issue related with JTAG IO placement when all normal IOs are used

[01/09/2020]  V2.7.4  Update Build 010920
- Downloader
  Fixed unstable download problem under burst mode for 5K devices
- IP Creator
  Fixed an issue related for FIFO depth
  Fixed issues related with cascading single-port Block-RAM/ROMs
- Packing/Placement
  Support LUT/REG level location constraint
  Support incremental placement

[12/31/2019]  V2.7.4  <=============================================
- 5K device support update
  BITGEN update for ECLK, CLKDLY, FL, PCNTR, BANKREF
  IP Creator : fix single port ROM IP generation issue
- GUI
  IO constrait editor update for better synchronizing RTL port changes.

[12/18/2019]  V2.7.3 Update Build 121819
- Update for PG/LVDSO/INRD, for all sealion devices (5K/12K/25K)
- Router
  Updated support for fast-routing wires.

[12/13/2019]  V2.7.3 Update Build 121319
- Fixed a bug of bitstream generation, related with LVDS output of 5K devices.

[12/12/2019]  V2.7.3 Update Build 121219
- Fixed an issue in downloader in SDM mode for 5K devices (with on-die flash)
- Support more fine-tuned clock frequency divider of OSC

[12/08/2019]  V2.7.3  <=============================================
- New device support
  SL2E-5E-8N96
- SED support update for autoreboot pin
- Downloader
  Refactored GUI
- Router
  Fixed bugs related with ECLK and ALU24
  Better handling of PCLK conflicts between hardware connection against
  user constraint.
- Placer
  Fixed a bug related with 12K N96 package.
- STA
  Fixed a corner bug related with unconstrained register-to-ouput path

[11/26/2019]  V2.7.2 Update Build 112619
- Placement
  Fixed a bug related with 5K PLL
- Routing
  Fixed a bug related with mixed-clock-data net with clock constraint
- Design Interface
  Fixed an issue related with RAMD initval=0x0. (From synplify EDIF)

[11/11/2019]  V2.7.2  Fast Track build 111119
- Fixed a bug related with DSP legalization of CE pin swapping

[11/08/2019]  V2.7.2  <=============================================
- New device support
  SL2-12E-8N96
- Device name change : SL2-5E => SL2E-5E
- IP Creator
  Fixed bugs related with 5K/25K device support
- Downloader GUI
  Update 5K device name display

oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
[11/03/2019]  V2.7.1
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
- Unified format of device name to comply what specified in product
  brochure.
  > Changed device name SL2S-25E-6N96 to SL2D-25E-8N96
  > Changed device name SL2-12V-6F256 to SL2-12E-8F256
  > All the other -6 speedgrade device names are now of -8
- New device support : SL2-5E-8N96
- IP Creator
  Refactored IP generation of BRAM, FIFO and ROM
- HqInsight
  > Fixed bugs related with deep design hierarchy and syntax
    highlighting
- Place and Route
  > Fixed a placement regression issue, related with wrongly saving
    of bad wirelength in non-timing-driven flow.
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

[10/10/2019]  V2.6.5 Fast Track build 101019
- Fixed a bug related with initial value and constant register removal

[10/05/2019]  V2.6.5  <=============================================
- New device support
  SL2-5E-T256
  SL2S-25E-N96

- RTL Synthesis
  Fixed bugs related with RAM inference and logic decomposition.
- Device model
  Tighten Clock Enable setup constraint
- Place and Route
  For 25K devices : improved FMAX by ~5%, reduced placer runtime by ~10%
  Make processing adaptive to differ device/design size.
  Fixed a bug related with 25K PLL auto PCLK assignment.
- Design Explorer
  Added constraint file management.
  Supported Synchronization with HqFpga project file
- IP Creator
  Refactored support for BRAM/ROM IPs
- HqInsight
  Fixed bugs related with dos/unix EOL
  More error checking and report when dumping VCD files

[09/03/2019]  V2.6.4  Update build 090319
- Refined placement and routing for CE net
- Refined SCLK net usage for LSR/CE
- Refined bridge wire delay.

[08/19/2019]  V2.6.4  Update build 081919
- CIBTEST Updates
  timing model
  Control port types for SCLK handling

[08/03/2019]  V2.6.4  <=============================================
- RTL Synthesis
  Fixed very-wide-input logic crash problem on win32 platform
  Refined accumulator inference and mapping
- Place and Route
  Refined SCLK placement and routing for control signals
  Reduced placer runtime for 12K devices by ~5%
  Fine tuned placer QoR for 25K devices
- Design Explorer
  Refined user experience related with toolbar, file handling and cursor handling
  Added cross-probing function
  Fixed bugs related with opening empty HQ project file.
  Fixed bugs related with dos/unix EOL
- HqInsight
  Fixed bug related with partial-selected signals
  Keep Instrumentor settings as much as possible, when there are project file changes

[06/26/2019]  V2.6.3  Update build 062619
- fixed a bug related with very-wide-input logic decomposition.

[06/21/2019]  V2.6.3  Update build 062119
- Refined iterative timing driven optimization (looptdo)

[06/18/2019]  V2.6.3  Update build 061819
- Support Recovery/Removal analysis and optimization
- Refined SCLK handling for control nets
- Rollback CCU2 timing to 1x. (from FT053019)

[05/23/2019]  V2.6.3  Update build 052319
- Extra-mode router : fixed a problem related with outputting debug
  messages under corner condition.

[05/17/2019]  V2.6.3  Update build 051719
- Packing update for DDIR IO-Registers for 12k and 25K devices
- RTL synthesis update on accumulator mux optimization

[05/13/2019]  V2.6.3  Update build 051319
- JTAG IO support update for 25K uBGA213 device.

[05/11/2019]  V2.6.3  Update build 051119
- fixed a bug in ROM inference
- legalization update for xsPOWCTR

[05/03/2019]  V2.6.3  <=============================================
- Refined Carry chain timing arcs
- Packing support for absorbing pipelined register into BRAMs
- Placement update
  Refine of delay estimation
  Refine of [-effort high] optimization
  Refine of mixed clock-data pin net
- HqInsight update for usability

[04/26/2019]  V2.6.3  Release Candidate Build 042619
- update SLICE timing arcs based on 20190420 timing file
- HqInsight update
  legalization checking before saving.
  Language consistency support
  progress bar while instrumenting IP
- Design explorer updates
  Auto-hierarchy building while editing
  file detection bug-fixes
- RTL synthesis
  FSM bug-fixes related with redundent states, state extraction
  FF control logic extraction bug-fixes
  crash bug-fix related to Chinese language
- user manual update

[04/11/2019]  V2.6.2  Fast Track Build 041119
- Resolved a routability issue for router -extra mode
- Fixed a resource report problem related with IO register for 3D devices
- Error checking for multiple pin assignment to one port
- Add GUI support for bitgen -config option
- Design explorer update for stablity

[04/10/2019]  V2.6.2  Fast Track Build 041019
- Add -config option for bitgen, e.g. -config master_spi_port=disabled|ext_crystal=on

[04/09/2019]  V2.6.2  Fast Track Build 040919
- Fixed pin assignment issue of placing dual-purpose IO with IO Register.
- Display running environment information at HqFpga startup.

[03/27/2019]  V2.6.2  Fast Track Build 032719
- By default disable clock divider in RTL synthesis

[03/21/2019]  V2.6.2  <=============================================
- Refined Routing parameters
- Refined delay modeling
  Updated carry chain cell delays
  updated SLICE_ABCD delays

[03/14/2019]  V2.6.1 Fast Track Build 031419
- Renamed device SL2-25E-F213 to SL2S-25E-U213
- Speeded up HqInsight parsing process
- Bitgen set01 support

[03/06/2019]  V2.6.1 Fast Track Build 030619
- Embedded SDRAM support for 25K BGA213 device

[03/01/2019]  V2.6.1 Fast Track Build 030119
- Fixes JTAG pin issue for 25K BGA213 device
- Refines design.looptdo flow.

oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
[02/23/2019]  V2.6.1
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
- Packer update for force-absorbing core FF to IOREG
- Design dexplorer update for Linux
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

[01/31/2019]  V2.6 Fast Track Build 013119
- Packer update for absorbing tri-state control FF to IO logic
- Bitgen bug fixes related with OSC/POR... etc
- Router update for user specified SCLKs
- STA update for better logical/physical pin matching
- Minor timing model updates for IO logics

[01/05/2019]  V2.6 Fast Track Build 010519
- Support of SL2-12X-6F256
- Integrates design explorer

[12/18/2018]  V2.5.10 Fast Track Build 121818
- Router extra-mode update for IOLOGIC compat issue.
- RTL synthesis update for non-uniform-shape RAM mapping
- HqInsight viewer update for unreachable characters

[11/21/2018]  V2.5.10 Fast Track Build 112118
- MULT8/ALU24 full support
- Routing runtime reduction

[11/08/2018]  V2.5.10 Fast Track Build 110818
- HqInsight Update
  Support of mixed primitive in Verilog files
  Fixed crash problem when Verilog file contains non-ascii characters
  Better check of file/directory permission

[09/30/2018]  V2.5.10 <=============================================
- IpCreator : fixes a bug related with data width 16 for PDP/DP EBRs
- Router : reduces runtime by ~10%

[09/30/2018]  V2.5.9  <=============================================
- IpCreator updates
  SP-EBR IP refine
  EBR init file handling refine
- Router
  refine user-specified SCLK constraint hanlding

[09/22/2018]  V2.5.8  <=============================================
- IpCreator updates
  EBR initialization file handling
  IP configurer update for EBR
  refine file chooser
- HqInsight updates
  Refine handling of multiple modules in one file
- HqFpga main program updaes
  Router updates of user-specified SCLK contraints
  ECO router updates
  12K device QFP package pin update

[09/10/2018]  V2.5.7  <=============================================
- Bitstream downloader update
  multi-language support, UI layout refine, ...etc.
- Fixes several issues in router
  related with secondary clock assignment, DQS pin, ...etc.
- Fixes resource report issue for 12K/25K Q176 packaing
- Updates Sealion simulation model

[08/30/2018]  V2.5.6 Fast Track Build
- more netlist integrity checking in physical netlist reader
  added -strict option in corresponding command
- add lut function/equation support

[08/22/2018]  V2.5.6 <=============================================
- 25K support stablized.
- Fixed mapping crash problem for windows x6a4 platform
- More legalization check for IOB
- GUI updates
  HqInsight bug-fix for more than modules in one file
  Fixed several IP Creator regression issues
  Shrink HqInsight file sizes
  Hqui status control updates

[08/09/2018]  V2.5.5 Fast Track Build
- Fixed 25K device CIBTEST bitgen issue
- Fixed auto-clock derivation for 25K PLL
- Updated IP Creator for 25K PLL

[08/06/2018]  V2.5.5 Fast Track Build
- Fixed 25K device CIBTEST placement issue.

[08/04/2018]  V2.5.5 Fast Track Build
- 25K device bitgen: fixed issue related with DQS and riologic on left pic
- Placer: fixed long runtime issue for large chain
- GUI: fixed device name issue, fixed netlist viewer column selection issue

[08/02/2018]  V2.5.5 Fast Track Build
- Fixed DSP bitgen issue
- Bitgen update for 25K PLL CLKO5
- JTAG support for Q176 and F324 packages

[07/30/2018]  V2.5.5 Fast Track Build
- Fixed a regression problem in design.looptdo

[07/28/2018]  V2.5.5 Fast Track Build
- Updated pinout for 12K/25K eQFP 176 packaging.
- updated downloader for PS mode

[07/26/2018]  V2.5.5 Fast Track Build
- Fixed a port name matching problem caused by bus and single-bit name

[07/20/2018]  V2.5.5 <=============================================
- Optionally set unused IO to high impedance state
- Integrates netlist viewer
- Router QoR improvement
- bit2svf for 25K device
- Fixed several IP Creator bugs

[06/30/2018]  V2.5.4 <=============================================
- Update SL12K Q176 pinout based on 062118 revision
- Update of extra-mode router for routability

[06/21/2018]  V2.5.3 <=============================================
- Suppor for SL2-25E-F324/256, SL2S-25E-E176
  With pinout table 0618
- HqInsight update of combining debug and download cable
- Fixed SL25 resource report issue
- Add DSP infer/map option on GUI
- Update user manual for IP Creator

[06/06/2018]  V2.5.2 <=============================================
- IP Creator stable
- Refined IPGEN with meaningful names
- Update for SL25 F324 package

[06/06/2018]  V2.5.1 Fast Track Build
- support for xsMULT9, xsALU54, xsALU24
- initial support for SL25 F324 package

oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
[05/27/2018]  V2.5.1
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
- Initial IP Creator support
- DSP parition update for sealion
- routing update for 25K
- pinout update for 25K
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

[05/04/2018]  V2.4.7 Fast Track Build
- Honor clock assignment constraint for extra-mode router

[04/29/2018]  V2.4.7  <=============================================
- Add MULT9/ALLU24 support
- Add Test logic support
- FIFO packing/bitgen updates

[04/09/2018]  V2.4.6 Fast Track Build
- fix DQM@SDRAM direction problem.

[03/29/2018]  V2.4.6 Fast Track Build
- legalization for DQS.DQSI connection to GND

[03/28/2018]  V2.4.6 Fast Track Build
- Update Q176 special port naming convention for SDRAM
- Update router PCLK auto assignment


[03/25/2018]  V2.4.6 Fast Track Build
- Update pin name handling for SL2S
- add SL2S missing package pins
- ROM packing bug-fixes

[03/13/2018]  V2.4.6 Fast Track Build
- update MULT infer/map for default CE connection to 1 rather than 0
- PLL25K bitgen support

[02/07/2018]  V2.4.6  <=============================================
- add WAKEUP support
- Reduce extra mode router runtime by 60%, with ~1% FMAX degradation
- Update tdoloop accordingly.

[01/26/2018]  V2.4.5  <=============================================
- Update GUI progress for placement and routing
- Report and check resources overflow at beginning of placement
- Packer update for IOLOGIC CE

[01/22/2018]  V2.4.4  <=============================================
- Reduces runtime by 50% for extra-mode router
- Fixes a bitstream generation issue related with ECLK
- Deployes new bitstream downloader

[01/18/2018]  V2.4.3  <=============================================
- Improves routability of extra-mode routing
- Fix a signal probing issue realted with probing one net/signal to two or more
  package pins

[01/15/2018]  V2.4.2  <=============================================
- Fix a routing bug related with ECLK under extra mode
- Fix routability regression issue

oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
[01/12/2018]  V2.4.1
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
- Add signal probing support.
- fix RTL false comb-loop issue
- enhance eco.route/design.route -effort extra
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

[01/04/2018]  V2.4
- add design.route -effort extra support
- add design.looptdo for iterative timing driven optimization
- HqInsight : fix issues related with uniquification

[12/16/2017]  V2.3.5
- QoR imporovement for Placer/Router
- Speedup ECO on Win32 platform
- Include all fast-track updates.

[12/09/2017]  Fast track build (V2.3.4)
- fix CLKOPD@PLL -> PCLK1/3 direct route issue
- fix PCLK delay calculation minor issue.

[12/01/2017]  Fast track build (V2.3.4)
- DCMA router support

[11/27/2017]  Fast track build (V2.3.4)
- fix bitgen bug for DQS1
- packer update to absorb inv into CCU
- router fix for multi-driven fuse issue.

[11/21/2017]  Fast track build (V2.3.4)
- add support to set un-used IO pull mode

[11/15/2017]  V2.3.4
- Support SL2SD device (3D packaging SL12 FPGA with SDRAM)
- Fixed a bug when handling distributed RAM
- Fixed a bug in debug mode (check xdata, timing_derate)

[10/20/2017]  V2.3.3
- Update new timing numbers realted with M0/1 -> OFX0/1 (20171016.tm)
- update GUI to remove no-use Nxx files

[09/19/2017]  V2.3.2
- Updated new timing numbers
- add user location support for DCLK(H1) MSEL2/1/0(G12/H12/H13)
- SCLK update

oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
[07/22/2017]  V2.3.1
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
- Integrates HqInsight (On-chip debugging)
oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

[07/01/2017]  V2.2.4
- Update GUI interface with downloader
- ECO update
- Standalone router delay calcuation

[06/15/2017]
- Updated clock delay numbers for SL12/25
- GUI add downloader button

[05/24/2017]  V2.2.3
- Update for GDDR 2x/4x, Video Inferface 7:1 support
- Bitgen update for rbin and bin
- GUI fresh-reun whole flow.

[04/23/2017]
- Updated DQSDLL auto-placement based on DQS
- various updates for SL25K

[03/11/2017]
- Initial support for SL25K

[10/09/2016]
- gbb update from Xist
  timing derate 0.88
- placer update for F/Q/OFX -> M0/1 routing restriction

[08/20/2016]
- add DCMA support
- timing derate from 0.75->0.85

[08/03/2016]
- add timing derate support
- add bitgen options on GUI
- fixed problem : CLKIO->PCLK through general routing resources
                  PCLK0 bitgen issue

[07/27/2016]
- update bit2svf based on Xist's gensvf_reverse_1125.pl file

[07/25/2016]
- update bit2svf for sealion rev1 device

[07/23/2016]
- support for sealion rev1 device (v02v1)

[06/25/2016]
- refactor placement and routing
- Internal-external primitive name support
- enhanced unrelated packing
- MLO bug-fix
- timing-driven logic optimization flow update

[05/18/2016]
- Generate SVF file when generating text-bit file

[05/09/2016]
- Add an routing option to use wrap-around x6/x2 routing resources as much as it can

[03/05/2016]
- Fixes dummy-aload false error-out issue for customer design
- Improves delay calculation

[03/03/2016]
- Add support to WindowsXP Win32 system

[12/31/2015]
- Fix PLL OPD routing problem

[12/29/2015]
- Fix duplicated routing switch names in Nxx file
- Fix GUI -loc -sdf setting problem
- Fix SDF/Verilog name matching issue.
- Fix GUI LVDS25 result in LVCMOS25 in Nxx problem
- Adjust timign driven strategory. Synthesis honors FMAX setting. User timing
constraints only affects PAR.

[12/29/2015]
- update router to reduce runtime
- Update GUI on PC/TC editor