******************************************************************* * * HqFpga-XIST V2.11.2 Release Note * ******************************************************************* * UPDATE HISTORY * [10/16/2021] V2.11.2 <============================================ - Downloader Fix stability issue in Windows7 platform. - Technology Mapping Fix a corner bug in LUT-Pack related with const zero - HqInsight Fix issue related with Verilog function. - IP Creator Fix issue related with floating number (e.g. user input 19.2 becomes 19.200004 internally) - Placer Improve congestion handling for Sealion devices [10/05/2021] V2.11.1 <============================================ - Device update Add ** Seal(28nm) 30K Device support ** SA5Z-30-D0-8U324 SA5Z-30-D1-8U213 SA5Z-30-D2-8U213 - RTL synthesis Refine FSM output logic optimization Update for initial value of dynamic shift registers Fix a bug in technology mapping related with combinational loop Fix an exception when prameter value is empty string - HqInsight hierarchical name related update for signals Add bus grouping for signals in netlist debugging Fix signal selection dialogbox issue - IP Creator Fix serveral issues in EBR/FIFO IP generation. - Design Interface Add frequency divider mode for OSC. [09/28/2021] V2.10.5 Fast Track Build 092821 - Placement Refine LUT/LE packing for seal device Refine detail pack resource report [09/27/2021] V2.10.5 Fast Track Build 092721 - Seal device support update Support 4mA drive for SSTL18_I IO_TYPE - Seal Router Reduce runtime for long wire Routing tree statistic information print - Downloader update Add two new FLASH IDs File history support [09/26/2021] V2.10.5 Fast Track Build 092621 - Seal Router Runtime reduction related with expected cost estimation. - Downloader Update to version 1.8 - HqInsight Fix signal selection dialog box regression issue. Temporary file handling related update. [09/23/2021] V2.10.5 BETA092321 <=========================== - GUI Fix resource report issue related with EBR 9k/18k and Co-packaged DDR-IOs. - HqInsight Fix a couple of stablility issues. [09/17/2021] V2.10.5 Fast Track Build 091721 - Device modeling x1 interconnect delay value refine due to Metal3 issue - ECO Support for blocking certain area on chip. [09/13/2021] V2.10.5 Fast Track Build 091321 - Bitgen for Seal devices Fix issue related with ALU24 PLL OS trim fix - Placer IO TYPE update for seal device [09/08/2021] V2.10.5 Fast Track Build 090821 - Place&Route Fix issues related with clock assignment without clock id Refine clock net routing related with ECLKSYNC/CM3/DLL etc. - Packing Legalize CM3 *CLK->GND connections [09/06/2021] V2.10.5 Fast Track Build 090621 - Routing Simple-resolve CE/Reset -> PCLK conflict (only one of them can be routed to PCLK) - Placement update related with DLLDEL-DDRDLL [09/03/2021] V2.10.5 Fast Track Build 090321 - Seal SA5Z-30 device related updates Placement: Refine IOTYPE support for all banks Routing: fix delay calcuation issue for long wire mid fanout - IP Creator Support high performance low jitter feature for Seal PLL [09/01/2021] V2.10.5 Fast Track Build 090121 - Seal 30K Production device related updates Bitgen : fix CRC/compress related issue Placer : Fix issue related with PLL-CM3 Router : Fix DDRCTRL clock routing issue Donwloader update [08/30/2021] V2.10.5 Fast Track Build 083021 - Seal 30K Production device related updates Bitgen update on compression, CRC and padding DQSBUFM supports 4 more paramerters Routing: fix control net routing to PCLK issue Placement: fix DDRDLL clock input model issue - RTL synthesis Fix a corner comb-loop issue in technology mapping Initial value updates fro shift register. - IP Creator Seal EBR IPGEN update Seal DSP basic IPGEN support - HqInsight Improve hierarchical name handling Improve bus name handling in netlist level debug [08/25/2021] V2.10.5 Fast Track Build 082521 - RTL synthesis Fix a bug in tech-mapping related with combination loop Refine FSM output logic optimization - Downloader Fix an issue related with 7K extenal flash Update for Seal SA5Z-30 devices. [08/23/2021] V2.10.5 Fast Track Build 082321 - Router Refine delay estimation for SA5Z-30 devices - Placer Fix DSP regression issues for SA5Z-30 devices - RTL synthesis Fix assertion issues related with parameter of empty string value Fix port name matching issue for single-bit port with bus name format - IP Creator Enable PLL IPGEN for Seal 30k production (SA5Z-30) devices [08/18/2021] V2.10.5 Fast Track Build 081821 - Placer Disable unnecessary dedicate connection checking for PLLREFCS of Seal devices. [08/17/2021] V2.10.5 Fast Track Build 081721 - IP Creator Update Seal IP of FIFO related with read width 36 Update FIFO simulation model accordingly [08/12/2021] V2.10.5 Fast Track Build 081221 - Placer Update FIFO support for Seal 30Z devices - RTL synthesis Fix an assertion issue in shift register handling [07/31/2021] V2.10.4 BETA073121 <=========================== - Production device support SA5Z-30-D0-8U324, SA5Z-30-D1-8U324, SA5Z-30-D2-8U324 - Refine timing modeling - RTL synthesis Fix a corner bug in MUX optimization for sealion family Refine message prompt for invalid decimal constant Refine Pseudo dual port RAM mapping Fix a corner bug in ROM infer/map - Placement&Route Ehance timing driven optimization Refine handling of SRL16/MULT/PRADD CM3/PLL related updates [07/14/2021] V2.10.3 FT071421 - Placement Fix issue related with SLICEM counting Fix logic error related with unrelated packing - Design interface IO related Legalization update for netlist generated by third-party tool - Packing Fix INV pack issue for seal devices Legalization of IOLOGIC unroutable GND input - IP Creator Update FIFO with 32bit data with and with 16K address extension - Downloader Combine Seal and Sealion downloader Update downloader for Sealion 7K device Add support of bin2burstsvf - Device modeling Update timing info for DQS and some interconnect wires [06/26/2021] V2.10.3 BETA062621 <=========================== - HqInsight Support for seal device - IP Creator Update for EBR/FIFO 16/32 bit data [06/09/2021] V2.10.2 FT060921 - Seal device realted updates Fix regression issue of JTAG bitgen Update Verilog simulation models of PLL and JTAG Restructure Verilog model from one big file to multiple files - RTL synthesis Fix FSM bug related with invalid and initital states Refine message prompt related with latch, port width mismatch, mult-driven, ...etc. [06/03/2021] V2.10.2 FT060321 - update timing data from the file swith_box_bbb.xlsx [05/31/2021] V2.10.2 FT053121 - Fixed min/max value problem for DDRCTRL and CM3 [05/28/2021] V2.10.2 FT052821 - Seal DSP SL_LOAD port support - Seal simulation model updates for PLL, FIFO8K and PREADD [05/21/2021] V2.10.2 FT052121 - Seal support update Updated simulation model for IOL with EDGEMON Support FIFO8K wide mode Support packing CLOCK INV [05/21/2021] V2.10.1 BETA052121 <=========================== - Device modeling Update cell timing parameters for DDRCTRL Simulation model update for IOREG with EDGEMON - Packing Support FIFO8K with wide data width [05/15/2021] V2.10.1 FT051521 - Packing Update for ODELAY control signals Refined absorbing CLKINV to IOReg - Router update for assigning Reset net to PCLK related with DDRCTRL RST_B port [05/13/2021] V2.10.1 FT051321 - Seal bitgen PGNG fuse update SLICE O5X select fuse update - Seal Packer update for IO Latch - IP Creator Add EBR/FIFO IPGEN for seal devices [05/11/2021] V2.9.9 FT051121 - Packing Fixed a bug related with LSR port of OSHX/TSHX - Updated cell timing models for CM3 add conditional timing arcs for {PLL_USRCLK PLL_OUT CLK_PAD CIBCLK} [05/10/2021] V2.9.9 FT051021 - Updated cell timing models for CM3 add clkset for {PLL_USRCLK PLL_OUT CLK_PAD CIBCLK} [04/30/2021] V2.9.9 FT043021 - Initial external VREF support - Timing model Fixed interconnect delay model issue related with CTRL/GFAN Fixed clock auto-generation issue related with CLKDIV - Seal 30K production update [04/23/2021] V2.9.9 FT042321 - Seal 30K production initial support - Updated cell timing models for CM3 and DDRCTRL MPW version - Updated simulation models for : High spped IO (e.g. DDR2 memory) interface primitives True dual port BRAM 16K (xsBRAM16KTD) [04/18/2021] V2.9.8 BETA041821 <=========================== - Slice timing arc/value update CLK->BMUX timing arc Asynchronous recovery/removal reset/set-to-q Seq2comb timing arc - Routing Limit logic_outs fanout - More DRC check Illegal PAD connection between two PIOs IO Standard conflict of paired pins ECLKSYNC overflow - GUI Fixed issue related with empty file in design explorer - Others DQSBUF/PREADD support update Regression issue fix [03/27/2021] V2.9.8 BETA032721 <=========================== - Device update Add param WRITE_LEVEING support for Seal DQSBUF - Downloader Update for 30K MPW device - GUI resolve issue of wrongly turning on LE level packing/placement in multiple device run (V2.9.8 FT032521) - Placer Correct problem of PT7A/B/C/D bank number for 30K device - Packing/Bitgen Updated parameters (PHASE_SHIFT, WRITE_LEVELING, ...etc) for IODDR cells (V2.9.8 FT032421) - Seal 30K PIO PG NG fuse support With GUI updated - Seal mpw ebr 72-bit PDP EBR support (V2.9.7 FT031621) - Bitgen Fix PLL Refclk4 typo MPW IMUX21 and BYP2 share fuse - Placement Refined set_global_attr by considering VCCIO - Packing Fixed ODDR71 related issue - RTL synthesis Fixed a bug in FSM extraction related with decoder. (V2.9.7 FT031121) - RTL synthesis Updated INIT value handling for Seal device Fixed a corner issue related with string parameter using ?: operator - Routing Fixed DCS-SEL routing fail for Seal 100 device - Constraint Support ioh.set_global_attr -unused_io tie_z for seal device - (V2.9.7 FT031021) - Routing Fixed a bug for DCS-SEL CIB clk_cs_1/clk_cs_3 - ECO Fixed a bug related with TIEOFF in signal-probe. Refined for X4 test pattern Fixed issue related with EBR input. (V2.9.7 FT030921) - ECO Initial signal probe support for seal device (V2.9.7 FT030521) - Clock TAP index constraint support : phycst.net.set -index -tapidx - Bitgen CIBTEST support update DCS support update (V2.9.7 FT030421) - Seal EFB support refine (V2.9.7 FT030221) - Placement Fixed PIO2PCLK clock counting issue (issue from Guowei) Fixed PIO2ECLK dedicated connection issue (issue from Huifen) - PLL IPGEN update for CLKOS3_FRAC_DIV support (req. by WenQin) - Bitgen : DSP dyn_opr_inv fuse invert for mpw (V2.9.7 FT030221) - PLL IPGEN update for trim and interanl-feedback support, for sealion and seal devices - Routing bug-fix for DDRCTRL of Seal 100K device - Seal CIBTEST intitial flow support [02/26/2021] V2.9.7 BETA022621 <=========================== - PLL IP Creator update for RESET/STDBY/CLKISEL/DPHASE/FBMODE - PLLREFCS support update (V2.9.7 FT022521) - Packing Prevent dropping user contraint when doing LUT input redundency removal - Routing Support disabling tiles for routing ECLK bridge bug-fixes for sealion devices [02/23/2021] V2.9.6 BETA022321 <=========================== > Seal IP Creator refactor > Incorporated FT021921 update - Bitgen bitgen "ctrl0" update for Seal 30K devices - Placement Fixed global net assignment win/linux difference issue [02/10/2021] V2.9.6 BETA021021 <=========================== - Placement Fixed issues related with SLICEM carry chain placement Fixed issues related with PCLK assignment Fixed several functional issues in LE packing Enhance DSP support related with SIGNED/SOURCEA/B ports - Routing Fixed dedicated clock-to-PLL input routing error. - Bitgen/Downloader Fixed extra leading 0000 issue in bin file generation for 30K devices Support 30K devices. [01/24/2021] V2.9.6 BETA012421 - Initial beta version for Seal device support.