******************************************************************* * * HqFpga-XIST V2.14.3 Release Note * ******************************************************************* * UPDATE HISTORY * [11/06/2023] V2.14.3 <============================================ - New device support SA5T-100-D0-8UA324C SL2-25E-8FA256CI - Place & Route ** Refine routing switch fanout control ** Fix placement-fail issue due to non-clock pad driving PLL. Refine QoR for Seal 100K device Placement legalization update for MULT18-MULT9 site conflict Enhance GND/VCC net routing for Seal device Fix multi-driven issue when a PLL output clock drives a LUT input for Seal device. Refine packing to get higher resource utilization for Seal device Fix X2 type typo for seal 100K device Refine EFB support for Seal devices - RTL synthesis Refine port-width mismatch handling in module instantiation Enhance checking and error report on mixed blocking and non-blocking assignment Fix sign/unsigned issue related with $clog and blackbox instance parameter. fix issue related with big number (> 32bit) Fix MUX optimization issue related with data and select coming from different module Support of synthesis directive of RAM style Add support of automatic gated clock conversion Downgrade sparse control set for FFs Fix stuck issue related with CE/data co-optimization Enhance constant evaluation related with range update in function call Update EBR inference/mapping for Seal device Better support for byte-enable Refine message prompt Enhance EBR36 support for seal device Support depth reduction for EBR with byte-enable Fix bug related with output register handling Enhance X7 RAMB->Seal EBR retargetting support DSP inference/mapping updates Fix issues related with ADD->MULT chain operation Fix MULT->REG merge related issue Fix issues related with signed/unsigned extension Fix issues related with legalization Fix issues causing logic optimization crash - IP Creator Fix Cordic IP bugs GDDR IP: fix missing module name issue EBR IPGEN Fix issue related with distributed ROM when depth is no more than 8 Fix distributed RAM/ROM initial value issues. Fix bugs related with address connection of PDP EBR for Seal device Fix ECC connection bug for Seal 100K device Fix abnormal instance name issue CORDIC IP: fix issues related with floating number range. PLL IP: Change frequency lock accuracy default value from 0 to 2 limit upper bound of extern feedback frequency. Update document for 8b10b, CORDIC, FFT IPs Divider IP: fix a bug failing in loop mode DSP IP: Fix CLK/CE/RST ports missing issue under certain configuration Fix message prompt issue related with Non-ASCII characters - HqInsight Add VIO support Fixed issue related with empty string parameter Fix signal mark issue related with switching sample clock Fix issues when clicking instrumented signal list. - Bitgen Refine download speed for Seal 30k device Support -sspi -i2c -trans_mode option Force enabling compress mode for bin file generation for Sealion device Fix FIFO EMPTY flag related issue Support SED AUTOFIX feature - Downloader Update for Seal 100K device Add DNA info for Seal 50k/100K devices Show device package info after detecting device Add status detection for burst mode downloading Fix unexpected reset issue when detecting Seal 30k device Support for merging uncompressed bin files Improve error handling/prompt. Display bit/bin/xfb file information when downloading or converting files Support for downloading bit files directly to flash. - Design interface Enhance region constraint support. More strict checking on bank VCCIO for seal devices Fix issues in simulation model files for Seal device Fix equivalent LUT count issue for distribute RAM in Seal device Refine IO report Refine instance/net/view/port name generation Refine EDIF reader for better interface with 3rd-party synthesis tool [06/19/2023] V2.14.2 <============================================ - Device support Support new devices SA5T-100-D0-8F676 SA5T-100-D0-8H676 SA5Z-50-D0-8U196 SA5Z-50-D0-8AF484 Update timing value of EBR,FIFO,IOL,DDRCTRL for Seal 30K/100K devices - RTL synthesis Preliminary support to System Verilog Fix a corner issue in combinational logic optimization related with bidirectional port Fix bug in MUX optimization related with X (dont-care) value Refine message prompt related with empty module, range-select, mixed blocking/non-blocking assigns, latch-from-mux, ROM reduction, ...etc. Enhance FF simplification on CE and data. Fix stuck issue on handling large MUX Refine IO-register init value support Refine big multiplication operator support Fixed a bug related with signed multiplication Fix DSP MG issue related with A*A Refine RAM inference and retargeting Fix RAM partition issue for Seal 100K MPW device Support RAM with ByteEnable Fix bugs related with RAM INIT combine Refine wide-data mode BRAM support Update RAM infer so as not to generate dummy generate dangling net Support RAM infer with more complex control logic (REN/WEN/WE/RE/CE/RS) Refine RAM inference related with different REN and WEN Enhance RAM inference related with various control type and priority : WE,RE,CE,SRS,...etc Fix RAM inference issue related with 36-bit EBR of 100K MPW device - Place & Route Control routing switch fanout to ensure signal integrity for Seal device Improve FMAX ~3% with ~10% runtime reduction for Seal device Fix wrong ECLK connection for 100Kprod device Fix ECLK routing issue fro 100Kprod device Enhance DLLDEL/DDRDLL placement Fix an issue related with TPLL->TECLK connection for Seal 50K device Refine dedicated connection vs PCLK connection related with PLL and ECLKSYNC Fix an issue related with gated clock. Fix routing issue related with constant clock net for SERDES in Seal 100K MPW device. Enhance bank vccio checking for input ports Remove redundant DSP CLK0/1 connections. Improve routability for design with very loose timing target, for Sealion devices Fix issue related with SERDES without explicit output - IP Creator EBR_PDP IPGEN update for Seal 100K MPW and production devices: Fix error if data width>=36 ECC ports for 100k PROD ebr_pdp IP 32k sp_rom Fix the issue importing IP generated by older version of HqFpga PLL IPGEN updates Add User-customized feedback option Display result from %0.3f -> %0.6f PLL IPGEN : use internal feedback by default. Fixed issue related with dummy IPGEN operation Add EBR IP for 100K PROD devices Divider IP update to support larger width range CM3 IP update related with AHB CM3 IP update by removing clock pins with side effects - HqInsight Initial VIO support. Enhance source-file-change prompt to avoid being ignored Fix a regression issue : pop up error dialog when creating a new insight project Fix an issue stuck at close-and-save Fixed issues related with $readmem with empty string check Fix an issue related with parameterized module instantiation, which may cause signal missing Fix issue related with $random Support break execution of FPGA implementation Fix syntax highlighting issue relate with file synchronization - GUI Enhance usability for ChipViewer Support IPAD/OPAD location selection for 100K devices Fix IO editor unset-location issue. Add I(industry) to condition selection list for Sealion 5K devices. - Downloader Fix pop-up window issue when "Update MCU Version" in Help menu Add new command line to append dummy to bin file Support merging FPGA bit and CM3 bin file with encryption - Bitgen Speedup bitstream generation for large devices Support SADC OT_PD_ENABLE feature for Seal device Fix issues related with SSTL12/HSTL12. - Design Interface Support LUT/FF location constraint for Seal device Add more parameter checking on PLL, delay cells for Seal device Update Verilog dumper and simulation models for P&R Result Fix multiple run crash issue in EDIF flow Check PLL feedback connection Add DDRCTRL simulation models Enhance differential IO handling and checking. Fix a corner issue of not reporting output delay value. Refine IO report [02/19/2023] V2.14.1 <============================================ - Device support Support Seal 50K device (SA5Z-50-D0-8AF484) Update EBR/ALU/MULT9/CM3 timing information for Seal 30k/100k devices. Change default IO_TYPE of Seal devices from LVCMOS25 to LVCMOS18 except for Seal 30K device - RTL synthesis *Verilog parser update Enhance constant evaluation related with string, parameter, integer part-selection, function/task, generate statement. Fix issues related with localparam, multi-line strings, open parameter binding, generate statement, array assignment. enhance real-type number support in parameter binding, function input and reg/wire assignment Fix issues related with index-out-of-range in generate statement. Support expr caculation for functionCall and real parameters Preliminary support to system verilog Refine FSM optimization and fix corner bugs Support infer/mapping of RAM with ByteEnable - Place & Route *Refine routability of extra-mode router for Sealion device Fix pclk/sclk assignment issue in normal-mode router for sealion device. Fix stuck problem due to all-constant-iput LUT generated by third-party tool Fix a issue related with packing MUX8 without LUT connection for Sealion device Enhance carry chain apacking for Seal devices Fix long runtime issue when routing big fanouts control nets. Fix clock assignment issues for Seal 50K and 100K MPW device Fix issue related with MULT9 in Seal 100K and 50K device Enable the X4/X5/X71 single-end PIO mode for Seal devices. - HqInsight *Support of continous triggering Fix color display issue related with part-select signal Fix an issue that symbols in block comment can be wrongly labeled - IP Creator Add 1D fileter IP for Sealion device Update divider IP Add sample files for Gernic DDR IPs for sealion device Add document to several IPs Update PLL IPGEN to support lowest PLL clock input frequency of 6MHz Fix EBR IPGEN issues related with data with=(9,18) and byte-enable - Design interface Fix issue of retargetting BlockRAM with synchronous set Refine message prompt for wrong PLL configuration Refine EBR retargetting for seal devices. Add SERDES/DDRC resource report Refine checking for potential clock issue. Update simulation models for EBR/FIFO32 related with ECC functions. Fix EDIF reader crash issue related with port array property. - Downloader *Add support to Seal 50K device Support x2/x4 file conversion for Seal 100K device Refine reading of FLASH ID Support downloading xfb file with chinese path name for 5k/7k devices Support downloading bit with mask - Bitgen Fix corner issues for Seal 100K device - GUI Add options for system verilog, shift-register and user customized settings. Enhance chipviewer for seal devices. Fix launch-fail issue in English language OS. [11/05/2022] V2.13.7 <============================================ - Device support Fix a corner issue related with CLKIO-to-ECLK for Sealiong 12K/25K devices. Seal 100K MPW device support update related with timing model, routing resources and bitgen - Place&Route Fix a corner routing issue happened in multiple run (e.g. in GUI environment) Fix an issue when trying merge SLICE with latches for Seal devices. - RTL synthesis Fix RAM partition issue in RAM inference for Seal devices. Refine logic and MUX optimization to reduce runtime of corner cases. Refine shift register dedicated chain connection for seal devices Fix false index-out-of-bound alarm in Verilog parser. Minor update on resource sharing related with adaptor. - Design Interface Refine resource report for BlockRAM and DSP/EBR Update EBR32K and FIFO16K simulation model for seal devices Add xsINVSA(inverter) primitive to seal device family. Fix unusal extra-large UDB/dump file issue. - Main GUI Refine submodule EDIF file search behavior Fix an issue when source file list may be cleared unexpectedly in rare cases. Fix EDIF file path related issues Remove two global settings which are rarely-used and error prone Add global settings for sepcifying naming style for auto-generated clocks Fix a bug in reset-to-default action. Speedup top module detection for Verilog file with protected region. - STA Fix an issue in slack report related with '[]' in generated clock name Fix a corner issue related with falsepath of a clock with generated clocks. Fix a coner bug related with create_clock on an unconnected pin Fix auto clock detection issue in Sealion 3D package with DDR2 RAM Fix FMAX report problem under hold analysis mode. Fix FMAX report bug related with set_max/min_delay constraint. - HqInsight Support aways-wait function. Add tip for signal searching. Refine flow control when there's error in source file Fix a bug when changing sample depth Fix a corner bug related with using a signal in sub-module as as sample clock - IP Creator Add CM3 IPGEN for Seal 30K devices. Update Aurora 8b10b, CORDIC and FFT IP Refine error checking and report Fix a bug introducing div=129 in PLL IPGEN Unify save/load operation for all IPs Add more exception condition checking. - Design explorer Fix design hierarchy display issue related with multi top modules and generated instances [08/26/2022] V2.13.6 <============================================ - Device support Add Seal 100K device support (SA5T-100E-8F676) DSP REG2 BYP mode support for Seal devices Add 4 dual-purpose pins for Sealion 7K devices: nCONFIG(PROGRAMN), nSTATUS(INITN), CONF_DONE(DONE), nCE(SN) Remove unsupported IO Standard LVDS33 from Seal devices. Fix corner bitgen issues related with T/BECLK1 for Sealion devices Fix Sealion 5K PB37 PIO input delay config issue Support 1.35 vccio for Seal devices. - HqInsight New integrated UI (instrumentor+implementation+interactive debug) Support open waveform with style setting file (.gtkw) Fix a problem related with parameterized module and top-level-sample-clock Fix problems related with relative file/directory path handling - IP Creator Fix FIFO IPGEN issue related with 16bit depth 32bit width Fix an issue related with ROM/RAM initialization for HDL-IP PLL IPGEN update related with xsPLLREFCS PLL IPGEN update for auto feedback clock selection - RTL synthesis Fix a bug in FSM extraction. Fix a bug in shift-register infer related with same-clock check Fix a crash prolbem when reporting an out-of-index error. Fixed a bug related with $readmem and parameters in module instantiation. Refine EBR infer/map for Sealion devices Fix ROM init-data related issues. Fix ROM datawith optimization related issues. Retargetting update/bug-fixes related with DSP/EBR - STA Fix a FMAX report issue related with CM3 Add STA slack support (ta.slack.report) after routing - Place & Route Fix a clock routing issue of Sealion device - GUI refine message flush behavior upon error/warning - Desing Interface Update EDIF reader to handle multiple view in one cell. - Misc User manual update to v2.4 [06/18/2022] V2.13.5 <============================================ - Device update Change all "I" suffix to "CI" in device name for all devices Refactor SADC support for Seal 30K devices - IP Creator Add Aurora 8b/10b IP for Sealion devices Add DDR2 memory controller IP for Seal devices Add LFSR IP for Sealion and Seal devices Refine 1D_FILTER ASYMMETRY PARALLEL 1-channel mode Refine shift register IP Refine CORDIC IP Add sorting function in IP browser Fix bug related with port inactive condition for instantiation - RTL synthesis Support encryption/decryption based on IEEE 1735(V1) standard Add stricter checking on primitive parameters Fix memory leak issues related with generate statement - Place & Route Update physical constraint support for carry chain of Seal devices Fix carry chain legalization of Seal devices Fix routing issue related with OUTCLK/MTX_CLK pins of CM3 core in Seal devices - STA Fix asynchronous timing arc related with FIFO E/F flag output [05/04/2022] V2.13.4 <============================================ - IP Creator *Add CORDIC IP support for Sealion devices *Add shift register IP support Add new TAB page to classify IPs by name Improve GDDR IP GUI Improve Filter IP related with highspeed mode Fix issue in distributed RAM ouput for Seal devices Fix issue related with single port ROM intitalization data when address width is larger than 14 - Downloader Add support to Seal 100K devices Add support to read DNA information Add support of on-line update to MCU APP and IAP progrogram. - Seal device update Improve VREF constraint support to external DDR RAM Fix issues related with DQSI input + IDDR delay Fix typos in timing model of DQS and SLICE Update timing values of DDRC,CM3,JTAG,EFB,SED,CIBBOOT Update auto-deriving of CM3 PCLK output -HqInsight Fix display issue related with Chinese characters - GUI Fix issues in RTL settings Fix issues related with empty project Fix dynamic linking library missing issue under Ubuntu Linux - RTL Synthesis Improve $signed/$unsigned support Refine MUX optimization Fix corner bugs in MUX optimization Fix a bug in expression optimization related with combinational loop Update primitive library for third-party synthesis tools [04/28/2022] V2.13.3 Fast Track Build 042822 - IP Creator Update CORDIC IP support for Sealion devices Add support to shift register IP Fix distributed RAM output issue for seal devices. - IP Creator Fix issue related with Chinese coding. - Seal device update Support auto-deriving of CM3 PCLK output Update CM3 timing parameters [04/20/2022] V2.13.3 Fast Track Build 042022 - Downloader Add flash ID XT25Q64 = 17600B Modify internal flash delay to improve compatiblity [04/17/2022] V2.13.3 Fast Track Build 041722 - IP Creator CORDIC IP support for Sealion devices - Seal device update Fix DQS and IDDR delay related issue DDR VREF constraint update Update timing values of DDRC,CM3,JTAG,EFB,SED,CIBBOOT - RTL synthesis Refine MUX2 chain optimization Fix a coner bug in MUX optimization - Design Explorer Fix top module related issue when adding file to an empty project - GUI Fix RTL setting related issue [03/30/2022] V2.13.3 Fast Track Build 033022 - IP Creator Fix SP_ROM IP initial data bug when address width is larger than 13 Refine GDDR IP diagram Filter update related with high speed clock port/parameters - Device modeling Fix several minor timing arc issues for DQS/SLICE - Downloader Support Seal 100K devices Support reading of DNA information Support online update to MCU and IAP program - RTL synthesis Refine $signed/$unsigned support [03/20/2022] V2.13.3 <============================================ - Device/package update SL2-25E-8U484 package update (add "D15" pin) Rename SA5Z-30-D2-8U240 to SA5Z-30-D2-8U256 - Place & Route Fix an issue related with redundant LUT equation Routing update for Seal devices Enhance PCLK routing Enhance RST/CE -> PCLK routing Improvement related with complex overused crossing for seal devices Allow comb logic -> SCLK for a user specified net - RTL synthesis XOR optimization enhancement Mutliplier pipelining update. Improves error message report related with array assignment. Change default bus signal name format from %s(%d) to %s[%d] - HqInsight Fix issues realted with BUFG/LUT1-as-VCC/GND in Seal EDIF debug flow Add estimation of debugger IP resource utilization Fix signal name issue related with sample clock - IP Creator Sealion 12k/25k PLL CLKI frequency range fix. DSP IPGEN issue fix : output module name is fixed rather than specified by user Add IP support of Generic DDR, distributed RAM/ROMs Fix a bug when an integer config value is larger than 99 Update 1D filter IPGEN for Seal devices - STA Enhance path-end report by showing logical pin Fix a typo in FMAX report - Device Modeling Fix TCK pin related bug for SL2-25E-8F324 device Fix timing arc issue realted with CM3 MTX_CLK port Update some simulation models of Seal devices: xsALU24SA, xsMULT9SA, xsPREADD9, xsPREADD18, xsPLLSA [01/30/2022] V2.13.2 <============================================ - Place & Route [!!IMPORTANT!!] Fix a DRC problem in Seal device placement, introduced since V2.12.1 - Design explorer Fix a crash issue when click "save" buttton while there's no file is opened [01/22/2022] V2.13.1 <============================================ - HqInsight Support combined conditional trigger Fix trigger position issue Fix an issue related with empty branch statement in Verilog - IP Creator Introduce new .hqip file format to support IP important and to ease IP modification Fix an regression issue in previous build - New device support SL2-25E-8U484I - Place & Route Improve SCLK handling for Sealion devices - Device modeling New IOTYPE support for Sealion devices : MDDR18, MDDR18D Timing parameter update of routing wires for Seal devices - GUI Fix temporary directory permission issue in Linux platform [12/11/2021] V2.12.2 <============================================ - IP Creator Fix bugs in Seal EBR IPGEN related with general mux and duplicated instance name Fix EBR IP config display issue - HqInsight Fix IO type setting issue related with inserted JTAG IOs for seal devices - Main program Auto-register duplication for driver of FIFO asynchronous reset. Add ioh.set_io_type command to set default IO standard (previously always LVCMOS25) Enhance MUXF legalization - RTL synthesis Refine message prompt related with FF asynchronous control signals [11/28/2021] V2.12.1 <============================================ - New device/package support SL2E-7V-8U256I SL2E-7V-8E144I - Place & Route Improves timing ~ 5% for Seal devices, with reduced area and runtime. - Downloader update for Seal devices Merge CM3 and FPGA bin file ADD CRC to CM3 file - IP Creator Seal DSP IPGEN Fix issues related with base DSP IP and 1D filter. BRAM IPGEN updates Support byte-enable for Seal BRAMs. Report BRAM count upong generating IP. PLL IPGEN Fix a corner issue. Support input of 3-digit number on config GUI fix an issue related parameter EN_PHI for sealion 5k/7k devices - RTL synthesis Refine MUX optimization. Enhance BRAM retargetting support. Fix issues related with non-standard mux and shfit register. Message refine related with mux and task - GUI Add selection for device working condition Fix a bug related with special directory name Resolve high CPU usage even when there's no user interaction. Refine usability of design explorer. - Device modeling Fix modeling issues related with I/ODDR. [10/16/2021] V2.11.3 <============================================ - HqInsight Fix stability issue for debugging seal devices Fix an issue related with text encoding - IP Creator IPGEN support for DSP 1D filter. - GUI Support setting seed for placement Fix an issue related with multiple top modules - RTL synthesis Fix a bug of multiplier inferencing for seal devices Refine mode setting for pseudo dual port RAMs - Placer&Route Refine resource reduction support for seal devices. Slight QoR improvement for normal-mode router - STA Fix several corner bugs [10/16/2021] V2.11.2 <============================================ - Downloader Fix stability issue in Windows7 platform. - Technology Mapping Fix a corner bug in LUT-Pack related with const zero - HqInsight Fix issue related with Verilog function. - IP Creator Fix issue related with floating number (e.g. user input 19.2 becomes 19.200004 internally) - Placer Improve congestion handling for Sealion devices [10/05/2021] V2.11.1 <============================================ - Device update Add ** Seal(28nm) 30K Device support ** SA5Z-30-D0-8U324 SA5Z-30-D1-8U213 SA5Z-30-D2-8U213 - RTL synthesis Refine FSM output logic optimization Update for initial value of dynamic shift registers Fix a bug in technology mapping related with combinational loop Fix an exception when prameter value is empty string - HqInsight hierarchical name related update for signals Add bus grouping for signals in netlist debugging Fix signal selection dialogbox issue - IP Creator Fix serveral issues in EBR/FIFO IP generation. - Design Interface Add frequency divider mode for OSC. [09/28/2021] V2.10.5 Fast Track Build 092821 - Placement Refine LUT/LE packing for seal device Refine detail pack resource report [09/27/2021] V2.10.5 Fast Track Build 092721 - Seal device support update Support 4mA drive for SSTL18_I IO_TYPE - Seal Router Reduce runtime for long wire Routing tree statistic information print - Downloader update Add two new FLASH IDs File history support [09/26/2021] V2.10.5 Fast Track Build 092621 - Seal Router Runtime reduction related with expected cost estimation. - Downloader Update to version 1.8 - HqInsight Fix signal selection dialog box regression issue. Temporary file handling related update. [09/23/2021] V2.10.5 BETA092321 <=========================== - GUI Fix resource report issue related with EBR 9k/18k and Co-packaged DDR-IOs. - HqInsight Fix a couple of stablility issues. [09/17/2021] V2.10.5 Fast Track Build 091721 - Device modeling x1 interconnect delay value refine due to Metal3 issue - ECO Support for blocking certain area on chip. [09/13/2021] V2.10.5 Fast Track Build 091321 - Bitgen for Seal devices Fix issue related with ALU24 PLL OS trim fix - Placer IO TYPE update for seal device [09/08/2021] V2.10.5 Fast Track Build 090821 - Place&Route Fix issues related with clock assignment without clock id Refine clock net routing related with ECLKSYNC/CM3/DLL etc. - Packing Legalize CM3 *CLK->GND connections [09/06/2021] V2.10.5 Fast Track Build 090621 - Routing Simple-resolve CE/Reset -> PCLK conflict (only one of them can be routed to PCLK) - Placement update related with DLLDEL-DDRDLL [09/03/2021] V2.10.5 Fast Track Build 090321 - Seal SA5Z-30 device related updates Placement: Refine IOTYPE support for all banks Routing: fix delay calcuation issue for long wire mid fanout - IP Creator Support high performance low jitter feature for Seal PLL [09/01/2021] V2.10.5 Fast Track Build 090121 - Seal 30K Production device related updates Bitgen : fix CRC/compress related issue Placer : Fix issue related with PLL-CM3 Router : Fix DDRCTRL clock routing issue Donwloader update [08/30/2021] V2.10.5 Fast Track Build 083021 - Seal 30K Production device related updates Bitgen update on compression, CRC and padding DQSBUFM supports 4 more paramerters Routing: fix control net routing to PCLK issue Placement: fix DDRDLL clock input model issue - RTL synthesis Fix a corner comb-loop issue in technology mapping Initial value updates fro shift register. - IP Creator Seal EBR IPGEN update Seal DSP basic IPGEN support - HqInsight Improve hierarchical name handling Improve bus name handling in netlist level debug [08/25/2021] V2.10.5 Fast Track Build 082521 - RTL synthesis Fix a bug in tech-mapping related with combination loop Refine FSM output logic optimization - Downloader Fix an issue related with 7K extenal flash Update for Seal SA5Z-30 devices. [08/23/2021] V2.10.5 Fast Track Build 082321 - Router Refine delay estimation for SA5Z-30 devices - Placer Fix DSP regression issues for SA5Z-30 devices - RTL synthesis Fix assertion issues related with parameter of empty string value Fix port name matching issue for single-bit port with bus name format - IP Creator Enable PLL IPGEN for Seal 30k production (SA5Z-30) devices [08/18/2021] V2.10.5 Fast Track Build 081821 - Placer Disable unnecessary dedicate connection checking for PLLREFCS of Seal devices. [08/17/2021] V2.10.5 Fast Track Build 081721 - IP Creator Update Seal IP of FIFO related with read width 36 Update FIFO simulation model accordingly [08/12/2021] V2.10.5 Fast Track Build 081221 - Placer Update FIFO support for Seal 30Z devices - RTL synthesis Fix an assertion issue in shift register handling [07/31/2021] V2.10.4 BETA073121 <=========================== - Production device support SA5Z-30-D0-8U324, SA5Z-30-D1-8U324, SA5Z-30-D2-8U324 - Refine timing modeling - RTL synthesis Fix a corner bug in MUX optimization for sealion family Refine message prompt for invalid decimal constant Refine Pseudo dual port RAM mapping Fix a corner bug in ROM infer/map - Placement&Route Ehance timing driven optimization Refine handling of SRL16/MULT/PRADD CM3/PLL related updates [07/14/2021] V2.10.3 FT071421 - Placement Fix issue related with SLICEM counting Fix logic error related with unrelated packing - Design interface IO related Legalization update for netlist generated by third-party tool - Packing Fix INV pack issue for seal devices Legalization of IOLOGIC unroutable GND input - IP Creator Update FIFO with 32bit data with and with 16K address extension - Downloader Combine Seal and Sealion downloader Update downloader for Sealion 7K device Add support of bin2burstsvf - Device modeling Update timing info for DQS and some interconnect wires [06/26/2021] V2.10.3 BETA062621 <=========================== - HqInsight Support for seal device - IP Creator Update for EBR/FIFO 16/32 bit data [06/09/2021] V2.10.2 FT060921 - Seal device realted updates Fix regression issue of JTAG bitgen Update Verilog simulation models of PLL and JTAG Restructure Verilog model from one big file to multiple files - RTL synthesis Fix FSM bug related with invalid and initital states Refine message prompt related with latch, port width mismatch, mult-driven, ...etc. [06/03/2021] V2.10.2 FT060321 - update timing data from the file swith_box_bbb.xlsx [05/31/2021] V2.10.2 FT053121 - Fixed min/max value problem for DDRCTRL and CM3 [05/28/2021] V2.10.2 FT052821 - Seal DSP SL_LOAD port support - Seal simulation model updates for PLL, FIFO8K and PREADD [05/21/2021] V2.10.2 FT052121 - Seal support update Updated simulation model for IOL with EDGEMON Support FIFO8K wide mode Support packing CLOCK INV [05/21/2021] V2.10.1 BETA052121 <=========================== - Device modeling Update cell timing parameters for DDRCTRL Simulation model update for IOREG with EDGEMON - Packing Support FIFO8K with wide data width [05/15/2021] V2.10.1 FT051521 - Packing Update for ODELAY control signals Refined absorbing CLKINV to IOReg - Router update for assigning Reset net to PCLK related with DDRCTRL RST_B port [05/13/2021] V2.10.1 FT051321 - Seal bitgen PGNG fuse update SLICE O5X select fuse update - Seal Packer update for IO Latch - IP Creator Add EBR/FIFO IPGEN for seal devices [05/11/2021] V2.9.9 FT051121 - Packing Fixed a bug related with LSR port of OSHX/TSHX - Updated cell timing models for CM3 add conditional timing arcs for {PLL_USRCLK PLL_OUT CLK_PAD CIBCLK} [05/10/2021] V2.9.9 FT051021 - Updated cell timing models for CM3 add clkset for {PLL_USRCLK PLL_OUT CLK_PAD CIBCLK} [04/30/2021] V2.9.9 FT043021 - Initial external VREF support - Timing model Fixed interconnect delay model issue related with CTRL/GFAN Fixed clock auto-generation issue related with CLKDIV - Seal 30K production update [04/23/2021] V2.9.9 FT042321 - Seal 30K production initial support - Updated cell timing models for CM3 and DDRCTRL MPW version - Updated simulation models for : High spped IO (e.g. DDR2 memory) interface primitives True dual port BRAM 16K (xsBRAM16KTD) [04/18/2021] V2.9.8 BETA041821 <=========================== - Slice timing arc/value update CLK->BMUX timing arc Asynchronous recovery/removal reset/set-to-q Seq2comb timing arc - Routing Limit logic_outs fanout - More DRC check Illegal PAD connection between two PIOs IO Standard conflict of paired pins ECLKSYNC overflow - GUI Fixed issue related with empty file in design explorer - Others DQSBUF/PREADD support update Regression issue fix [03/27/2021] V2.9.8 BETA032721 <=========================== - Device update Add param WRITE_LEVEING support for Seal DQSBUF - Downloader Update for 30K MPW device - GUI resolve issue of wrongly turning on LE level packing/placement in multiple device run (V2.9.8 FT032521) - Placer Correct problem of PT7A/B/C/D bank number for 30K device - Packing/Bitgen Updated parameters (PHASE_SHIFT, WRITE_LEVELING, ...etc) for IODDR cells (V2.9.8 FT032421) - Seal 30K PIO PG NG fuse support With GUI updated - Seal mpw ebr 72-bit PDP EBR support (V2.9.7 FT031621) - Bitgen Fix PLL Refclk4 typo MPW IMUX21 and BYP2 share fuse - Placement Refined set_global_attr by considering VCCIO - Packing Fixed ODDR71 related issue - RTL synthesis Fixed a bug in FSM extraction related with decoder. (V2.9.7 FT031121) - RTL synthesis Updated INIT value handling for Seal device Fixed a corner issue related with string parameter using ?: operator - Routing Fixed DCS-SEL routing fail for Seal 100 device - Constraint Support ioh.set_global_attr -unused_io tie_z for seal device - (V2.9.7 FT031021) - Routing Fixed a bug for DCS-SEL CIB clk_cs_1/clk_cs_3 - ECO Fixed a bug related with TIEOFF in signal-probe. Refined for X4 test pattern Fixed issue related with EBR input. (V2.9.7 FT030921) - ECO Initial signal probe support for seal device (V2.9.7 FT030521) - Clock TAP index constraint support : phycst.net.set -index -tapidx - Bitgen CIBTEST support update DCS support update (V2.9.7 FT030421) - Seal EFB support refine (V2.9.7 FT030221) - Placement Fixed PIO2PCLK clock counting issue (issue from Guowei) Fixed PIO2ECLK dedicated connection issue (issue from Huifen) - PLL IPGEN update for CLKOS3_FRAC_DIV support (req. by WenQin) - Bitgen : DSP dyn_opr_inv fuse invert for mpw (V2.9.7 FT030221) - PLL IPGEN update for trim and interanl-feedback support, for sealion and seal devices - Routing bug-fix for DDRCTRL of Seal 100K device - Seal CIBTEST intitial flow support [02/26/2021] V2.9.7 BETA022621 <=========================== - PLL IP Creator update for RESET/STDBY/CLKISEL/DPHASE/FBMODE - PLLREFCS support update (V2.9.7 FT022521) - Packing Prevent dropping user contraint when doing LUT input redundency removal - Routing Support disabling tiles for routing ECLK bridge bug-fixes for sealion devices [02/23/2021] V2.9.6 BETA022321 <=========================== > Seal IP Creator refactor > Incorporated FT021921 update - Bitgen bitgen "ctrl0" update for Seal 30K devices - Placement Fixed global net assignment win/linux difference issue [02/10/2021] V2.9.6 BETA021021 <=========================== - Placement Fixed issues related with SLICEM carry chain placement Fixed issues related with PCLK assignment Fixed several functional issues in LE packing Enhance DSP support related with SIGNED/SOURCEA/B ports - Routing Fixed dedicated clock-to-PLL input routing error. - Bitgen/Downloader Fixed extra leading 0000 issue in bin file generation for 30K devices Support 30K devices. [01/24/2021] V2.9.6 BETA012421 - Initial beta version for Seal device support.