******************************************************************* * * HqFpga-XIST Seal Alpha2 Fast Track Build Release Note * ******************************************************************* * UPDATE HISTORY * [01/09/2021] Seal Alpha 2 Fast Track Build Xi'an onsite build -- Requested by Wenqin Lv Same as below execpt that it is Windows version rather than linux version From: Wu Yang[mailto:wuyang@uptops-dt.com] Sent: Friday, January 1, 2021 8:17 PM To: Joanne Wei ; ÍõÀèÃ÷ Cc: Dongxiao Zhang (Daniel) Subject: hqfpga_lin64_100k_alpha2_20210101.tar 100k alpha2: corner wrap lines are OK. bitgen support clock(cmux + spine_en + tap) [09/12/2020] V2.8.3_SA091220 - LUT/FF level location constraint support - Routing double drive defualt no-share of X1/X2 [09/10/2020] V2.8.3_SA091020 - Open-up flow partial support - Timing driven optimization flow partial support - fixed a regression issue in XPN reader [09/08/2020] V2.8.3_SA090820 - Routing Support IMUX double drive feature - Bitgen Support frame CRC [08/25/2020] V2.8.3_SA082520 - Routing Fixed an issue related routing special pins on vcc/gnd net Disable route-through of CLK1 in DCS - Placement Auto IO placement for JTAG [08/22/2020] V2.8.3_SA082220 - Bitgen for SA5-30E Patch for PLL and DCS [08/21/2020] V2.8.3_SA082120 - Bitgen for SA5-30E Fixed VPRX22 issue CEPI invert - Bitgen/Routing for SA5-30E SEL6/7 -> BYP2/7 support - Placement Support set location to instance in cell group [08/20/2020] V2.8.3_SA082020 - Bitgen update clock_top.mem - Routing Remove GLOBAL_RST_N from DDRCTRL [08/19/2020] V2.8.3_SA081920N(ight) Build - Bitgen/Packing Fixed bugs in PIC/ECLK - Routing Fixed bugs related with DCC, USRCLK@DDRCTRL, CIBCLK@CM3 [08/18/2020] V2.8.3_SA081820 - Bitgen Fixed issue related with a reversed clock fuse address range - Routing Fixed an issue related with CM3 of SA5-30E device Fixed an issue related with MULT9 of SA5-74E device - Placement/Routing Support for DDRCTRL of SA-30E device [08/17/2020] V2.8.3_SA081720 - Routing Fixed HW-SW model difference issue for SA5-74 device Fxied corner routing issue for CM3 for SA5-30E device - Bitgen Refined method to handle #LATCH [08/16/2020 Night] V2.8.3_SA081620N * SA5M-30E device support * - 30K CM3 initial support device modeling, packing, placement, routing update - Bitgen/Packing Fixed issue related with #LATCH - Routing updated routing table to be compatible with X7 arch. update for FAN6/7 JMP [08/16/2020] V2.8.3_SA081620 * SA5M-30E device support * - Routing Fixed flag reset problem caused by rtres.disable - Bitgen Fixed issues related with IMUX and FAN6/7 default value [08/15/2020] V2.8.3_SA081520 - SA5M-30E device support Routing : Fixed routing issues related wrap-around lines Bitgen : Fixed issues related DQS issue and SWB [08/13/2020] V2.8.3_SA081320 - SA5M-30E device support Routing : Fixed routing issues related with PCLK/EBR/DSP Bitgen : Fixed issues related with clktop and addrs [08/11/2020] V2.8.3_SA081120 - SA5M-30E device support Initial whole-flow support. - SA5M-74E device support Fixed bitgen issue related with PLL and LVDS issue on PIO C/D position [08/06/2020] V2.8.3_SA080620 - Placement Initial support for 30K device Fixed a bug in DDRDLL Placement Fixed bugs in timing driven optimization flow [06/10/2020] V2.8.1_SA061020 - Routing Fix the jmp for DDRDLL_L Add connections from clock pad to ECLK for ECLKLR Add the source eclk for bottom tile BECLK1 Add the connections from clock pad to ECLK Change pin name from CLKT/B to CLK0/1 for ECLKBRIDGECS Add chain pins COs and CFBs for ALU - Placement Enhanced memory interface IO handling. Update for clock region handling Update for PCLK/ECLK/PLL/IO [04/26/2020] V2.7.6_SA042620 - Placement Fixed a bug related with output-ioreg and tri-ioreg companion. [04/23/2020] V2.7.6_SA042320 - New package support : SA5M-74E-8N96 - Placement-and-Routing clock region support update refine large-fanout net routing [03/17/2020] V2.7.6_SA031720 - Packing ALU CIN Legalization of const nets. [03/12/2020] V2.7.6_SA112619 - Bitgen initial support of DSP - Placer initial support of MULT9, PRADD initial support of clock region - Packing Refined support of SLICE, IO and EBR - ------ Merged updates from normal V2.7.6 -------v - RTL synthesis Fixe multiplier mapping issue related with sign/unsigned data. Added basic support for RAM-based shift register - Packing/Placement Support LUT/REG level location constraint Support incremental placement More strict user constraint checking. - Router Updated support for fast-routing wires. Better handling of PCLK conflicts between hardware connection against user constraint. - STA Fixed a corner bug related with unconstrained register-to-ouput path [11/26/2019] V2.7.1_SA112619 - Bitgen support for EBR18K [11/23/2019] V2.7.1_SA112319 - Initial support for EBR18K and distrubuted RAM - Bitgen bug-fixes for Distributed RAM, SRL, carry INIT [11/21/2019] V2.7.1_SA112119 - Bitgen updates Support slice out->outmux route-through Unset tsinv by default EBR9X support update [11/20/2019] V2.7.1_SA112019 - Routing : fixed bug related with DSP chain (dsp_18x18) [11/19/2019] V2.7.1_SA111919 - Initial support of PLL (sealion 25K-compatible mode) - router/bitgen updated based on data20191118.tar.gz Update for some DLL/EBR/EFB/DSP cibs - routing fixed regression issues. - Bitgen Slice.mem update - Packer legalization of PLL WB* pins [11/14/2019] V2.7.1_SA111419 - Routing Fixed a bug of wrong jmps for PADDT and PADDO on right-side IOs (cm3_gpio) Fixed a issue causing memory leaks - Bitgen : fixed tap fuse [11/13/2019] V2.7.1_SA111319N(ight) - Placement : fixed a bug in carry chain handling (dsp_36x36) - Routing : fixed bug related TIEOFF resource (cm3 with const connection) [11/13/2019] V2.7.1_SA111319 - Bitgen update BMAINMUX0 bug-fix Initial support for EBR and DSP. Fixed linux-windows result difference issue. [11/12/2019] V2.7.1_SA111219 - Support of power net (GND/VCC) routing - Support of long wire routing - Preliminary support of EBR -- support 9K with unit test, 18K is not supported) DSP -- support MULT with unit test ALU is supported, but not tested pre-adder is not supported CM3 -- suport with unit test [11/05/2019] V2.7.1_SA110519 - Router, fixed issues: long runtime problem. A few general routing resources is still used in GCLK. Wrong jmps between JPADDO and JPADDT - Bitgen Fixed issues related with mainmux, tapdriver and tsinv [11/03/2019] V2.7.1_SA110319 - Basic Seal device support Support IO, LUT, FF, global clock routing.