******************************************************************* * * HqFpga-XIST V3.0.4 Software Release Note * ******************************************************************* * UPDATE HISTORY * [07/21/2024] V3.0.4 <============================================ - Device support ** New device/packages support ** SL2E-4V-8E144CI SL2E-4V-8U256CI SL2E-2V-8U256CI SA5T-100-D0-8FA676C Fix issue related with external 1.2V VREF support for Seal device Seal 30K IO_TYPE updates Support LVDS18 Disable IO_TYPE under 1.8v, except SSTL15 Add LVTTL33D support for Seal device - GUI Enhance design project migration with relative path handling Fix IO type missing issue in constraint editor for Seal devices Integrate routing heatmap viewer Add option to disable IO insertion Support import RTL with .f list file Enhance stability and usability of IDE-style GUI, fix issues related with editor, terminal, constrained editor, design hierarchy, flow control, special file hierarchy/path, message, list file, ...etc. - HqInsight (debugger) * Support multiple LA core * Improve user interaction performance Enhance handling of large files By default use internal waveform viewer (HqWave) instead of GtkWave Support VIO retargetting flow Keep instrumented signal settings when source file change Enhance source file change detection Enhance save/load of instrumented signal settings Support customized trigger position (pre-stored tap count). Optimize trigger condition Remove 'X' values (wait enough data stored before trigger) Refine VLA setting Refine UI (font, backcolor) Fix various issue related with : signal selection, waveform, color setting, radix, VLA setting, VIO debugger, editor display, EDIF flow, Continuous triggering, combined trigger condition top/sub module change/removal, synthesis directive, linux platform, ..etc. - IP Creator Refine error checking and prompt upon fail-run of an ipgen executable. Add new IPs: CM33 IP for Seal 50K device. SED IP for Seal device FIFO-Generator IP CORDIC IP: fix output data range error in complex modular(translate) mode DDRC IP update: add device checking Refine datasheet, diagram; Add an option to ouput file for simulation; Update for DDR3 mode; Fix clock-frequency setting issue in DDR3-SDRAM mode Add generation status checking and prompt FIFO IP: fix issues related with FULL/EMPTY flag PLL IP: Add PHASESEL bus width info in diagram, fix wrong messages GDDR71 IP: fix issues related with LVDS18 EBR IP: fix USE_XY_DA/DB parameter value issue for Seal 100K device CM3 IP: Fix typo on AHB master config page FFT IP: fix issues related with datawith 18 Filter IP: Update dataSheet on dual-chan-mode's control&data info Fix IP output file rename issue Solved issue related with white-space in path name - Downloader updates related with 50K/100K/4K devices update DNA information detection, bit-verify for sealion devices; refine output message and GUI Fix golden address issue for 4K/7K/12K/30K/50K devices Fix EBR initialization issue for Seal devices Add download support and DNA detection for 100K A2 device Fix svf.log-missing issue when hqfpga invoking cable Enhance dualboot to make primary address customizable Add dualboot primary address entry in GUI Fix EBR data issue when doing bit2bin of Seal 100K device Add dialog box upon multiple HqFpga instances Fixed the problem of deleting bit files by mistake - Bitgen Fix PRADD/MULT C fuse Update package pins related with NCSO/ASDO/MCLK for Seal 50K devices Fix issue for HSTL12D SSTL12D POD12D IO types Support IO PGNG fuse setting for Seal devices. Adjust pgng fuse setting for Seal 50K/100K devices Add an argument -dclk for specifying DCLK frequency Fix issues of pnterm fuse on differential IO_TYPE for Seal devices - RTL synthesis Fix an issue related with complex FSM state minimization Reduce runtime for redundant FF removal for corner cases. Enhance check of ROM infer size Improve if statement related with constant value if branch Refine RAM infer, map and retargetting: Support one-write two-read ports, open DO bits Support more complex coding styles using if/case statements Improve distributed PDP RAM inference related with byte-enable Support ROM address size reduction Fix issues related with single port RAM, addr-reg, byte-enable Improve SDP RAM inference related with ADDR-REG, ByteEnable Enhance error checking and message prompt during retargetting Refine DSP infer, map and retargetting: Enhance inference/map related with MULT+REG, DSP driving multiple ADD/SUBs Enhance DSP48 retargetting by supporting more OPMODEs Enhance DSP48 retargetting related with A/BREG mode and C port connection Enhance attribute support and parameter checking Enhance error checking for case statement with more than one default branches Refine error message prompt when instance name is the same as net name Fix analyzer issues related with function, task, multi-driven Refine DSP retargetting Refine big-sized ROM inference. Fix crash issue related with undriven input of MUX. Refine message prompt related with parameter, localparam and partial-selection Add checking for unconnected ports Support empty module which is actually a primitive Support non-blocking assignment in task Enhance constant FF removal Enhance large binary-mux partition handling. Enhance expression optimization on consecutive LSB 0s Refine exception checking and message prompt Check parameter value of primitives at early stage Refine naming of inferred shift-register logic Support one-dimensional reg array write in constant function; Improve constant array index handling Fix abnormal exit on syntax error of parameter by name Fix typos in message file Enhance attribute support for concated values. Reduce runtime for shift register inference. Reduce runtime for binary MUX handling Enhance array index net handling Enhance debug message upon exception in analyzer Fix issue related with array initialization Enhance exception handling in MUX optimization Improving $readmem statement for empty mem init file Fix dead loop issue in expression optimization Fix an cross-probing issue related with macro Add checking of port-redecalration and illegal definition Remove FF dummy control pins Fix issues in FSM state extraction and minimization Fix long runtime issue when parsing encrypted file Fix crash issues related with module without port Unified error message in Chinese and English; Refine error message related with port declaration - Place & Route Enhance routability and congestion handling of router for Seal devices reduce ~10% routing runtime Enhance routability for Seal device with ~10% routing runtime reduction Fix packing crash issue related with abnormal SERDES connection Balance net/slice to avoid congestion for effort-low packing Refine SCLK clock/data sink routing policy for Sealion devices Enhance IOLOGIC packing support IREG and OREG/TREG with inverted clock phase Fix SADC placement issue for Seal 100K device Fix placement issue related with ALU24 for Seal devices Refine Bank ADC VCCIO checking for Seal 30K device - device modeling Fix timing arc missing issue between RSTm and CLKn for Seal DSP cells Update timing information related with DWA of EBR18/36, CLKm->RSTn of DSP Update wide-EBR support and timing info. - Design interface Add differential clock IO checking Set DMP, ECC_EFB, ISCPU as dont-touch to keep it from being swept. More strict checking on string-type parameters of primitives Do EBR/DSP retargetting immediately after EDIF reader. Enhance type/range validity checking to primitive parameters Seal pack update for EDIF lut pairing Report un-used resources in utilization report Support IS_*_INVERTED parameters for primitives generated by 3rd-party tool Refine mixed-clock-data check for inverter/buffer update Verilog write NOT to write equation for non-generic logic cells (e.g. MUXCY) Simulation model update: Add DDRCTRL models for modelsim EBR model update for READ_BEFORE_WRITE mode of both ports SERDES_CH/SERDES_COM_E1 Expose new SERDES ports to users: SERDES_CH.QPLLCLK and SERDES_COM_E1.QPLLOUTCLK IO report: show package pin name instead of inner pad location for seal devices Include IREG/OREG/TREG numbers when reporting IOLOGIC resources. Add checking of IREG/OREG/TREG usage and pairing Report PRADD utilization - STA Support analysis/report for unconstrained clocks Fix a crash bug related with enormous path constraints Enhance validity checking for clock group constraint [02/18/2024] V3.0.3 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.4 Build 021824: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.4/ [11/06/2023] V3.0.2 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.3 Build 110623: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.3/ [06/19/2023] V3.0.1 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.2 Build 061923: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.2/ [02/19/2023] V3.0.0 <============================================ - IDE-look UI - Core components are same as those in HqFpga 2.14.1 Build 021923: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.1/