//synthsis translate_off
//synopsys translate_off
"NOTE: This file should NOT be used for simulation!"
//synopsys translate_on
//synthsis translate_on

(* black_box, dont_touch="true" *)
module xsIOBI (I, O)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
output O ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBI_PD (I, O)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
output O ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBI_PU (I, O)/*synthesis syn_black_box syn_noprune=1*/;
input  I;
output O;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBI_D (A, AN, Z, ZN)/*synthesis syn_black_box syn_noprune=1*/;
  input  A;
  input  AN;
  output Z;
  output ZN;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBO (I, O)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
output O ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBO_C (I, OT, OC)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
output OT ;
output OC ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBT (I, T, O)/*synthesis syn_black_box syn_noprune=1*/;
input I ;
input T ;
output O ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBT_PU (I, T, O)/*synthesis syn_black_box syn_noprune=1*/;
input I ;
input T ;
output O ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBO_D (A, Z, ZN)/*synthesis syn_black_box syn_noprune=1*/;
  input  A;
  output Z;
  output ZN;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBB (I, T, O, B)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
input  T ;
output O ;
inout  B ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBB_PD (I, T, O, B)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
input  T ;
output O;
inout  B ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBB_PU (I, T, O, B)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
input  T ;
output O;
inout  B ;
endmodule

(* black_box, dont_touch="true" *)
module xsIOBB_K (I, T, O, B)/*synthesis syn_black_box syn_noprune=1*/;
input  I ;
input  T ;
output O;
inout  B ;
endmodule

(* black_box, dont_touch="true" *)
module xsIDFF_K1P1E1 (D, SP, SCLK, PD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SP;
input SCLK;
input PD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsIDFF_K1C1E1 (D, SP, SCLK, CD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SP;
input SCLK;
input CD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsIDFF_K1R1E1 (D, SP, SCLK, CD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SP;
input SCLK;
input CD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsIDFF_K1S1E1 (D, SP, SCLK, PD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SP;
input SCLK;
input PD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsODFF_K1P1E1 (D, SP, SCLK, PD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D ;
input SP ;
input SCLK ;
input PD ;
output Q ;
endmodule

(* black_box, dont_touch="true" *)
module xsODFF_K1C1E1 (D, SP, SCLK, CD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D ;
input SP ;
input SCLK ;
input CD ;
output Q ;
endmodule

(* black_box, dont_touch="true" *)
module xsODFF_K1R1E1 (D, SP, SCLK, CD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D ;
input SP ;
input SCLK ;
input CD ;
output Q ;
endmodule

(* black_box, dont_touch="true" *)
module xsODFF_K1S1E1 (D, SP, SCLK, PD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D ;
input SP ;
input SCLK ;
input PD ;
output Q ;
endmodule

(* black_box, dont_touch="true" *)
module xsILAT_K1P1 (D, SCLK, PD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SCLK;
input PD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsILAT_K1C1 (D, SCLK, CD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SCLK;
input CD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsILAT_K1R1 (D, SCLK, CD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SCLK;
input CD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsILAT_K1S1 (D, SCLK, PD, Q)/*synthesis syn_black_box syn_noprune=1*/;
  parameter GSR = "ENABLED";
input D;
input SCLK;
input PD;
output Q;
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM32KTD_E1 (
    // 100k prod
input IN_1BIT_ERR, IN_DBIT_ERR,
output SBIT_ECC_ERR, MORE_ECC_ERR,
    // end 100k prod
input   DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9,
         DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
         ADA14, ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5,
         ADA4,  ADA3,  ADA2, ADA1, ADA0,
         CEA, OCEA, CLKA, WEA, CSA3, CSA2, CSA1, CSA0, RSTA,
         DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9,
         DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
         ADB14, ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5,
         ADB4,  ADB3,  ADB2, ADB1, ADB0,
         CEB, OCEB, CLKB, WEB, CSB3, CSB2, CSB1, CSB0, RSTB,
// for 72-bit psdeou
input   YDIA17, YDIA16, YDIA15, YDIA14, YDIA13, YDIA12, YDIA11, YDIA10, YDIA9,
         YDIA8, YDIA7, YDIA6, YDIA5, YDIA4, YDIA3, YDIA2, YDIA1, YDIA0,
         YDIB17, YDIB16, YDIB15, YDIB14, YDIB13, YDIB12, YDIB11, YDIB10, YDIB9,
         YDIB8, YDIB7, YDIB6, YDIB5, YDIB4, YDIB3, YDIB2, YDIB1, YDIB0,
input YADA3, YADA2, YADA1, YADA0, YADB1, YADB0,
output  YDOA17, YDOA16, YDOA15, YDOA14, YDOA13, YDOA12, YDOA11, YDOA10, YDOA9,
         YDOA8, YDOA7, YDOA6, YDOA5, YDOA4, YDOA3, YDOA2, YDOA1, YDOA0,
         YDOB17, YDOB16, YDOB15, YDOB14, YDOB13, YDOB12, YDOB11, YDOB10, YDOB9,
         YDOB8, YDOB7, YDOB6, YDOB5, YDOB4, YDOB3, YDOB2, YDOB1, YDOB0,
// end for 72-bit psdeou
output  DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9,
         DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
         DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9,
         DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 )/*synthesis syn_black_box syn_noprune=1*/;
parameter  ECC_WEN = "FALSE";
parameter  ECC_REN = "FALSE";
parameter  USE_XY_DA = "FALSE";
parameter  USE_XY_DB = "FALSE";
parameter  USE_XY_DI = "FALSE";
parameter  USE_XY_DO = "FALSE";
parameter  DATA_WIDTH_A = 18;
parameter  DATA_WIDTH_B = 18;
parameter  REGMODE_A = "NOREG";
parameter  REGMODE_B = "NOREG";
parameter  RESETMODE = "SYNC";
parameter  ASYNC_RESET_RELEASE = "SYNC";
parameter  WRITEMODE_A = "NORMAL";
parameter  WRITEMODE_B = "NORMAL";
parameter  CSDECODE_A = "0b0000";
parameter  CSDECODE_B = "0b0000";
parameter  GSR = "ENABLED";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_40 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_41 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_42 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_43 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_44 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_45 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_46 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_47 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_48 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_49 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_50 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_51 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_52 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_53 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_54 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_55 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_56 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_57 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_58 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_59 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_60 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_61 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_62 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_63 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_64 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_65 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_66 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_67 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_68 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_69 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_70 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_71 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_72 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_73 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_74 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_75 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_76 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_77 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_78 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_79 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INIT_DATA = "STATIC";
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM32KTD (
    // 100k prod
input IN_1BIT_ERR, IN_DBIT_ERR,
output SBIT_ECC_ERR, MORE_ECC_ERR,
    // end 100k prod
input   DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9,
         DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
         ADA14, ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5,
         ADA4,  ADA3,  ADA2, ADA1, ADA0,
         CEA, OCEA, CLKA, WEA, CSA3, CSA2, CSA1, CSA0, RSTA,
         DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9,
         DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
         ADB14, ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5,
         ADB4,  ADB3,  ADB2, ADB1, ADB0,
         CEB, OCEB, CLKB, WEB, CSB3, CSB2, CSB1, CSB0, RSTB,
// for 72-bit psdeou
input   YDIA17, YDIA16, YDIA15, YDIA14, YDIA13, YDIA12, YDIA11, YDIA10, YDIA9,
         YDIA8, YDIA7, YDIA6, YDIA5, YDIA4, YDIA3, YDIA2, YDIA1, YDIA0,
         YDIB17, YDIB16, YDIB15, YDIB14, YDIB13, YDIB12, YDIB11, YDIB10, YDIB9,
         YDIB8, YDIB7, YDIB6, YDIB5, YDIB4, YDIB3, YDIB2, YDIB1, YDIB0,
input YADA3, YADA2, YADA1, YADA0, YADB1, YADB0,
output  YDOA17, YDOA16, YDOA15, YDOA14, YDOA13, YDOA12, YDOA11, YDOA10, YDOA9,
         YDOA8, YDOA7, YDOA6, YDOA5, YDOA4, YDOA3, YDOA2, YDOA1, YDOA0,
         YDOB17, YDOB16, YDOB15, YDOB14, YDOB13, YDOB12, YDOB11, YDOB10, YDOB9,
         YDOB8, YDOB7, YDOB6, YDOB5, YDOB4, YDOB3, YDOB2, YDOB1, YDOB0,
// end for 72-bit psdeou
output  DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9,
         DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
         DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9,
         DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 )/*synthesis syn_black_box syn_noprune=1*/;
parameter  ECC_WEN = "FALSE";
parameter  ECC_REN = "FALSE";
parameter  USE_XY_DA = "FALSE";
parameter  USE_XY_DB = "FALSE";
parameter  USE_XY_DI = "FALSE";
parameter  USE_XY_DO = "FALSE";
parameter  DATA_WIDTH_A = 18;
parameter  DATA_WIDTH_B = 18;
parameter  REGMODE_A = "NOREG";
parameter  REGMODE_B = "NOREG";
parameter  RESETMODE = "SYNC";
parameter  ASYNC_RESET_RELEASE = "SYNC";
parameter  WRITEMODE_A = "NORMAL";
parameter  WRITEMODE_B = "NORMAL";
parameter  CSDECODE_A = "0b0000";
parameter  CSDECODE_B = "0b0000";
parameter  GSR = "ENABLED";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_40 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_41 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_42 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_43 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_44 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_45 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_46 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_47 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_48 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_49 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_50 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_51 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_52 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_53 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_54 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_55 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_56 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_57 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_58 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_59 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_60 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_61 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_62 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_63 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_64 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_65 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_66 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_67 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_68 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_69 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_70 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_71 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_72 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_73 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_74 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_75 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_76 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_77 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_78 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_79 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INIT_DATA = "STATIC";
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM16KTD_E0 (
input   DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9,
         DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
         ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5,
         ADA4,  ADA3,  ADA2, ADA1, ADA0,
         CEA, OCEA, CLKA, WEA, CSA1, CSA0, RSTA,
         DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9,
         DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
         ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5,
         ADB4,  ADB3,  ADB2, ADB1, ADB0,
         CEB, OCEB, CLKB, WEB, CSB1, CSB0, RSTB,
output  DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9,
         DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
         DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9,
         DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 )/*synthesis syn_black_box syn_noprune=1*/;
parameter  DATA_WIDTH_A = 18;
parameter  DATA_WIDTH_B = 18;
parameter  REGMODE_A = "NOREG";
parameter  REGMODE_B = "NOREG";
parameter  RESETMODE = "SYNC";
parameter  ASYNC_RESET_RELEASE = "SYNC";
parameter  WRITEMODE_A = "NORMAL";
parameter  WRITEMODE_B = "NORMAL";
parameter  CSDECODE_A = "0b00";
parameter  CSDECODE_B = "0b00";
parameter  GSR = "ENABLED";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INIT_DATA = "STATIC";
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM16KTD (
input   DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9,
         DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
         ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5,
         ADA4,  ADA3,  ADA2, ADA1, ADA0,
         CEA, OCEA, CLKA, WEA, CSA3, CSA2, CSA1, CSA0, RSTA,
         DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9,
         DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
         ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5,
         ADB4,  ADB3,  ADB2, ADB1, ADB0,
         CEB, OCEB, CLKB, WEB, CSB3, CSB2, CSB1, CSB0, RSTB,
output  DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9,
         DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
         DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9,
         DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 )/*synthesis syn_black_box syn_noprune=1*/;
parameter  DATA_WIDTH_A = 18;
parameter  DATA_WIDTH_B = 18;
parameter  REGMODE_A = "NOREG";
parameter  REGMODE_B = "NOREG";
parameter  RESETMODE = "SYNC";
parameter  ASYNC_RESET_RELEASE = "SYNC";
parameter  WRITEMODE_A = "NORMAL";
parameter  WRITEMODE_B = "NORMAL";
parameter  CSDECODE_A = "0b0000";
parameter  CSDECODE_B = "0b0000";
parameter  GSR = "ENABLED";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INIT_DATA = "STATIC";
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM8KTD (DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9,
//end of change
         DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
         ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5,
         ADA4,  ADA3,  ADA2, ADA1, ADA0,
         CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA,
//change
         DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9,
//end of change
         DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
         ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5,
         ADB4,  ADB3,  ADB2, ADB1, ADB0,
         CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB,
//change
         DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9,
//end ofchange
         DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
//change
         DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9,
//end ofchange
         DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH_A = 18;            // 1, 2, 4, 9, 18, 36
   parameter  DATA_WIDTH_B = 18;            // 1, 2, 4, 9, 18, 36
   parameter  REGMODE_A = "NOREG";         // "NOREG", "OUTREG"
   parameter  REGMODE_B = "NOREG";         // "NOREG", "OUTREG"
   parameter  CSDECODE_A = "0b000";        // "0b000", "0b001", "0b010"......."0b111"
   parameter  CSDECODE_B = "0b000";        // "0b000", "0b001", "0b010"......."0b111"
   parameter  WRITEMODE_A = "NORMAL";      // "NORMAL", "READBEFOREWRITE", "WRITETHROUGH"
   parameter  WRITEMODE_B = "NORMAL";      // "NORMAL", "READBEFOREWRITE", "WRITETHROUGH"
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  RESETMODE = "SYNC";          // "SYNC", "ASYNC"
   parameter  ASYNC_RESET_RELEASE = "SYNC";          // "SYNC", "ASYNC"
   parameter  INIT_DATA = "STATIC";          // "STATIC", "DYNAMIC"
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
input    DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9,
//end of change
         DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
         ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5,
         ADA4,  ADA3,  ADA2, ADA1, ADA0,
         CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA,
//change
         DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9,
//end of change
         DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
         ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5,
         ADB4,  ADB3,  ADB2, ADB1, ADB0,
         CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB;
output   DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9,
//end of change
         DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
//change
         DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9,
//end of change
         DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0;
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM8KPD (
//change
	 DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28,
	 DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,
//end of change
         DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
         DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
//change
         ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
         BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,
//end of change
//zdx@UDT {
	ADW8, // nouse -- for backward compatible with 7K
//zdx@UDT }
         ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5,
         ADR4,  ADR3,  ADR2, ADR1, ADR0,
         CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
//change
	 DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28,
	 DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,
//end of change
         DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH_W = 36;
   parameter  DATA_WIDTH_R = 18;
   parameter  REGMODE = "NOREG";
   parameter  CSDECODE_W = "0b000";
   parameter  CSDECODE_R = "0b000";
   parameter  GSR = "ENABLED";
   parameter  RESETMODE = "SYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  INIT_DATA = "STATIC";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
input	 DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28,
	 DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,
//end of change
         DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
         DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
//change 082915
//         ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
         ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
         BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,
         ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5,
         ADR4,  ADR3,  ADR2, ADR1, ADR0,
         CER, OCER, CLKR, CSR2, CSR1, CSR0, RST;
output	 DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28,
	 DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,
//end of change
         DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0;
input ADW8; // nouse -- for backward compatible with 7K
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM32KS_E1 (DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
               DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD14, AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0, YAD1, YAD0,
         CE, OCE, CLK, WE, CS3, CS2, CS1, CS0, RST,
         YDI17, YDI16, YDI15, YDI14, YDI13, YDI12, YDI11, YDI10, YDI9,
         YDI8, YDI7, YDI6, YDI5, YDI4, YDI3, YDI2, YDI1, YDI0,
	 DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0,
         YDO17, YDO16, YDO15, YDO14, YDO13, YDO12, YDO11, YDO10, YDO9,
         YDO8, YDO7, YDO6, YDO5, YDO4, YDO3, YDO2, YDO1, YDO0)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  USE_XY_DATA = "FALSE";
   parameter  DATA_WIDTH = 18;
   parameter  REGMODE = "NOREG";
   parameter  CSDECODE = "0b0000";
   parameter  WRITEMODE = "NORMAL";
   parameter  GSR = "ENABLED";
   parameter  RESETMODE = "SYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  INIT_DATA = "STATIC";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_40 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_41 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_42 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_43 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_44 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_45 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_46 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_47 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_48 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_49 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_50 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_51 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_52 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_53 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_54 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_55 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_56 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_57 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_58 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_59 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_60 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_61 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_62 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_63 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_64 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_65 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_66 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_67 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_68 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_69 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_70 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_71 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_72 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_73 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_74 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_75 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_76 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_77 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_78 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_79 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
input    DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
         DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD14, AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0, YAD1, YAD0,
         CE, OCE, CLK, WE, CS3, CS2, CS1, CS0, RST;
output   DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0;
input   YDI17, YDI16, YDI15, YDI14, YDI13, YDI12, YDI11, YDI10, YDI9,
         YDI8, YDI7, YDI6, YDI5, YDI4, YDI3, YDI2, YDI1, YDI0;
output  YDO17, YDO16, YDO15, YDO14, YDO13, YDO12, YDO11, YDO10, YDO9,
         YDO8, YDO7, YDO6, YDO5, YDO4, YDO3, YDO2, YDO1, YDO0;
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM32KS (DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
               DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD14, AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0, YAD1, YAD0,
         CE, OCE, CLK, WE, CS3, CS2, CS1, CS0, RST,
         YDI17, YDI16, YDI15, YDI14, YDI13, YDI12, YDI11, YDI10, YDI9,
         YDI8, YDI7, YDI6, YDI5, YDI4, YDI3, YDI2, YDI1, YDI0,
	 DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0,
         YDO17, YDO16, YDO15, YDO14, YDO13, YDO12, YDO11, YDO10, YDO9,
         YDO8, YDO7, YDO6, YDO5, YDO4, YDO3, YDO2, YDO1, YDO0)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  USE_XY_DATA = "FALSE";
   parameter  DATA_WIDTH = 18;
   parameter  REGMODE = "NOREG";
   parameter  CSDECODE = "0b0000";
   parameter  WRITEMODE = "NORMAL";
   parameter  GSR = "ENABLED";
   parameter  RESETMODE = "SYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  INIT_DATA = "STATIC";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_40 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_41 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_42 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_43 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_44 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_45 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_46 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_47 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_48 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_49 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_4F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_50 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_51 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_52 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_53 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_54 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_55 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_56 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_57 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_58 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_59 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_5F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_60 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_61 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_62 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_63 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_64 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_65 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_66 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_67 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_68 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_69 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_6F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_70 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_71 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_72 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_73 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_74 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_75 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_76 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_77 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_78 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_79 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_7F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
input    DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
         DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD14, AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0, YAD1, YAD0,
         CE, OCE, CLK, WE, CS3, CS2, CS1, CS0, RST;
output   DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0;
input   YDI17, YDI16, YDI15, YDI14, YDI13, YDI12, YDI11, YDI10, YDI9,
         YDI8, YDI7, YDI6, YDI5, YDI4, YDI3, YDI2, YDI1, YDI0;
output  YDO17, YDO16, YDO15, YDO14, YDO13, YDO12, YDO11, YDO10, YDO9,
         YDO8, YDO7, YDO6, YDO5, YDO4, YDO3, YDO2, YDO1, YDO0;
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM16KS_E0 (DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
               DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0,
         CE, OCE, CLK, WE, CS1, CS0, RST,
	 DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH = 18;
   parameter  REGMODE = "NOREG";
   parameter  CSDECODE = "0b00";
   parameter  WRITEMODE = "NORMAL";
   parameter  GSR = "ENABLED";
   parameter  RESETMODE = "SYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  INIT_DATA = "STATIC";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
input    DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
         DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0,
         CE, OCE, CLK, WE, CS1, CS0, RST;
output   DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0;
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM16KS (DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
               DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0,
         CE, OCE, CLK, WE, CS3, CS2, CS1, CS0, RST,
	 DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH = 18;
   parameter  REGMODE = "NOREG";
   parameter  CSDECODE = "0b0000";
   parameter  WRITEMODE = "NORMAL";
   parameter  GSR = "ENABLED";
   parameter  RESETMODE = "SYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  INIT_DATA = "STATIC";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
input    DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
         DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD13, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0,
         CE, OCE, CLK, WE, CS3, CS2, CS1, CS0, RST;
output   DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0;
endmodule

(* black_box, dont_touch="true" *)
module xsBRAM8KS (DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
               DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0,
         CE, OCE, CLK, WE, CS2, CS1, CS0, RST,
//change
	 DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
//end change
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH = 18;
   parameter  REGMODE = "NOREG";
   parameter  CSDECODE = "0b000";
   parameter  WRITEMODE = "NORMAL";
   parameter  GSR = "ENABLED";
   parameter  RESETMODE = "SYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  INIT_DATA = "STATIC";
parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
input    DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9,
//end change
         DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
         AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5,
         AD4, AD3,  AD2, AD1, AD0,
         CE, OCE, CLK, WE, CS2, CS1, CS0, RST;
output   DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9,
         DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0;
endmodule

(* black_box, dont_touch="true" *)
module xsFIFO32KB (
// 100k prod
input IN_1BIT_ERR, IN_DBIT_ERR,
output SBIT_ECC_ERR, MORE_ECC_ERR,
// DC = data count
output   DC0, DC1, DC2, DC3, DC4, DC5, DC6, DC7, DC8,
         DC9, DC10, DC11, DC12, DC13, DC14, DC15,
input    YDI0, YDI1, YDI2, YDI3, YDI4, YDI5, YDI6, YDI7, YDI8,
         YDI9, YDI10, YDI11, YDI12, YDI13, YDI14, YDI15, YDI16, YDI17,
         YDI18, YDI19, YDI20, YDI21, YDI22, YDI23, YDI24, YDI25, YDI26,
         YDI27, YDI28, YDI29, YDI30, YDI31, YDI32, YDI33, YDI34, YDI35,
output   YDO0, YDO1, YDO2, YDO3, YDO4, YDO5, YDO6, YDO7, YDO8,
         YDO9, YDO10, YDO11, YDO12, YDO13, YDO14, YDO15, YDO16, YDO17,
         YDO18, YDO19, YDO20, YDO21, YDO22, YDO23, YDO24, YDO25, YDO26,
         YDO27, YDO28, YDO29, YDO30, YDO31, YDO32, YDO33, YDO34, YDO35,
// end 100k prod
input    DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8,
         DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
         DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26,
         DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35,
         FULLI, CSW0, CSW1, CSW2, EMPTYI, CSR0, CSR1, CSR2, WE, RE, CLKW, CLKR, RST, RPRST,
         ORE,
output   DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8,
         DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
         DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26,
         DO27, DO28, DO29, DO30, DO31, DO32, DO33, DO34, DO35,
         EF, AEF, AFF, FF)/*synthesis syn_black_box syn_noprune=1*/;
parameter  ECC_WEN = "FALSE";
parameter  ECC_REN = "FALSE";
parameter  USE_XY_DA = "FALSE";
parameter  USE_XY_DB = "FALSE";
parameter  FIFO_CNT_CK_SEL = "CLKR"; // "CLKW"
parameter  USE_XY_DI = "FALSE";
parameter  USE_XY_DO = "FALSE";
   parameter  DATA_WIDTH_W = 18;
   parameter  DATA_WIDTH_R = 18;
   parameter  REGMODE = "NOREG";
   parameter  RESETMODE = "ASYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  CSDECODE_W = "0b000";
   parameter  CSDECODE_R = "0b000";
   parameter  AEPOINTER = "0b00000000000000";
   parameter  AEPOINTER1 = "0b00000000000000";
   parameter  AFPOINTER = "0b00000000000000";
   parameter  AFPOINTER1 = "0b00000000000000";
   parameter  FULLPOINTER = "0b00000000000000";
   parameter  FULLPOINTER1 = "0b00000000000000";
   parameter  EMPTYPOINTER = "0b00000";
   parameter  EMPTYPOINTER1 = "0b000000";
   parameter  USE_EMPTYPOINTER = "FALSE";
   parameter  GSR = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsFIFO16KB (DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8,
         DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
         DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26,
         DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35,
         FULLI, CSW0, CSW1, CSW2, EMPTYI, CSR0, CSR1, CSR2, WE, RE, CLKW, CLKR, RST, RPRST,
         ORE, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8,
         DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
         DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26,
         DO27, DO28, DO29, DO30, DO31, DO32, DO33, DO34, DO35,
         EF, AEF, AFF, FF)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH_W = 18;
   parameter  DATA_WIDTH_R = 18;
   parameter  REGMODE = "NOREG";
   parameter  RESETMODE = "ASYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  CSDECODE_W = "0b000";
   parameter  CSDECODE_R = "0b000";
   parameter  AEPOINTER = "0b00000000000000";
   parameter  AEPOINTER1 = "0b00000000000000";
   parameter  AFPOINTER = "0b00000000000000";
   parameter  AFPOINTER1 = "0b00000000000000";
   parameter  FULLPOINTER = "0b00000000000000";
   parameter  FULLPOINTER1 = "0b00000000000000";
   parameter  EMPTYPOINTER = "0b00000";
   parameter  EMPTYPOINTER1 = "0b000000";
   parameter  USE_EMPTYPOINTER = "FALSE";
   parameter  GSR = "DISABLED";
input    DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8,
         DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
         DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26,
         DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35,
         FULLI, CSW0, CSW1, CSW2, EMPTYI, CSR0, CSR1, CSR2, WE, RE, CLKW, CLKR, RST, RPRST,
         ORE;
output   DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8,
         DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
         DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26,
         DO27, DO28, DO29, DO30, DO31, DO32, DO33, DO34, DO35,
         EF, AEF, AFF, FF;
endmodule

(* black_box, dont_touch="true" *)
module xsFIFO16KD (
         DC0, DC1, DC2, DC3, DC4, DC5, DC6, DC7, DC8,
         DC9, DC10, DC11, DC12, DC13, DC14, DC15,
         DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8,
         DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
         DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26,
         DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35,
         FULLI, CSW0, CSW1, CSW2, EMPTYI, CSR0, CSR1, CSR2, WE, RE, CLKW, CLKR, RST, RPRST,
         ORE, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8,
         DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
         DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26,
         DO27, DO28, DO29, DO30, DO31, DO32, DO33, DO34, DO35,
         EF, AEF, AFF, FF)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH_W = 18;
   parameter  DATA_WIDTH_R = 18;
   parameter  REGMODE = "NOREG";
   parameter  RESETMODE = "ASYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  CSDECODE_W = "0b000";
   parameter  CSDECODE_R = "0b000";
   parameter  AEPOINTER = "0b00000000000000";
   parameter  AEPOINTER1 = "0b00000000000000";
   parameter  AFPOINTER = "0b00000000000000";
   parameter  AFPOINTER1 = "0b00000000000000";
   parameter  FULLPOINTER = "0b00000000000000";
   parameter  FULLPOINTER1 = "0b00000000000000";
   parameter  EMPTYPOINTER = "0b00000";
   parameter  EMPTYPOINTER1 = "0b000000";
   parameter  USE_EMPTYPOINTER = "FALSE";
   parameter  GSR = "DISABLED";
   parameter FIFO_CNT_CK_SEL = "CLKR";	//This parameter is only used for simulation: "CLKR" "CLKW"
output   DC0, DC1, DC2, DC3, DC4, DC5, DC6, DC7, DC8,
         DC9, DC10, DC11, DC12, DC13, DC14, DC15;
input    DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8,
         DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
         DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26,
         DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35,
         FULLI, CSW0, CSW1, CSW2, EMPTYI, CSR0, CSR1, CSR2, WE, RE, CLKW, CLKR, RST, RPRST,
         ORE;
output   DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8,
         DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
         DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26,
         DO27, DO28, DO29, DO30, DO31, DO32, DO33, DO34, DO35,
         EF, AEF, AFF, FF;
endmodule

(* black_box, dont_touch="true" *)
module xsFIFO8KB (DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8,
         DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
         DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26,
         DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35,
         FULLI, CSW0, CSW1, EMPTYI, CSR0, CSR1, WE, RE, CLKW, CLKR, RST, RPRST,
         ORE, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8,
         DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
         DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26,
         DO27, DO28, DO29, DO30, DO31, DO32, DO33, DO34, DO35,
         EF, AEF, AFF, FF)/*synthesis syn_black_box syn_noprune=1*/;
   parameter  DATA_WIDTH_W = 18;
   parameter  DATA_WIDTH_R = 18;
   parameter  REGMODE = "NOREG";
   parameter  RESETMODE = "ASYNC";
   parameter  ASYNC_RESET_RELEASE = "SYNC";
   parameter  CSDECODE_W = "0b00";
   parameter  CSDECODE_R = "0b00";
   parameter  AEPOINTER = "0b00000000000000";
   parameter  AEPOINTER1 = "0b00000000000000";
   parameter  AFPOINTER = "0b00000000000000";
   parameter  AFPOINTER1 = "0b00000000000000";
   parameter  FULLPOINTER = "0b00000000000000";
   parameter  FULLPOINTER1 = "0b00000000000000";
   parameter  EMPTYPOINTER = "0b00000";
   parameter  EMPTYPOINTER1 = "0b000000";
   parameter  USE_EMPTYPOINTER = "FALSE";
   parameter  GSR = "DISABLED";
input    DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8,
         DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
         DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26,
         DI27, DI28, DI29, DI30, DI31, DI32, DI33, DI34, DI35,
         FULLI, CSW0, CSW1, EMPTYI, CSR0, CSR1, WE, RE, CLKW, CLKR, RST, RPRST,
         ORE;
output   DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8,
         DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
         DO18, DO19, DO20, DO21, DO22, DO23, DO24, DO25, DO26,
         DO27, DO28, DO29, DO30, DO31, DO32, DO33, DO34, DO35,
         EF, AEF, AFF, FF;
endmodule

(* black_box, dont_touch="true" *)
module xsMULT18SA (
input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0,
input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0,
input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0,
input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, SL_LOAD,
input CLK3,CLK2,CLK1,CLK0,CE3,CE2,CE1,CE0,RST3,RST2,RST1,RST0,
input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9,
input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0,
input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9,
input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0,
output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9,
output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0,
output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9,
output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0,
output ROA17,ROA16,ROA15,ROA14,ROA13,ROA12,ROA11,ROA10,ROA9,
output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0,
output ROB17,ROB16,ROB15,ROB14,ROB13,ROB12,ROB11,ROB10,ROB9,
output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0,
output ROC17,ROC16,ROC15,ROC14,ROC13,ROC12,ROC11,ROC10,ROC9,
output ROC8,ROC7,ROC6,ROC5,ROC4,ROC3,ROC2,ROC1,ROC0,
output P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18,
output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0,
output SIGNEDP )/*synthesis syn_black_box syn_noprune=1*/;
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_INPUTC_CLK = "NONE";
parameter REG_INPUTC_CE = "CE0";
parameter REG_INPUTC_RST = "RST0";
parameter REG_PIPELINE_CLK = "NONE";
parameter REG_PIPELINE_CE = "CE0";
parameter REG_PIPELINE_RST = "RST0";
parameter REG_OUTPUT_CLK = "NONE";
parameter REG_OUTPUT_CE = "CE0";
parameter REG_OUTPUT_RST = "RST0";
parameter CLK0_DIV = "DISABLED";
parameter CLK1_DIV = "DISABLED";
parameter CLK2_DIV = "DISABLED";
parameter CLK3_DIV = "DISABLED";
parameter HIGHSPEED_CLK = "NONE";
parameter GSR = "ENABLED";
parameter CAS_MATCH_REG = "FALSE";
parameter SOURCEB_MODE = "B_SHIFT";
parameter MULT_BYPASS = "DISABLED";
parameter RESETMODE = "SYNC";
parameter REG2_INPUTA_BYP = "ENABLED";
parameter REG2_INPUTB_BYP = "ENABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsMULT9SA (
input A8,A7,A6,A5,A4,A3,A2,A1,A0,
input B8,B7,B6,B5,B4,B3,B2,B1,B0,
input C8,C7,C6,C5,C4,C3,C2,C1,C0,
input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, SL_LOAD,
input CLK3,CLK2,CLK1,CLK0,CE3,CE2,CE1,CE0,RST3,RST2,RST1,RST0,
input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0,
input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0,
output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0,
output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0,
output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0,
output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0,
output ROC8,ROC7,ROC6,ROC5,ROC4,ROC3,ROC2,ROC1,ROC0,
output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0,
output SIGNEDP )/*synthesis syn_black_box syn_noprune=1*/;
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_INPUTC_CLK = "NONE";
parameter REG_INPUTC_CE = "CE0";
parameter REG_INPUTC_RST = "RST0";
parameter REG_PIPELINE_CLK = "NONE";
parameter REG_PIPELINE_CE = "CE0";
parameter REG_PIPELINE_RST = "RST0";
parameter REG_OUTPUT_CLK = "NONE";
parameter REG_OUTPUT_CE = "CE0";
parameter REG_OUTPUT_RST = "RST0";
parameter CLK0_DIV = "DISABLED";
parameter CLK1_DIV = "DISABLED";
parameter CLK2_DIV = "DISABLED";
parameter CLK3_DIV = "DISABLED";
parameter HIGHSPEED_CLK = "NONE";
parameter GSR = "ENABLED";
parameter CAS_MATCH_REG = "FALSE";
parameter SOURCEB_MODE = "B_SHIFT";
parameter MULT_BYPASS = "DISABLED";
parameter RESETMODE = "SYNC";
parameter REG2_INPUTA_BYP = "ENABLED";
parameter REG2_INPUTB_BYP = "ENABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsMULT18 (P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18,
P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0,
SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9,
SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0,
SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9,
SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0,
ROA17,ROA16,ROA15,ROA14,ROA13,ROA12,ROA11,ROA10,ROA9,
ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0,
ROB17,ROB16,ROB15,ROB14,ROB13,ROB12,ROB11,ROB10,ROB9,
ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0,
A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0,
B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0,
SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9,
SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0,
SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9,
SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0,
SIGNEDA,SIGNEDB,CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3,SOURCEA,SOURCEB,SIGNEDP)/*synthesis syn_black_box syn_noprune=1*/;
input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0;
input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0;
input SIGNEDA,SIGNEDB,SOURCEA,SOURCEB;
input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3;
input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9;
input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0;
input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9;
input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0;
output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9;
output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0;
output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9;
output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0;
output ROA17,ROA16,ROA15,ROA14,ROA13,ROA12,ROA11,ROA10,ROA9;
output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0;
output ROB17,ROB16,ROB15,ROB14,ROB13,ROB12,ROB11,ROB10,ROB9;
output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0;
output P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18;
output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0;
output SIGNEDP;
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_PIPELINE_CLK = "NONE";
parameter REG_PIPELINE_CE = "CE0";
parameter REG_PIPELINE_RST = "RST0";
parameter REG_OUTPUT_CLK = "NONE";
parameter REG_OUTPUT_CE = "CE0";
parameter REG_OUTPUT_RST = "RST0";
parameter GSR = "ENABLED";
parameter CAS_MATCH_REG = "FALSE";
parameter MULT_BYPASS = "DISABLED";
parameter RESETMODE = "SYNC";
endmodule

(* black_box, dont_touch="true" *)
module xsALU54(
CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB,
A35,A34,A33,A32,A31,A30,A29,A28,A27,A26,A25,A24,A23,A22,A21,A20,A19,A18,
A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0,
B35,B34,B33,B32,B31,B30,B29,B28,B27,B26,B25,B24,B23,B22,B21,B20,B19,B18,
B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0,
C53,C52,C51,C50,C49,C48,C47,C46,C45,C44,C43,C42,C41,C40,C39,C38,C37,C36,
C35,C34,C33,C32,C31,C30,C29,C28,C27,C26,C25,C24,C23,C22,C21,C20,C19,C18,
C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0,
MA35,MA34,MA33,MA32,MA31,MA30,MA29,MA28,MA27,MA26,MA25,MA24,MA23,MA22,MA21,
MA20,MA19,MA18,MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,
MA4,MA3,MA2,MA1,MA0,
MB35,MB34,MB33,MB32,MB31,MB30,MB29,MB28,MB27,MB26,MB25,MB24,MB23,MB22,MB21,
MB20,MB19,MB18,MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,
MB4,MB3,MB2,MB1,MB0,
CIN53,CIN52,CIN51,CIN50,CIN49,CIN48,CIN47,CIN46,CIN45,CIN44,CIN43,CIN42,
CIN41,CIN40,CIN39,CIN38,CIN37,CIN36,CIN35,CIN34,CIN33,CIN32,CIN31,CIN30,CIN29,
CIN28,CIN27,CIN26,CIN25,CIN24,CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,
CIN15,CIN14,CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0,
OP10,OP9,OP8,OP7,OP6,OP5,OP4,OP3,OP2,OP1,OP0,SIGNEDCIN,
R53,R52,R51,R50,R49,R48,R47,R46,R45,R44,R43,R42,R41,R40,R39,R38,R37,R36,
R35,R34,R33,R32,R31,R30,R29,R28,R27,R26,R25,R24,R23,R22,R21,R20,R19,R18,
R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0,
EQZ,EQZM,EQOM,EQPAT,EQPATB,OVER,UNDER,OVERUNDER,SIGNEDR)/*synthesis syn_black_box syn_noprune=1*/;
input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3,SIGNEDIA,SIGNEDIB;
input A35,A34,A33,A32,A31,A30,A29,A28,A27,A26,A25,A24,A23,A22,A21,A20,A19,A18;
input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0;
input B35,B34,B33,B32,B31,B30,B29,B28,B27,B26,B25,B24,B23,B22,B21,B20,B19,B18;
input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0;
input C53,C52,C51,C50,C49,C48,C47,C46,C45,C44,C43,C42,C41,C40,C39,C38,C37,C36;
input C35,C34,C33,C32,C31,C30,C29,C28,C27,C26,C25,C24,C23,C22,C21,C20,C19,C18;
input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0;
input MA35,MA34,MA33,MA32,MA31,MA30,MA29,MA28,MA27,MA26,MA25,MA24,MA23,MA22,MA21;
input MA20,MA19,MA18,MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5;
input MA4,MA3,MA2,MA1,MA0;
input MB35,MB34,MB33,MB32,MB31,MB30,MB29,MB28,MB27,MB26,MB25,MB24,MB23,MB22,MB21;
input MB20,MB19,MB18,MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5;
input MB4,MB3,MB2,MB1,MB0;
input CIN53,CIN52,CIN51,CIN50,CIN49,CIN48,CIN47,CIN46,CIN45,CIN44,CIN43,CIN42;
input CIN41,CIN40,CIN39,CIN38,CIN37,CIN36,CIN35,CIN34,CIN33,CIN32,CIN31,CIN30,CIN29;
input CIN28,CIN27,CIN26,CIN25,CIN24,CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16;
input CIN15,CIN14,CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0;
input OP10,OP9,OP8,OP7,OP6,OP5,OP4,OP3,OP2,OP1,OP0,SIGNEDCIN;
output R53,R52,R51,R50,R49,R48,R47,R46,R45,R44,R43,R42,R41,R40,R39,R38,R37,R36;
output R35,R34,R33,R32,R31,R30,R29,R28,R27,R26,R25,R24,R23,R22,R21,R20,R19,R18;
output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0;
output EQZ,EQZM,EQOM,EQPAT,EQPATB,OVER,UNDER,OVERUNDER,SIGNEDR;
parameter REG_INPUTC0_CLK = "NONE";
parameter REG_INPUTC0_CE = "CE0";
parameter REG_INPUTC0_RST = "RST0";
parameter REG_INPUTC1_CLK = "NONE";
parameter REG_INPUTC1_CE = "CE0";
parameter REG_INPUTC1_RST = "RST0";
parameter REG_OPCODEOP0_0_CLK = "NONE";
parameter REG_OPCODEOP0_0_CE  = "CE0";
parameter REG_OPCODEOP0_0_RST = "RST0";
parameter REG_OPCODEOP1_0_CLK = "NONE";
parameter REG_OPCODEOP0_1_CLK = "NONE";
parameter REG_OPCODEOP0_1_CE = "CE0";
parameter REG_OPCODEOP0_1_RST = "RST0";
parameter REG_OPCODEOP1_1_CLK = "NONE";
parameter REG_OPCODEIN_0_CLK = "NONE";
parameter REG_OPCODEIN_0_CE = "CE0";
parameter REG_OPCODEIN_0_RST = "RST0";
parameter REG_OPCODEIN_1_CLK = "NONE";
parameter REG_OPCODEIN_1_CE = "CE0";
parameter REG_OPCODEIN_1_RST = "RST0";
parameter REG_OUTPUT0_CLK = "NONE";
parameter REG_OUTPUT0_CE = "CE0";
parameter REG_OUTPUT0_RST = "RST0";
parameter REG_OUTPUT1_CLK = "NONE";
parameter REG_OUTPUT1_CE = "CE0";
parameter REG_OUTPUT1_RST = "RST0";
parameter REG_FLAG_CLK = "NONE";
parameter REG_FLAG_CE = "CE0";
parameter REG_FLAG_RST = "RST0";
parameter MCPAT_SOURCE = "STATIC";
parameter MASKPAT_SOURCE = "STATIC";
parameter MASK01 = "0x00000000000000";
parameter MCPAT = "0x00000000000000";
parameter MASKPAT = "0x00000000000000";
parameter RNDPAT = "0x00000000000000";
parameter GSR = "ENABLED";
parameter RESETMODE = "SYNC";
parameter MULT9_MODE = "DISABLED";
parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
parameter LEGACY = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsMULT9 (
A8,A7,A6,A5,A4,A3,A2,A1,A0,B8,B7,B6,B5,B4,B3,B2,B1,B0,
SIGNEDA,SIGNEDB,SOURCEA,SOURCEB,
CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,
SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0,
SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0,
SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0,
SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0,
ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0,
ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0,
P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0,
SIGNEDP)/*synthesis syn_black_box syn_noprune=1*/;
input A8,A7,A6,A5,A4,A3,A2,A1,A0;
input B8,B7,B6,B5,B4,B3,B2,B1,B0;
input SIGNEDA,SIGNEDB,SOURCEA,SOURCEB;
input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3;
input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0;
input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0;
output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0;
output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0;
output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0;
output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0;
output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0;
output SIGNEDP;
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_PIPELINE_CLK = "NONE";
parameter REG_PIPELINE_CE = "CE0";
parameter REG_PIPELINE_RST = "RST0";
parameter REG_OUTPUT_CLK = "NONE";
parameter REG_OUTPUT_CE = "CE0";
parameter REG_OUTPUT_RST = "RST0";
parameter CAS_MATCH_REG = "FALSE";
parameter MULT_BYPASS = "DISABLED";
parameter GSR = "ENABLED";
parameter RESETMODE = "SYNC";
endmodule

(* black_box, dont_touch="true" *)
module xsALU24(
MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,
MA4,MA3,MA2,MA1,MA0,
MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,
MB4,MB3,MB2,MB1,MB0,
CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,
CIN15,CIN14,CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0,
CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB,OPADDNSUB,OPCINSEL,
R23,R22,R21,R20,R19,R18,
R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0)/*synthesis syn_black_box syn_noprune=1*/;
input MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5;
input MA4,MA3,MA2,MA1,MA0;
input MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5;
input MB4,MB3,MB2,MB1,MB0;
input CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16;
input CIN15,CIN14,CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0;
input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3,SIGNEDIA,SIGNEDIB,OPADDNSUB,OPCINSEL;
output R23,R22,R21,R20,R19,R18;
output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0;
parameter REG_OUTPUT_CLK = "NONE";
parameter REG_OUTPUT_CE = "CE0";
parameter REG_OUTPUT_RST = "RST0";
parameter REG_OPCODE_0_CLK = "NONE";
parameter REG_OPCODE_0_CE  = "CE0";
parameter REG_OPCODE_0_RST = "RST0";
parameter REG_OPCODE_1_CLK = "NONE";
parameter REG_OPCODE_1_CE = "CE0";
parameter REG_OPCODE_1_RST = "RST0";
parameter GSR = "ENABLED";
parameter RESETMODE = "SYNC";
endmodule

(* black_box, dont_touch="true" *)
module xsPREADD9 (
input PA8,PA7,PA6,PA5,PA4,PA3,PA2,PA1,PA0,
input PB8,PB7,PB6,PB5,PB4,PB3,PB2,PB1,PB0,
input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0,
input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0,
input C8,C7,C6,C5,C4,C3,C2,C1,C0,
input SOURCEA,OPPRE,SL_LOAD,
input CLK3,CLK2,CLK1,CLK0,
input CE3,CE2,CE1,CE0,
input RST3,RST2,RST1,RST0,
output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0,
output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0,
output PO8,PO7,PO6,PO5,PO4,PO3,PO2,PO1,PO0 )/*synthesis syn_black_box syn_noprune=1*/;
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_INPUTC_CLK = "NONE";
parameter REG_INPUTC_CE = "CE0";
parameter REG_INPUTC_RST = "RST0";
parameter REG_OPPRE_CLK = "NONE";
parameter REG_OPPRE_CE = "CE0";
parameter REG_OPPRE_RST = "RST0";
parameter CLK0_DIV = "DISABLED";
parameter CLK1_DIV = "DISABLED";
parameter CLK2_DIV = "DISABLED";
parameter CLK3_DIV = "DISABLED";
parameter HIGHSPEED_CLK = "NONE";
parameter GSR = "ENABLED";
parameter CAS_MATCH_REG = "FALSE";
parameter SOURCEA_MODE = "A_SHIFT";
parameter SOURCEB_MODE = "SHIFT";
parameter FB_MUX = "B_SOURCE";
parameter RESETMODE = "SYNC";
parameter SYMMETRY_MODE = "DIRECT";
parameter REG2_INPUTA_BYP = "ENABLED";
parameter REG2_INPUTB_BYP = "ENABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsPREADD18 (
input PA17,PA16,PA15,PA14,PA13,PA12,PA11,PA10,PA9,PA8,PA7,PA6,
      PA5,PA4,PA3,PA2,PA1,PA0,
input PB17,PB16,PB15,PB14,PB13,PB12,PB11,PB10,PB9,PB8,PB7,PB6,
      PB5,PB4,PB3,PB2,PB1,PB0,
input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9,SRIA8,SRIA7,SRIA6,
      SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0,
input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9,SRIB8,SRIB7,SRIB6,
      SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0,
input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0,
input SOURCEA,OPPRE,SL_LOAD,
input CLK3,CLK2,CLK1,CLK0,
input CE3,CE2,CE1,CE0,
input RST3,RST2,RST1,RST0,
output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9,SROA8,SROA7,SROA6,
      SROA5,SROA4,SROA3,SROA2,SROA1,SROA0,
output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9,SROB8,SROB7,SROB6,
      SROB5,SROB4,SROB3,SROB2,SROB1,SROB0,
output PO17,PO16,PO15,PO14,PO13,PO12,PO11,PO10,PO9,PO8,PO7,PO6,
      PO5,PO4,PO3,PO2,PO1,PO0 )/*synthesis syn_black_box syn_noprune=1*/;
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_INPUTC_CLK = "NONE";
parameter REG_INPUTC_CE = "CE0";
parameter REG_INPUTC_RST = "RST0";
parameter REG_OPPRE_CLK = "NONE";
parameter REG_OPPRE_CE = "CE0";
parameter REG_OPPRE_RST = "RST0";
parameter CLK0_DIV = "DISABLED";
parameter CLK1_DIV = "DISABLED";
parameter CLK2_DIV = "DISABLED";
parameter CLK3_DIV = "DISABLED";
parameter HIGHSPEED_CLK = "NONE";
parameter GSR = "ENABLED";
parameter CAS_MATCH_REG = "FALSE";
parameter SOURCEA_MODE = "A_SHIFT";
parameter SOURCEB_MODE = "SHIFT";
parameter FB_MUX = "B_SOURCE";
parameter RESETMODE = "SYNC";
parameter SYMMETRY_MODE = "DIRECT";
parameter REG2_INPUTA_BYP = "ENABLED";
parameter REG2_INPUTB_BYP = "ENABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsALU54SA (
input CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB,SIGNEDCIN,SL_LOAD,
input A35,A34,A33,A32,A31,A30,A29,A28,A27,A26,A25,A24,A23,A22,A21,A20,A19,A18,
input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0,
input B35,B34,B33,B32,B31,B30,B29,B28,B27,B26,B25,B24,B23,B22,B21,B20,B19,B18,
input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0,
input C53,C52,C51,C50,C49,C48,C47,C46,C45,C44,C43,C42,C41,C40,C39,C38,C37,C36,
input C35,C34,C33,C32,C31,C30,C29,C28,C27,C26,C25,C24,C23,C22,C21,C20,C19,C18,
input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0,
input CFB53,CFB52,CFB51,CFB50,CFB49,CFB48,CFB47,CFB46,CFB45,CFB44,CFB43,CFB42,CFB41,
input CFB40,CFB39,CFB38,CFB37,CFB36,CFB35,CFB34,CFB33,CFB32,CFB31,CFB30,CFB29,CFB28,
input CFB27,CFB26,CFB25,CFB24,CFB23,CFB22,CFB21,CFB20,CFB19,CFB18,CFB17,CFB16,CFB15,
input CFB14,CFB13,CFB12,CFB11,CFB10,CFB9,CFB8,CFB7,CFB6,CFB5,CFB4,CFB3,CFB2,CFB1,CFB0,
input MA35,MA34,MA33,MA32,MA31,MA30,MA29,MA28,MA27,MA26,MA25,MA24,MA23,MA22,MA21,MA20,MA19,MA18,
input MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,MA4,MA3,MA2,MA1,MA0,
input MB35,MB34,MB33,MB32,MB31,MB30,MB29,MB28,MB27,MB26,MB25,MB24,MB23,MB22,MB21,MB20,MB19,MB18,
input MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,MB4,MB3,MB2,MB1,MB0,
input CIN53,CIN52,CIN51,CIN50,CIN49,CIN48,CIN47,CIN46,CIN45,CIN44,CIN43,CIN42,CIN41,
input CIN40,CIN39,CIN38,CIN37,CIN36,CIN35,CIN34,CIN33,CIN32,CIN31,CIN30,CIN29,CIN28,
input CIN27,CIN26,CIN25,CIN24,CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,CIN15,
input CIN14,CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0,
input OP10,OP9,OP8,OP7,OP6,OP5,OP4,OP3,OP2,OP1,OP0,
output R53,R52,R51,R50,R49,R48,R47,R46,R45,R44,R43,R42,R41,R40,R39,R38,R37,R36,
output R35,R34,R33,R32,R31,R30,R29,R28,R27,R26,R25,R24,R23,R22,R21,R20,R19,R18,
output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0,
output CO53,CO52,CO51,CO50,CO49,CO48,CO47,CO46,CO45,CO44,CO43,CO42,CO41,CO40,CO39,CO38,CO37,CO36,
output CO35,CO34,CO33,CO32,CO31,CO30,CO29,CO28,CO27,CO26,CO25,CO24,CO23,CO22,CO21,CO20,CO19,CO18,
output CO17,CO16,CO15,CO14,CO13,CO12,CO11,CO10,CO9,CO8,CO7,CO6,CO5,CO4,CO3,CO2,CO1,CO0,
output EQZ,EQZM,EQOM,EQPAT,EQPATB,OVER,UNDER,OVERUNDER,
output SIGNEDR )/*synthesis syn_black_box syn_noprune=1*/;
parameter REG_INPUTC0_CLK = "NONE"; // C[26:0]
parameter REG_INPUTC0_CE = "CE0";      // C[26:0]
parameter REG_INPUTC0_RST = "RST0";  // C[26:0]
parameter REG_INPUTC1_CLK = "NONE"; // C[53:27]
parameter REG_INPUTC1_CE = "CE0";      // C[53:27]
parameter REG_INPUTC1_RST = "RST0";  // C[53:27]
parameter REG_OPCODEOP0_0_CLK = "NONE"; // Input reg of OPCODE oper[0]
parameter REG_OPCODEOP0_0_CE = "CE0";   // Input reg of OPCODE oper[3:0]
parameter REG_OPCODEOP0_0_RST = "RST0"; // Input reg of OPCODE oper[3:0]
parameter REG_OPCODEOP1_0_CLK = "NONE"; // Input reg of OPCODE oper [3:1]
parameter REG_OPCODEOP0_1_CLK = "NONE"; // Pipeline reg of OPCODE oper[0]
parameter REG_OPCODEOP0_1_CE = "CE0";   // Pipeline reg of OPCODE oper[3:0]
parameter REG_OPCODEOP0_1_RST = "RST0"; // Pipeline reg of OPCODE oper[3:0]
parameter REG_OPCODEOP1_1_CLK = "NONE"; // Pipeline reg of OPCODE oper[3:1]
parameter REG_OPCODEIN_0_CLK = "NONE"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0]
parameter REG_OPCODEIN_0_CE = "CE0";   // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0]
parameter REG_OPCODEIN_0_RST = "RST0"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0]
parameter REG_OPCODEIN_1_CLK = "NONE"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0]
parameter REG_OPCODEIN_1_CE = "CE0";   // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0]
parameter REG_OPCODEIN_1_RST = "RST0"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0]
parameter REG_OUTPUT0_CLK = "NONE";
parameter REG_OUTPUT0_CE = "CE0";
parameter REG_OUTPUT0_RST = "RST0";
parameter REG_OUTPUT1_CLK = "NONE";
parameter REG_OUTPUT1_CE = "CE0";
parameter REG_OUTPUT1_RST = "RST0";
parameter REG_FLAG_CLK = "NONE";
parameter REG_FLAG_CE = "CE0";
parameter REG_FLAG_RST = "RST0";
parameter MCPAT_SOURCE = "STATIC";
parameter MASKPAT_SOURCE = "STATIC";
parameter MASK01 = "0x00000000000000";
parameter REG_INPUTCFB_CLK = "NONE";
parameter REG_INPUTCFB_CE = "CE0";
parameter REG_INPUTCFB_RST = "RST0";
parameter CLK0_DIV = "DISABLED";
parameter CLK1_DIV = "DISABLED";
parameter CLK2_DIV = "DISABLED";
parameter CLK3_DIV = "DISABLED";
parameter MCPAT = "0x00000000000000";
parameter MASKPAT = "0x00000000000000";
parameter RNDPAT = "0x00000000000000";
parameter GSR = "ENABLED";
parameter RESETMODE = "SYNC";
parameter MULT9_MODE = "DISABLED";
parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
parameter LEGACY = "DISABLED";
parameter HIGHSPEED_CLK = "NONE";
parameter REG2_OPCODEOP0_0_BYP = "ENABLED";
parameter REG2_OPCODEOP1_0_BYP = "ENABLED";
parameter REG2_OPCODEIN_0_BYP = "ENABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsALU24SA (
input CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB,SL_LOAD,
input MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,MA4,MA3,MA2,MA1,MA0,
input MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,MB4,MB3,MB2,MB1,MB0,
input CFB23,CFB22,CFB21,CFB20,CFB19,CFB18,CFB17,CFB16,CFB15,CFB14,
input CFB13,CFB12,CFB11,CFB10,CFB9,CFB8,CFB7,CFB6,CFB5,CFB4,CFB3,CFB2,CFB1,CFB0,
input CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,CIN15,CIN14,
input CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0,
input OPADDNSUB, OPCINSEL,
output R23,R22,R21,R20,R19,R18,
output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0,
output CO23,CO22,CO21,CO20,CO19,CO18,
output CO17,CO16,CO15,CO14,CO13,CO12,CO11,CO10,CO9,CO8,CO7,CO6,CO5,CO4,CO3,CO2,CO1,CO0 )/*synthesis syn_black_box syn_noprune=1*/;
parameter REG_OUTPUT_CLK = "NONE";
parameter REG_OUTPUT_CE = "CE0";
parameter REG_OUTPUT_RST = "RST0";
parameter REG_OPCODE_0_CLK = "NONE";
parameter REG_OPCODE_0_CE = "CE0";
parameter REG_OPCODE_0_RST = "RST0";
parameter REG_OPCODE_1_CLK = "NONE";
parameter REG_OPCODE_1_CE = "CE0";
parameter REG_OPCODE_1_RST = "RST0";
parameter REG_INPUTCFB_CLK = "NONE";
parameter REG_INPUTCFB_CE  = "CE0";
parameter REG_INPUTCFB_RST = "RST0";
parameter CLK0_DIV = "DISABLED";
parameter CLK1_DIV = "DISABLED";
parameter CLK2_DIV = "DISABLED";
parameter CLK3_DIV = "DISABLED";
parameter GSR = "ENABLED";
parameter RESETMODE = "SYNC";
parameter HIGHSPEED_CLK = "NONE";
parameter REG2_OPCODE_0_BYP = "ENABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsPLLSA (
   input    CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP,
            LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD,
            ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE,
            PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0,
            PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0,
            WBCLK, WBRST, WBSTB, WBWE,
            WBDATI7, WBDATI6, WBDATI5, WBDATI4, WBDATI3, WBDATI2, WBDATI1, WBDATI0,
            WBADDR4, WBADDR3, WBADDR2, WBADDR1, WBADDR0,
   output   CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK,
            PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0,
            PLLACK,
            WBDATO7, WBDATO6, WBDATO5, WBDATO4, WBDATO3, WBDATO2, WBDATO1, WBDATO0, WBACK,
            DPHSRC, CLKINTFB, CLKO5, CLKO6, CLKO7 )/*synthesis syn_black_box syn_noprune=1*/;
   parameter SPECTR_TEST_EN_USR = "FALSE";
   parameter CLKO5_SEL = "CLKO5"; // "CLKOPD" for legacy 12k clkopd
   parameter CLKO5_DIV = 8;
   parameter CLKO5_ENABLE = "ENABLED";
   parameter VCO_BYPASS_E0 = "DISABLED";
   parameter CLKO5_CPHASE = 0;
   parameter CLKO5_FPHASE = 0;
   parameter PREDIVIDER_MUXE1 = 0;
   parameter OUTDIVIDER_MUXE2 = "DIVE";
   parameter CLKOPD_DLY = 0; // not supported in mib yet ... ???
   //parameter CLKOPD_SIGN = "FALSE";
   parameter CLKO6_DIV = 8;
   parameter CLKO6_ENABLE = "ENABLED";
   parameter VCO_BYPASS_F0 = "DISABLED";
   parameter CLKO6_CPHASE = 0;
   parameter CLKO6_FPHASE = 0;
   parameter PREDIVIDER_MUXF1 = 0;
   parameter OUTDIVIDER_MUXF2 = "DIVF";
   parameter CLKO7_DIV = 8;
   parameter CLKO7_ENABLE = "ENABLED";
   parameter VCO_BYPASS_G0 = "DISABLED";
   parameter CLKO7_CPHASE = 0;
   parameter CLKO7_FPHASE = 0;
   parameter PREDIVIDER_MUXG1 = 0;
   parameter OUTDIVIDER_MUXG2 = "DIVG";
   parameter CLKI_DIV = 1;
   parameter CLKFB_DIV = 1;
   parameter CLKOP_DIV = 8;
   parameter CLKOS_DIV = 8;
   parameter CLKOS2_DIV = 8;
   parameter CLKOS3_DIV = 8;
   parameter CLKOP_ENABLE = "ENABLED";
   parameter CLKOS_ENABLE = "ENABLED";
   parameter CLKOS2_ENABLE = "ENABLED";
   parameter CLKOS3_ENABLE = "ENABLED";
   parameter VCO_BYPASS_A0 = "DISABLED";
   parameter VCO_BYPASS_B0 = "DISABLED";
   parameter VCO_BYPASS_C0 = "DISABLED";
   parameter VCO_BYPASS_D0 = "DISABLED";
   parameter CLKOP_CPHASE = 0;
   parameter CLKOS_CPHASE = 0;
   parameter CLKOS2_CPHASE = 0;
   parameter CLKOS3_CPHASE = 0;
   parameter CLKOP_FPHASE = 0;
   parameter CLKOS_FPHASE = 0;
   parameter CLKOS2_FPHASE = 0;
   parameter CLKOS3_FPHASE = 0;
   parameter FEEDBK_PATH = "CLKOP";
   parameter FRACN_ENABLE = "DISABLED";
   parameter FRACN_DIV = 0;
   parameter CLKOP_TRIM_POL = "RISING";
   parameter CLKOP_TRIM_DELAY = 0;
   parameter CLKOS_TRIM_POL = "RISING";
   parameter CLKOS_TRIM_DELAY = 0;
   parameter PLL_USE_WB = "DISABLED";
   parameter PREDIVIDER_MUXA1 = 0;
   parameter PREDIVIDER_MUXB1 = 0;
   parameter PREDIVIDER_MUXC1 = 0;
   parameter PREDIVIDER_MUXD1 = 0;
   parameter OUTDIVIDER_MUXA2 = "DIVA";
   parameter OUTDIVIDER_MUXB2 = "DIVB";
   parameter OUTDIVIDER_MUXC2 = "DIVC";
   parameter OUTDIVIDER_MUXD2 = "DIVD";
   parameter PLL_LOCK_MODE = 0;
   parameter STDBY_ENABLE = "DISABLED";
   parameter DPHASE_SOURCE = "DISABLED";
   parameter PLLRST_ENA = "DISABLED";
   parameter MRST_ENA = "DISABLED";
   parameter DCRST_ENA = "DISABLED";
   parameter DDRST_ENA = "DISABLED";
   parameter INTFB_WAKE = "DISABLED";
   parameter EN_PHI = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsCLA (
  CO,
  O,
  CI,
  CYINIT,
  DI,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output [3:0] CO;
   output [3:0] O;
   input CI;
   input CYINIT;
   input [3:0] DI;
   input [3:0] S;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1 (
  Q,
  C,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, D;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1C1 (
  Q,
  C,
  CLR,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, CLR, D;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1C1E1 (
  Q,
  C,
  CE,
  CLR,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_CLR_INVERTED = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
   output Q;
   input C, CE, CLR, D;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0C1E1 (
  Q,
  C,
  CE,
  CLR,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, CE, CLR, D;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0C1 (
  Q,
  C,
  CLR,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, CLR, D;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1E1 (
  Q,
  C,
  CE,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, CE, D;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0E1 (
  Q,
  C,
  CE,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, CE, D;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1P1 (
  Q,
  C,
  D,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input C, D, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1P1E1 (
  Q,
  C,
  CE,
  D,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [0:0] INIT = 1'b1;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_PRE_INVERTED = 1'b0;
   output Q;
   input C, CE, D, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0P1E1 (
  Q,
  C,
  CE,
  D,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input C, CE, D, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0P1 (
  Q,
  C,
  D,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input C, D, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1R1 (
  Q,
  C,
  D,
  R
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, D, R;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1R1E1 (
  Q,
  C,
  CE,
  D,
  R
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_R_INVERTED = 1'b0;
   output Q;
   input C, CE, D, R;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0R1E1 (
  Q,
  C,
  CE,
  D,
  R
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, CE, D, R;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0R1 (
  Q,
  C,
  D,
  R
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, D, R;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1S1 (
  Q,
  C,
  D,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input C, D, S;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K1S1E1 (
  Q,
  C,
  CE,
  D,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [0:0] INIT = 1'b1;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_S_INVERTED = 1'b0;
   output Q;
   input C, CE, D, S;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0S1E1 (
  Q,
  C,
  CE,
  D,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input C, CE, D, S;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0S1 (
  Q,
  C,
  D,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input C, D, S;
endmodule

(* black_box, dont_touch="true" *)
module xsDFFSA_K0 (
  Q,
  C,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input C, D;
endmodule

(* black_box, dont_touch="true" *)
module xs0 (
  G
)/*synthesis syn_black_box syn_noprune=1*/;
   output G;
endmodule

(* black_box, dont_touch="true" *)
module xsINVSA (
  O,
  I
)/*synthesis syn_black_box syn_noprune=1*/;
   output O;
   input I;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K1 (
  Q,
  D,
  G
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input D, G;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K1C1 (
  Q,
  CLR,
  D,
  G
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input CLR, D, G;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K1C1E1 (
  Q,
  CLR,
  D,
  G,
  GE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_CLR_INVERTED = 1'b0;
  parameter [0:0] IS_G_INVERTED = 1'b0;
   output Q;
   input CLR, D, G, GE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K0C1E1 (
  Q,
  CLR,
  D,
  G,
  GE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input CLR, D, G, GE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K0C1 (
  Q,
  CLR,
  D,
  G
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input CLR, D, G;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K1E1 (
  Q,
  D,
  G,
  GE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input D, G, GE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K0E1 (
  Q,
  D,
  G,
  GE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input D, G, GE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K1P1 (
  Q,
  D,
  G,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input D, G, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K1P1E1 (
  Q,
  D,
  G,
  GE,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [0:0] INIT = 1'b1;
  parameter [0:0] IS_G_INVERTED = 1'b0;
  parameter [0:0] IS_PRE_INVERTED = 1'b0;
   output Q;
   input D, G, GE, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K0P1E1 (
  Q,
  D,
  G,
  GE,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input D, G, GE, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K0P1 (
  Q,
  D,
  G,
  PRE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b1;
   output Q;
   input D, G, PRE;
endmodule

(* black_box, dont_touch="true" *)
module xsLATSA_K0 (
  Q,
  D,
  G
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 1'b0;
   output Q;
   input D, G;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA1 (
  O,
  I0
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [1:0] INIT = 2'h0;
   output O;
   input I0;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA1_D (
  LO,
  O,
  I0
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 2'h0;
   output LO, O;
   input I0;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA1_L (
  LO,
  I0
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 2'h0;
   output LO;
   input I0;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA2 (
  O,
  I0,
  I1
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [3:0] INIT = 4'h0;
   output O;
   input I0, I1;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA2_D (
  LO,
  O,
  I0,
  I1
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 4'h0;
   output LO, O;
   input I0, I1;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA2_L (
  LO,
  I0,
  I1
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 4'h0;
   output LO;
   input I0, I1;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA3 (
  O,
  I0,
  I1,
  I2
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [7:0] INIT = 8'h00;
   output O;
   input I0, I1, I2;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA3_D (
  LO,
  O,
  I0,
  I1,
  I2
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 8'h00;
   output LO, O;
   input I0, I1, I2;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA3_L (
  LO,
  I0,
  I1,
  I2
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 8'h00;
   output LO;
   input I0, I1, I2;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA4 (
  O,
  I0,
  I1,
  I2,
  I3
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [15:0] INIT = 16'h0000;
   output O;
   input I0, I1, I2, I3;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA4_D (
  LO,
  O,
  I0,
  I1,
  I2,
  I3
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output O, LO;
   input I0, I1, I2, I3;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA4_L (
  LO,
  I0,
  I1,
  I2,
  I3
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output LO;
   input I0, I1, I2, I3;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA5 (
  O,
  I0,
  I1,
  I2,
  I3,
  I4
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [31:0] INIT = 32'h00000000;
   output O;
   input I0, I1, I2, I3, I4;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA5_D (
  LO,
  O,
  I0,
  I1,
  I2,
  I3,
  I4
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 32'h00000000;
   output LO, O;
   input I0, I1, I2, I3, I4;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA5_L (
  LO,
  I0,
  I1,
  I2,
  I3,
  I4
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 32'h00000000;
   output LO;
   input I0, I1, I2, I3, I4;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA6 (
  O,
  I0,
  I1,
  I2,
  I3,
  I4,
  I5
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [63:0] INIT = 64'h0000000000000000;
   output O;
   input I0, I1, I2, I3, I4, I5;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA6_2 (
  O6,
  O5,
  I0,
  I1,
  I2,
  I3,
  I4,
  I5
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [63:0] INIT = 64'h0000000000000000;
   output O6, O5;
   input I0, I1, I2, I3, I4, I5;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA6_D (
  LO,
  O,
  I0,
  I1,
  I2,
  I3,
  I4,
  I5
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 64'h0000000000000000;
   output LO, O;
   input I0, I1, I2, I3, I4, I5;
endmodule

(* black_box, dont_touch="true" *)
module xsLUTSA6_L (
  LO,
  I0,
  I1,
  I2,
  I3,
  I4,
  I5
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 64'h0000000000000000;
   output LO;
   input I0, I1, I2, I3, I4, I5;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXCY (
  O,
  CI,
  DI,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output O;
   input CI, DI, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXCY_D (
  LO,
  O,
  CI,
  DI,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO, O;
   input CI, DI, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXCY_L (
  LO,
  CI,
  DI,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO;
   input CI, DI, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF5 (
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF5_D (
  LO,
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO, O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF5_L (
  LO,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF6 (
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF6_D (
  LO,
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO, O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF6_L (
  LO,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF7 (
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF7_D (
  LO,
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO, O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF7_L (
  LO,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF8 (
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF8_D (
  LO,
  O,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO, O;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsMUXF8_L (
  LO,
  I0,
  I1,
  S
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO;
   input I0, I1, S;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM128X1D (
  DPO,
  SPO,
  A,
  D,
  DPRA,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [127:0] INIT = 128'h0;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output DPO, SPO;
   input D;
   input WCLK;
   input WE;
   input [6:0] A;
   input [6:0] DPRA;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM128X1S (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5,
  A6,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [127:0] INIT = 128'h0;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output O;
   input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM256X1S (
  O,
  A,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [255:0] INIT = 256'h0;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output O;
   input D;
   input WCLK;
   input WE;
   input [7:0] A;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM32M (
  DOA,
  DOB,
  DOC,
  DOD,
  ADDRA,
  ADDRB,
  ADDRC,
  ADDRD,
  DIA,
  DIB,
  DIC,
  DID,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [63:0] INIT_A = 64'h0000000000000000;
  parameter [63:0] INIT_B = 64'h0000000000000000;
  parameter [63:0] INIT_C = 64'h0000000000000000;
  parameter [63:0] INIT_D = 64'h0000000000000000;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output [1:0] DOA;
   output [1:0] DOB;
   output [1:0] DOC;
   output [1:0] DOD;
   input WCLK;
   input WE;
   input [1:0] DIA;
   input [1:0] DIB;
   input [1:0] DIC;
   input [1:0] DID;
   input [4:0] ADDRA;
   input [4:0] ADDRB;
   input [4:0] ADDRC;
   input [4:0] ADDRD;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM32X1D (
  DPO,
  SPO,
  A0,
  A1,
  A2,
  A3,
  A4,
  D,
  DPRA0,
  DPRA1,
  DPRA2,
  DPRA3,
  DPRA4,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [31:0] INIT = 32'h0;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output DPO, SPO;
   input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM32X1S (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [31:0] INIT = 32'h0;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output O;
   input A0, A1, A2, A3, A4, D, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM32X1S_1 (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 32'h00000000;
   output O;
   input A0, A1, A2, A3, A4, D, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM32X2S (
  O0,
  O1,
  A0,
  A1,
  A2,
  A3,
  A4,
  D0,
  D1,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT_00 = 32'h00000000;
   parameter INIT_01 = 32'h00000000;
   output O0, O1;
   input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM32X4S (
  O0,
  O1,
  O2,
  O3,
  A0,
  A1,
  A2,
  A3,
  A4,
  D0,
  D1,
  D2,
  D3,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT_00 = 32'h00000000;
   parameter INIT_01 = 32'h00000000;
   parameter INIT_02 = 32'h00000000;
   parameter INIT_03 = 32'h00000000;
   output O0, O1, O2, O3;
   input A0, A1, A2, A3, A4, D0, D1, D2, D3, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM32X8S (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT_00 = 32'h00000000;
   parameter INIT_01 = 32'h00000000;
   parameter INIT_02 = 32'h00000000;
   parameter INIT_03 = 32'h00000000;
   parameter INIT_04 = 32'h00000000;
   parameter INIT_05 = 32'h00000000;
   parameter INIT_06 = 32'h00000000;
   parameter INIT_07 = 32'h00000000;
   output [7:0] O;
   input A0, A1, A2, A3, A4, WCLK, WE;
   input [7:0] D;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM64M (
  DOA,
  DOB,
  DOC,
  DOD,
  ADDRA,
  ADDRB,
  ADDRC,
  ADDRD,
  DIA,
  DIB,
  DIC,
  DID,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [63:0] INIT_A = 64'h0000000000000000;
  parameter [63:0] INIT_B = 64'h0000000000000000;
  parameter [63:0] INIT_C = 64'h0000000000000000;
  parameter [63:0] INIT_D = 64'h0000000000000000;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output DOA;
   output DOB;
   output DOC;
   output DOD;
   input DIA;
   input DIB;
   input DIC;
   input DID;
   input WCLK;
   input WE;
   input [5:0] ADDRA;
   input [5:0] ADDRB;
   input [5:0] ADDRC;
   input [5:0] ADDRD;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM64X1D (
  DPO,
  SPO,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5,
  D,
  DPRA0,
  DPRA1,
  DPRA2,
  DPRA3,
  DPRA4,
  DPRA5,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [63:0] INIT = 64'h0;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output DPO, SPO;
   input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM64X1S (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [63:0] INIT = 64'h0;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
   output O;
   input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM64X1S_1 (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 64'h0000000000000000;
   output O;
   input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM64X2S (
  O0,
  O1,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5,
  D0,
  D1,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT_00 = 64'h0000000000000000;
   parameter INIT_01 = 64'h0000000000000000;
   output O0, O1;
   input A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM16X1D (
  DPO,
  SPO,
  A0,
  A1,
  A2,
  A3,
  D,
  DPRA0,
  DPRA1,
  DPRA2,
  DPRA3,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output DPO, SPO;
   input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM16X1D_1 (
  DPO,
  SPO,
  A0,
  A1,
  A2,
  A3,
  D,
  DPRA0,
  DPRA1,
  DPRA2,
  DPRA3,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output DPO, SPO;
   input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM16X1S (
  O,
  A0,
  A1,
  A2,
  A3,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output O;
   input A0, A1, A2, A3, D, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM16X1S_1 (
  O,
  A0,
  A1,
  A2,
  A3,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output O;
   input A0, A1, A2, A3, D, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM16X2S (
  O0,
  O1,
  A0,
  A1,
  A2,
  A3,
  D0,
  D1,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT_00 = 16'h0000;
   parameter INIT_01 = 16'h0000;
   output O0, O1;
   input A0, A1, A2, A3, D0, D1, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM16X4S (
  O0,
  O1,
  O2,
  O3,
  A0,
  A1,
  A2,
  A3,
  D0,
  D1,
  D2,
  D3,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT_00 = 16'h0000;
   parameter INIT_01 = 16'h0000;
   parameter INIT_02 = 16'h0000;
   parameter INIT_03 = 16'h0000;
   output O0, O1, O2, O3;
   input A0, A1, A2, A3, D0, D1, D2, D3, WCLK, WE;
endmodule

(* black_box, dont_touch="true" *)
module xsLRAM16X8S (
  O,
  A0,
  A1,
  A2,
  A3,
  D,
  WCLK,
  WE
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT_00 = 16'h0000;
   parameter INIT_01 = 16'h0000;
   parameter INIT_02 = 16'h0000;
   parameter INIT_03 = 16'h0000;
   parameter INIT_04 = 16'h0000;
   parameter INIT_05 = 16'h0000;
   parameter INIT_06 = 16'h0000;
   parameter INIT_07 = 16'h0000;
   output [7:0] O;
   input A0, A1, A2, A3, WCLK, WE;
   input [7:0] D;
endmodule

(* black_box, dont_touch="true" *)
module xsLROM128X1 (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5,
  A6
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 128'h00000000000000000000000000000000;
   output O;
   input A0, A1, A2, A3, A4, A5, A6;
endmodule

(* black_box, dont_touch="true" *)
module xsLROM16X1 (
  O,
  A0,
  A1,
  A2,
  A3
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output O;
   input A0, A1, A2, A3;
endmodule

(* black_box, dont_touch="true" *)
module xsLROM256X1 (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5,
  A6,
  A7
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
   output O;
   input A0, A1, A2, A3, A4, A5, A6, A7;
endmodule

(* black_box, dont_touch="true" *)
module xsLROM32X1 (
  O,
  A0,
  A1,
  A2,
  A3,
  A4
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 32'h00000000;
   output O;
   input A0, A1, A2, A3, A4;
endmodule

(* black_box, dont_touch="true" *)
module xsLROM64X1 (
  O,
  A0,
  A1,
  A2,
  A3,
  A4,
  A5
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 64'h0000000000000000;
   output O;
   input A0, A1, A2, A3, A4, A5;
endmodule

(* black_box, dont_touch="true" *)
module xsSRL16 (
  Q,
  A0,
  A1,
  A2,
  A3,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output Q;
   input A0, A1, A2, A3, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRL16E (
  Q,
  A0,
  A1,
  A2,
  A3,
  CE,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [15:0] INIT = 16'h0000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;
   output Q;
   input A0, A1, A2, A3, CE, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRL16E_1 (
  Q,
  A0,
  A1,
  A2,
  A3,
  CE,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output Q;
   input A0, A1, A2, A3, CE, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRL16_1 (
  Q,
  A0,
  A1,
  A2,
  A3,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output Q;
   input A0, A1, A2, A3, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRLC16 (
  Q,
  Q15,
  A0,
  A1,
  A2,
  A3,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output Q, Q15;
   input A0, A1, A2, A3, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRLC16E (
  Q,
  Q15,
  A0,
  A1,
  A2,
  A3,
  CE,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [15:0] INIT = 16'h0000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;
   output Q, Q15;
   input A0, A1, A2, A3, CE, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRLC16E_1 (
  Q,
  Q15,
  A0,
  A1,
  A2,
  A3,
  CE,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output Q, Q15;
   input A0, A1, A2, A3, CE, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRLC16_1 (
  Q,
  Q15,
  A0,
  A1,
  A2,
  A3,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
   parameter INIT = 16'h0000;
   output Q, Q15;
   input A0, A1, A2, A3, CLK, D;
endmodule

(* black_box, dont_touch="true" *)
module xsSRLC32E (
  Q,
  Q31,
  A,
  CE,
  CLK,
  D
)/*synthesis syn_black_box syn_noprune=1*/;
  parameter [31:0] INIT = 32'h00000000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;
   output Q;
   output Q31;
   input CE, CLK, D;
   input [4:0] A;
endmodule

(* black_box, dont_touch="true" *)
module xsCLKBRANCH (
  CLKI,
  TO_PCLK,
  TO_NCLK,
  TO_RCLK
)/*synthesis syn_black_box syn_noprune=1*/;
   input  CLKI;
   output TO_PCLK;
   output TO_NCLK;
   output TO_RCLK;
endmodule

(* black_box, dont_touch="true" *)
module xs1 (
  P
)/*synthesis syn_black_box syn_noprune=1*/;
   output P;
endmodule

(* black_box, dont_touch="true" *)
module xsXORCY (
  O,
  CI,
  LI
)/*synthesis syn_black_box syn_noprune=1*/;
   output O;
   input CI, LI;
endmodule

(* black_box, dont_touch="true" *)
module xsXORCY_D (
  LO,
  O,
  CI,
  LI
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO, O;
   input CI, LI;
endmodule

(* black_box, dont_touch="true" *)
module xsXORCY_L (
  LO,
  CI,
  LI
)/*synthesis syn_black_box syn_noprune=1*/;
   output LO;
   input CI, LI;
endmodule

(* black_box, dont_touch="true" *)
module xsDDRDLL (CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4,
                DCNTL3, DCNTL2, DCNTL1, DCNTL0, DIVOSC)/*synthesis syn_black_box syn_noprune=1*/;
parameter FORCE_MAX_DELAY = "NO";
parameter GSR = "ENABLED";
parameter   LOCK_CYC   = 200;
parameter CSCALE_EN = "FALSE";
parameter CSCALE = 0;
input  CLK, RST, UDDCNTLN, FREEZE;
output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0;
output DIVOSC;
endmodule

(* black_box, dont_touch="true" *)
module xsDDRDLLB (CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL8, DCNTL7, DCNTL6, DCNTL5, DCNTL4,
                DCNTL3, DCNTL2, DCNTL1, DCNTL0, DIVOSC)/*synthesis syn_black_box syn_noprune=1*/;
parameter FORCE_MAX_DELAY = "NO";
parameter GSR = "ENABLED";
parameter   LOCK_CYC   = 200;
parameter CSCALE_EN = "FALSE";
parameter CSCALE = 0;
input  CLK, RST, UDDCNTLN, FREEZE;
output LOCK, DDRDEL, DCNTL8, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0;
output DIVOSC;
endmodule

(* black_box, dont_touch="true" *)
module xsDDRDLLC (
    ECLK_DETECT_FLAG,
    CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL8, DCNTL7, DCNTL6, DCNTL5, DCNTL4,
    DCNTL3, DCNTL2, DCNTL1, DCNTL0, DIVOSC)/*synthesis syn_black_box syn_noprune=1*/;
parameter FORCE_MAX_DELAY = "NO";
parameter GSR = "ENABLED";
parameter   LOCK_CYC   = 200;
parameter CSCALE_EN = "FALSE";
parameter CSCALE = 0;
output ECLK_DETECT_FLAG;
input  CLK, RST, UDDCNTLN, FREEZE;
output LOCK, DDRDEL, DCNTL8, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0;
output DIVOSC;
endmodule

(* black_box, dont_touch="true" *)
module xsDQSBUF(DQSI, READ3, READ2, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
       ECLK, ECLK90, SCLK, //DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3,
       //DYNDELAY2, DYNDELAY1, DYNDELAY0,
       RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
       SLIP, SWITCH,
       SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELA8, SELA9, SELA10,
       SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10,
       CDRCLK, NEXTCLK, DIVCLK,
       DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID,
       BURSTDET, RDCFLAG, WRCFLAG)/*synthesis syn_black_box syn_noprune=1*/;
input  DQSI, READ3, READ2, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL;
input  ECLK, ECLK90, SCLK;//, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3;
//input  DYNDELAY2, DYNDELAY1, DYNDELAY0;
input  RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE;
input  SLIP, SWITCH;
input  SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELA8, SELA9, SELA10;
input  SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10;
output CDRCLK, NEXTCLK, DIVCLK;
output DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID;
output BURSTDET, RDCFLAG, WRCFLAG;
   parameter CONTINUE_READ = "FALSE";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
   parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LI_DEL_VAL = 0;
   parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LO_DEL_VAL = 0;
   parameter GSR = "ENABLED";
   parameter DDRXMODE = 0;
   parameter DIV = 0;
   parameter CDR = "FALSE";
//   parameter GEARING_MODE = "X2";          // "X2", "X4"
   // these 2 parameter must be same as releated DDRDLL
   parameter CSCALE_EN = "FALSE";
   parameter CSCALE = 0;
   parameter DQSR90_INSEL = "DQSBUF"; // DQSTREE
   parameter DQSW270_INSEL = "DQSBUF"; // DQSTREE
   parameter DQSW_INSEL = "DQSBUF"; // DQSTREE
   parameter READ_ENA_DELAY = "0.3NS"; // 0.8NS
endmodule

(* black_box, dont_touch="true" *)
module xsDQSBUFN(DQSI, READ3, READ2, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
       ECLK, ECLK90, SCLK, //DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3,
       //DYNDELAY2, DYNDELAY1, DYNDELAY0,
       RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
       SLIP, SWITCH,
       SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELA8, SELA9, SELA10,
       SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10,
       CDRCLK, NEXTCLK, DIVCLK,
       DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID,
       BURSTDET, RDCFLAG, WRCFLAG)/*synthesis syn_black_box syn_noprune=1*/;
input  DQSI, READ3, READ2, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL;
input  ECLK, ECLK90, SCLK;//, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3;
//input  DYNDELAY2, DYNDELAY1, DYNDELAY0;
input  RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE;
input  SLIP, SWITCH;
input  SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELA8, SELA9, SELA10;
input  SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10;
output CDRCLK, NEXTCLK, DIVCLK;
output DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID;
output BURSTDET, RDCFLAG, WRCFLAG;
   parameter CONTINUE_READ = "FALSE";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
   parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LI_DEL_VAL = 0;
   parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LO_DEL_VAL = 0;
   parameter GSR = "ENABLED";
   parameter DDRXMODE = 0;
   parameter DIV = 0;
   parameter CDR = "FALSE";
//   parameter GEARING_MODE = "X2";          // "X2", "X4"
   // these 2 parameter must be same as releated DDRDLL
   parameter CSCALE_EN = "FALSE";
   parameter CSCALE = 0;
   parameter DQSR90_INSEL = "DQSBUF"; // DQSTREE
   parameter DQSW270_INSEL = "DQSBUF"; // DQSTREE
   parameter DQSW_INSEL = "DQSBUF"; // DQSTREE
   parameter READ_ENA_DELAY = "0.0NS"; // 0.3NS 0.8NS
   parameter CUSTOM_READ_ENA_DELAY = 0; // 8 bits
   parameter USE_CUSTOM_READ_ENA_DELAY = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsDQSBUFP(DQSI, READ3, READ2, READ1, READ0, READCLKSEL3, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
       ECLK, ECLK90, SCLK, //DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3,
       //DYNDELAY2, DYNDELAY1, DYNDELAY0,
       RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
       SLIP, SWITCH,
       SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELAWL8, SELA9, SELA10, SELA11,
       SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10, SELB11,
       CDRCLK, NEXTCLK, DIVCLK,
       DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID,
       BURSTDET, RDCFLAG, WRCFLAG)/*synthesis syn_black_box syn_noprune=1*/;
input  DQSI, READ3, READ2, READ1, READ0, READCLKSEL3, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL;
input  ECLK, ECLK90, SCLK;//, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3;
//input  DYNDELAY2, DYNDELAY1, DYNDELAY0;
input  RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE;
input  SLIP, SWITCH;
input  SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELAWL8, SELA9, SELA10, SELA11;
input  SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10, SELB11;
output CDRCLK, NEXTCLK, DIVCLK;
output DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID;
output BURSTDET, RDCFLAG, WRCFLAG;
   parameter CONTINUE_READ = "FALSE";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
   parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LI_DEL_VAL = 0;
   parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LO_DEL_VAL = 0;
   parameter GSR = "ENABLED";
   parameter DDRXMODE = 0;
   parameter DIV = 0;
   parameter CDR = "FALSE";
//   parameter GEARING_MODE = "X2";          // "X2", "X4"
   // these 2 parameter must be same as releated DDRDLL
   parameter CSCALE_EN = "FALSE";
   parameter CSCALE = 0;
   //parameter DQSR90_INSEL = "DQSBUF"; // DQSTREE
   //parameter DQSW270_INSEL = "DQSBUF"; // DQSTREE
   //parameter DQSW_INSEL = "DQSBUF"; // DQSTREE
   parameter READ_ENA_DELAY = "0.0NS"; // 0.3NS 0.8NS
   parameter CUSTOM_READ_ENA_DELAY = 0; // 9 bits
   parameter USE_CUSTOM_READ_ENA_DELAY = "FALSE";
   parameter RSTN_PULSE_WIDTH_SEL = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsDQSBUFQ(
       RD_ENA_DLY_SEL_0, RD_ENA_DLY_SEL_1, RD_ENA_DLY_SEL_2, RD_ENA_DLY_SEL_3,
       RD90_MARGIN_PRESET_0, RD90_MARGIN_PRESET_1, RD90_MARGIN_PRESET_2, RD90_MARGIN_PRESET_3,
       RD90_MARGIN_PRESET_4, RD90_MARGIN_PRESET_5, RD90_MARGIN_PRESET_6, RD90_MARGIN_PRESET_7,
       RD90_MARGIN_PRESET_8, DQS_READ_SEL,
       DQSI, READ3, READ2, READ1, READ0, READCLKSEL3, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
       ECLK, ECLK90, SCLK, //DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3,
       //DYNDELAY2, DYNDELAY1, DYNDELAY0,
       RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
       SLIP, SWITCH,
       SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELAWL8, SELA9, SELA10, SELA11,
       SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10, SELB11,
       CDRCLK, NEXTCLK, DIVCLK,
       DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID,
       BURSTDET, RDCFLAG, WRCFLAG)/*synthesis syn_black_box syn_noprune=1*/;
input RD_ENA_DLY_SEL_0, RD_ENA_DLY_SEL_1, RD_ENA_DLY_SEL_2, RD_ENA_DLY_SEL_3;
input RD90_MARGIN_PRESET_0;
input RD90_MARGIN_PRESET_1;
input RD90_MARGIN_PRESET_2;
input RD90_MARGIN_PRESET_3;
input RD90_MARGIN_PRESET_4;
input RD90_MARGIN_PRESET_5;
input RD90_MARGIN_PRESET_6;
input RD90_MARGIN_PRESET_7;
input RD90_MARGIN_PRESET_8;
input DQS_READ_SEL;
input  DQSI, READ3, READ2, READ1, READ0, READCLKSEL3, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL;
input  ECLK, ECLK90, SCLK;//, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3;
//input  DYNDELAY2, DYNDELAY1, DYNDELAY0;
input  RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE;
input  SLIP, SWITCH;
input  SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELAWL8, SELA9, SELA10, SELA11;
input  SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10, SELB11;
output CDRCLK, NEXTCLK, DIVCLK;
output DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID;
output BURSTDET, RDCFLAG, WRCFLAG;
   parameter CONTINUE_READ = "FALSE";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
   parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LI_DEL_VAL = 0;
   parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LO_DEL_VAL = 0;
   parameter GSR = "ENABLED";
   parameter DDRXMODE = 0;
   parameter DIV = 0;
   parameter CDR = "FALSE";
//   parameter GEARING_MODE = "X2";          // "X2", "X4"
   // these 2 parameter must be same as releated DDRDLL
   parameter CSCALE_EN = "FALSE";
   parameter CSCALE = 0;
   //parameter DQSR90_INSEL = "DQSBUF"; // DQSTREE
   //parameter DQSW270_INSEL = "DQSBUF"; // DQSTREE
   //parameter DQSW_INSEL = "DQSBUF"; // DQSTREE
   parameter READ_ENA_DELAY = "0.0NS"; // 0.3NS 0.8NS
   parameter CUSTOM_READ_ENA_DELAY = 0; // 9 bits
   parameter USE_CUSTOM_READ_ENA_DELAY = "FALSE";
   parameter RSTN_PULSE_WIDTH_SEL = "FALSE";
   parameter RD90_MARGIN_SEL = "FALSE";
   parameter DDR3_DDR4_SEL = "DDR3";
endmodule

(* black_box, dont_touch="true" *)
module xsDQSBUFS(
       INIT_DONE, INPUT_FIFO_RST,
       RD_ENA_DLY_SEL_0, RD_ENA_DLY_SEL_1, RD_ENA_DLY_SEL_2, RD_ENA_DLY_SEL_3,
       RD90_MARGIN_PRESET_0, RD90_MARGIN_PRESET_1, RD90_MARGIN_PRESET_2, RD90_MARGIN_PRESET_3,
       RD90_MARGIN_PRESET_4, RD90_MARGIN_PRESET_5, RD90_MARGIN_PRESET_6, RD90_MARGIN_PRESET_7,
       RD90_MARGIN_PRESET_8, DQS_READ_SEL,
       DQSI, READ3, READ2, READ1, READ0, READCLKSEL3, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
       ECLK, ECLK90, SCLK, //DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3,
       //DYNDELAY2, DYNDELAY1, DYNDELAY0,
       RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
       SLIP, SWITCH,
       SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELAWL8, SELA9, SELA10, SELA11,
       SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10, SELB11,
       CDRCLK, NEXTCLK, DIVCLK,
       DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID,
       BURSTDET, RDCFLAG, WRCFLAG)/*synthesis syn_black_box syn_noprune=1*/;
input INIT_DONE;
input INPUT_FIFO_RST;
input RD_ENA_DLY_SEL_0, RD_ENA_DLY_SEL_1, RD_ENA_DLY_SEL_2, RD_ENA_DLY_SEL_3;
input RD90_MARGIN_PRESET_0;
input RD90_MARGIN_PRESET_1;
input RD90_MARGIN_PRESET_2;
input RD90_MARGIN_PRESET_3;
input RD90_MARGIN_PRESET_4;
input RD90_MARGIN_PRESET_5;
input RD90_MARGIN_PRESET_6;
input RD90_MARGIN_PRESET_7;
input RD90_MARGIN_PRESET_8;
input DQS_READ_SEL;
input  DQSI, READ3, READ2, READ1, READ0, READCLKSEL3, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL;
input  ECLK, ECLK90, SCLK;//, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3;
//input  DYNDELAY2, DYNDELAY1, DYNDELAY0;
input  RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE;
input  SLIP, SWITCH;
input  SELAWL0, SELAWL1, SELAWL2, SELAWL3, SELAWL4, SELAWL5, SELAWL6, SELAWL7, SELAWL8, SELA9, SELA10, SELA11;
input  SELB0, SELB1, SELB2, SELB3, SELB4, SELB5, SELB6, SELB7, SELB8, SELB9, SELB10, SELB11;
output CDRCLK, NEXTCLK, DIVCLK;
output DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID;
output BURSTDET, RDCFLAG, WRCFLAG;
   parameter CONTINUE_READ = "FALSE";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
   parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LI_DEL_VAL = 0;
   parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
   parameter DQS_LO_DEL_VAL = 0;
   parameter GSR = "ENABLED";
   parameter DDRXMODE = 0;
   parameter DIV = 0;
   parameter CDR = "FALSE";
//   parameter GEARING_MODE = "X2";          // "X2", "X4"
   // these 2 parameter must be same as releated DDRDLL
   parameter CSCALE_EN = "FALSE";
   parameter CSCALE = 0;
   //parameter DQSR90_INSEL = "DQSBUF"; // DQSTREE
   //parameter DQSW270_INSEL = "DQSBUF"; // DQSTREE
   //parameter DQSW_INSEL = "DQSBUF"; // DQSTREE
   parameter READ_ENA_DELAY = "0.0NS"; // 0.3NS 0.8NS
   parameter CUSTOM_READ_ENA_DELAY = 0; // 9 bits
   parameter USE_CUSTOM_READ_ENA_DELAY = "FALSE";
   parameter RSTN_PULSE_WIDTH_SEL = "FALSE";
   parameter RD90_MARGIN_SEL = "FALSE";
   parameter DDR3_DDR4_SEL = "DDR3";
   parameter DQSR90_INSEL = "DQSBUF"; // DQSTREE
   parameter DQSW270_INSEL = "DQSBUF"; // DQSTREE
   parameter DQSW_INSEL = "DQSBUF"; // DQSTREE
   parameter READ_CLK_SEL_CUT = "FALSE"; // TRUE
endmodule

(* black_box, dont_touch="true" *)
module xsIDDRSAX1(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, SCLK, RST, ALIGNWD, Q0, Q1)/*synthesis syn_black_box syn_noprune=1*/;
input  D, SCLK, RST, ALIGNWD;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsIDDRSAX2(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD, Q0, Q1, Q2, Q3)/*synthesis syn_black_box syn_noprune=1*/;
input  D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1, Q2, Q3;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsIDDRSA71(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6)/*synthesis syn_black_box syn_noprune=1*/;
input  D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1, Q2, Q3, Q4, Q5, Q6;
  parameter GSR = "ENABLED";
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsIDDRSAX4(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7)/*synthesis syn_black_box syn_noprune=1*/;
input  D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsIDDRSAX5(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9)/*synthesis syn_black_box syn_noprune=1*/;
input  D, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDRMDQIN(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, DQSR90, SCLK, RST, ALIGNWD, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1,
       WRPNTR0, Q0, Q1, QWL)/*synthesis syn_black_box syn_noprune=1*/;
input  D, DQSR90, SCLK, RST, ALIGNWD;
input  RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1, QWL;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsDDR2MDQIN(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, DQSR90, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1,
       WRPNTR0, Q0, Q1, Q2, Q3, QWL)/*synthesis syn_black_box syn_noprune=1*/;
input  D, DQSR90, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD;
input  RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1, Q2, Q3, QWL;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR3MDQIN(MONDIS0, MONDIS1, ACK, EDGE_PLUS, EDGE_MINUS,
    D, DQSR90, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1,
       WRPNTR0, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, QWL)/*synthesis syn_black_box syn_noprune=1*/;
input  D, DQSR90, CDRCLK, NEXTCLK, ECLK, SCLK, RST, ALIGNWD;
input  RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0;
input MONDIS0, MONDIS1, ACK;
output EDGE_PLUS, EDGE_MINUS;
output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, QWL;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  MON_ENABLE = "FALSE";
   parameter  MON_EDGE = "ONE"; // "ONE" or "TWO"
   parameter  SLIP_ENABLE = "FALSE";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsODDRSA(D0, D1, RST, SCLK, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, RST, SCLK;
   output Q;
  parameter GSR = "ENABLED";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
endmodule

(* black_box, dont_touch="true" *)
module xsODDRSAX2(D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK;
   output Q;
  parameter GSR = "ENABLED";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsODDRSA71(D0, D1, D2, D3, D4, D5, D6, RST, CDRCLK, NEXTCLK, ECLK, SCLK, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, D4, D5, D6, RST, CDRCLK, NEXTCLK, ECLK, SCLK;
   output Q;
  parameter GSR = "ENABLED";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsODDRSAX4(D0, D1, D2, D3, D4, D5, D6, D7, RST, CDRCLK, NEXTCLK, ECLK, SCLK, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, D4, D5, D6, D7, RST, CDRCLK, NEXTCLK, ECLK, SCLK;
   output Q;
  parameter GSR = "ENABLED";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsODDRSAX5(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, RST, CDRCLK, NEXTCLK, ECLK, SCLK, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, RST, CDRCLK, NEXTCLK, ECLK, SCLK;
   output Q;
  parameter GSR = "ENABLED";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsTDDRSA(T0, SCLK, RST, Q)/*synthesis syn_black_box syn_noprune=1*/;
input  T0, SCLK, RST;
output Q;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  REGSET = "SET";             // "SET", "RESET"
endmodule

(* black_box, dont_touch="true" *)
module xsDDRMDQOUT(D0, D1, RST, SCLK, DQSW270, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, RST, SCLK, DQSW270;
   output Q;
  parameter GSR = "ENABLED";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
endmodule

(* black_box, dont_touch="true" *)
module xsDDRMDQSOUT(D0, D1, RST, SCLK, DQSW, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, RST, SCLK, DQSW;
   output Q;
  parameter GSR = "ENABLED";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
endmodule

(* black_box, dont_touch="true" *)
module xsDDR2MDQOUT(D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270;
   output Q;
  parameter GSR = "ENABLED";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR2MDQSOUT(D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW;
   output Q;
  parameter GSR = "ENABLED";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR3MDQOUT(D0, D1, D2, D3, D4, D5, D6, D7, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, D4, D5, D6, D7, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270;
   output Q;
  parameter GSR = "ENABLED";
  parameter WRITE_LEVELING = "2T";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR3MDQSOUT(D0, D1, D2, D3, D4, D5, D6, D7, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, D4, D5, D6, D7, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW;
   output Q;
  parameter GSR = "ENABLED";
  parameter WRITE_LEVELING = "2T";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR2MADDRCMD(D0, D1, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270;
   output Q;
  parameter GSR = "ENABLED";
  parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR3MADDRCMD(D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270, Q)/*synthesis syn_black_box syn_noprune=1*/;
   input D0, D1, D2, D3, RST, CDRCLK, NEXTCLK, ECLK, SCLK, DQSW270;
   output Q;
  parameter GSR = "ENABLED";
  parameter WRITE_LEVELING = "2T";
  parameter ISI_ENABLE = "FALSE";
  parameter ISI_DELAY = 0; // 1 for 25ps; 2 for 50ps; 3 for 100ps;
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDRMDQTRIOUT(T0, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW270, RST, Q)/*synthesis syn_black_box syn_noprune=1*/;
input  T0, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW270, RST;
output Q;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  REGSET = "SET";             // "SET", "RESET"
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDRMDQSTRIOUT(T0, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW, RST, Q)/*synthesis syn_black_box syn_noprune=1*/;
input  T0, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW, RST;
output Q;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  REGSET = "SET";             // "SET", "RESET"
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR2MDQTRIOUT(T0, T1, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW270, RST, Q)/*synthesis syn_black_box syn_noprune=1*/;
input  T0, T1, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW270, RST;
output Q;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  REGSET = "SET";             // "SET", "RESET"
   parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR2MDQSTRIOUT(T0, T1, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW, RST, Q)/*synthesis syn_black_box syn_noprune=1*/;
input  T0, T1, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW, RST;
output Q;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  REGSET = "SET";             // "SET", "RESET"
   parameter  WL_ENABLE = "FALSE";
  parameter WRITE_LEVELING = "2T";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR3MDQTRIOUT(T0, T1, T2, T3, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW270, RST, Q)/*synthesis syn_black_box syn_noprune=1*/;
input  T0, T1, T2, T3, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW270, RST;
output Q;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  REGSET = "SET";             // "SET", "RESET"
  parameter WRITE_LEVELING = "2T";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsDDR3MDQSTRIOUT(T0, T1, T2, T3, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW, RST, Q)/*synthesis syn_black_box syn_noprune=1*/;
input  T0, T1, T2, T3, SCLK, CDRCLK, NEXTCLK, ECLK, DQSW, RST;
output Q;
   parameter  GSR = "ENABLED";            // "DISABLED", "ENABLED"
   parameter  REGSET = "SET";             // "SET", "RESET"
  parameter WRITE_LEVELING = "2T";
   parameter CRUCLK = "ECLK";             // "ECLK", "CDRCLK", "NEXTCLK"
endmodule

(* black_box, dont_touch="true" *)
module xsCLKDIVSA (CLKI, RST, ALIGNWD, CDIVX)/*synthesis syn_black_box syn_noprune=1*/;
   input CLKI, RST, ALIGNWD;
   output CDIVX;
   parameter GSR = "DISABLED";
   parameter DIV = "2.0";
endmodule

(* black_box, dont_touch="true" *)
module xsCLKDIV (
   input    RST, CLKI, ALIGNWD,
   output   CDIV1, CDIVX )/*synthesis syn_black_box syn_noprune=1*/;
   parameter  GSR = "DISABLED";
   parameter  DIV = "2.0";
endmodule

(* black_box, dont_touch="true" *)
module xsDCC (
   input    CLKI, CE,
   output   CLKO )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsDCCB (
   input    CLKI, CE,
   output   CLKO )/*synthesis syn_black_box syn_noprune=1*/;
   parameter [1:0] DELAY = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsCDELAY (
   input    I,
   output   O )/*synthesis syn_black_box syn_noprune=1*/;
   parameter [1:0] DELAY = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsDCLKSEL (CLK0, CLK1, SEL1, SEL0, MODESEL, DCSOUT)/*synthesis syn_black_box syn_noprune=1*/;
  input  CLK0, CLK1, SEL1, SEL0, MODESEL;
  output DCSOUT;
  parameter DCSMODE = "POS";
endmodule

(* black_box, dont_touch="true" *)
module xsECLKBCS (
input  CLK0, CLK1, SEL,
output ECSOUT )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsECLKSBK (
input  ECLKI, STOP,
output ECLKO )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsECLKSYNC (
   input    ECLKI, STOP,
   output   ECLKO )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsOSC (
   input    STDBY,
   output   OSC, SEDSTDBY )/*synthesis syn_black_box syn_noprune=1*/;
   parameter NOM_FREQ = "2.03";
   parameter NOM_DIV = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsPLLREFCS (
input CLK0,CLK1,SEL,
output PLLCSOUT )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsDLLDLY (A, DDRDEL, LOADN, MOVE, DIRECTION, CFLAG, Z)/*synthesis syn_black_box syn_noprune=1*/;
input A, DDRDEL, LOADN, MOVE, DIRECTION;
output CFLAG, Z;
   parameter DEL_ADJ  = "PLUS";
   parameter DEL_VAL = 0;
   // these 2 parameter must be same as releated DDRDLL
   parameter CSCALE_EN = "FALSE";
   parameter CSCALE = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsDELAYDYN_E1 (
input A, LOADN, MOVE, DIRECTION, MOVE_SEL,
output Z, CFLAG )/*synthesis syn_black_box syn_noprune=1*/;
parameter  DEVICE="SEAL_GENERAL"; // SEAL50K, SEAL30K
parameter  DEL_MODE = "USER_DEFINED";
parameter [6:0] DEL_VALUE = 0;
parameter [5:0] MOVE_CTRL = 0;
parameter  WAIT_FOR_EDGE = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsDELAYDYN (
input A, LOADN, MOVE, DIRECTION,
output Z, CFLAG )/*synthesis syn_black_box syn_noprune=1*/;
parameter  DEVICE="SEAL_GENERAL"; // SEAL50K, SEAL30K
parameter  DEL_MODE = "USER_DEFINED";
parameter  DEL_VALUE = 0;
parameter  WAIT_FOR_EDGE = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsDELAYSA (
input  A,
output  Z )/*synthesis syn_black_box syn_noprune=1*/;
parameter  DEVICE="SEAL_GENERAL"; // SEAL50K, SEAL30K
parameter  DEL_MODE = "USER_DEFINED";
parameter  DEL_VALUE = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsODELAY (
input  A,
output  Z )/*synthesis syn_black_box syn_noprune=1*/;
parameter  DEL_VALUE = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsCM3(
    // 30K new
    input DBG_SWDI_TMS,
    output DBG_SWDO,
    output DBG_SWDO_EN,
    input PB24_DO_C,
    input PB24_DO_D,
    input PB24_TO_C,
    input PB24_TO_D,
    output TDO_ENABLE,
    output TDO_TMS,
    input CS_TCK,
    input CS_TDI,
    output PCLKEN,
    input DFTSE,
    input DFTSI0,
    input DFTSI1,
    input DFTSI2,
//    output DFTSO0,
//    output DFTSO1,
//    output DFTSO2,
    input DFTTM,
    input [3:0] DMACBREQ,
    output [3:0] DMACCLR,
    input [3:0] DMACLBREQ,
    input [3:0] DMACLSREQ,
    input [3:0] DMACSREQ,
    output [3:0] DMACTC,

    // 46K orig
    input PLL_OUT,
    input PLL_USRCLK,
    input CLK_PAD,

    input CIBCLK, // CIB_CLK
    output CLKOUT,
    input CPURSTN, // FABRIC_CPU_RSTN
    input [15:0] EXTINT,
    input [31:0] GPIOI, // IO_EXP_PORT_I
    output [31:0] GPIOO, // IO_EXP_PORT_O_INT
    output [31:0] GPIOOEN, // IO_EXP_PORT_OEN_INT
    input [31:0] INITEXP0HADDR,
    input [2:0] INITEXP0HBURST,
    input INITEXP0HMASTLOCK,
    input [3:0] INITEXP0HPROT,
    output [31:0] INITEXP0HRDATA,
    output INITEXP0HREADY,
    output INITEXP0HRESP,
    input INITEXP0HSEL,
    input [2:0] INITEXP0HSIZE,
    input [1:0] INITEXP0HTRANS,
    input [31:0] INITEXP0HWDATA,
    input INITEXP0HWRITE,
    input [31:0] INITEXP1HADDR,
    input [2:0] INITEXP1HBURST,
    input INITEXP1HMASTLOCK,
    input [3:0] INITEXP1HPROT,
    output [31:0] INITEXP1HRDATA,
    output INITEXP1HREADY,
    output INITEXP1HRESP,
    input INITEXP1HSEL,
    input [2:0] INITEXP1HSIZE,
    input [1:0] INITEXP1HTRANS,
    input [31:0] INITEXP1HWDATA,
    input INITEXP1HWRITE,
    output MTX_CLK,
    input MTXRSTN, // FABRIC_MTX_RSTN
    input NSRST, // CS_
    input NTRST, // CS_
    output PCLK,
    output [31:0] TARGEXP0HADDR,
    output [2:0] TARGEXP0HBURST,
    output TARGEXP0HMASTLOCK,
    output [3:0] TARGEXP0HPROT,
    input [31:0] TARGEXP0HRDATA,
    output TARGEXP0HREADYMUX,
    input TARGEXP0HREADYOUT,
    input TARGEXP0HRESP,
    output TARGEXP0HSEL,
    output [2:0] TARGEXP0HSIZE,
    output [1:0] TARGEXP0HTRANS,
    output [31:0] TARGEXP0HWDATA,
    output TARGEXP0HWRITE,
    output [31:0] TARGEXP1HADDR,
    output [2:0] TARGEXP1HBURST,
    output TARGEXP1HMASTLOCK,
    output [3:0] TARGEXP1HPROT,
    input [31:0] TARGEXP1HRDATA,
    output TARGEXP1HREADYMUX,
    input TARGEXP1HREADYOUT,
    input TARGEXP1HRESP,
    output TARGEXP1HSEL,
    output [2:0] TARGEXP1HSIZE,
    output [1:0] TARGEXP1HTRANS,
    output [31:0] TARGEXP1HWDATA,
    output TARGEXP1HWRITE,
    output TRACECLK,  // CS_
    output [3:0] TRACEDATA, // CS_
    input TREECLK)/*synthesis syn_black_box syn_noprune=1*/;
parameter PCLK_DIV = 0; // PCLK_DIV 0-7
parameter CORECLK = "PLL_USRCLK"; // "CLK_TREE" "CLK_PAD" "PLL_OUT" "CIB_CLK"
parameter RSTN_ENABLE = "FALSE";
parameter MTXCLK = "CORECLK"; // "SOURCECLK"
parameter CORECLK_EN = "FALSE";
parameter CORE_SET = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsADC(
    input [1:0] IN,
    input [2:0] CHSL,
    input CLKL,
    output [11:0] DOUTL,
    output ENDL,
    input PDL,
    input SAMPL)/*synthesis syn_black_box syn_noprune=1*/;
parameter ADC_IFS = "CM3"; // "CIB"
parameter ADC_REFS = "VCCAUX"; // "2.5V"
endmodule

(* black_box, dont_touch="true" *)
module xsSADC_E1(
    output [2:0]CHNL_SEL_LAST,
    output CLK_TO_CIB,
    output BG_READY,
    output SYS_BUSY,
    output ALARM_OVERVOLT_AUX,
    output ALARM_OVERVOLT_INT,
    output ALARM_TEMP_85,
    output ALARM_TEMP_100,
    output ALARM_TEMP_125,
    output ALARM_OVERTEMP_L,
    output ALARM_OVERTEMP_H,
    output OVERTEMP_PD_FLAG,
    input OVERTEMP_PD_DIS,
    input MODE_SEL,
    input REF_SEL,
    input SYS_EN,
    input [7:0] IN,
    input [3:0] CHSL,
    input CLKL,
    output [11:0] DOUTL,
    output ENDL,
    input PDL,
    input SAMPL)/*synthesis syn_black_box syn_noprune=1*/;
parameter ADC_IFS = "CM3"; // "CIB"
//parameter ADC_REFS = "VCCAUX"; // "2.5V"
parameter /*[11:0]*/ OT_CODE_L = 0;
parameter /*[11:0]*/ OT_CODE_H = 0;
// add one parameter for bitgen
parameter OT_PD_ENABLE = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsGADC(
    output BG_READY,
    input REF_SEL,
    input [7:0] IN,
    input [2:0] CHSL,
    input CLKL,
    output [11:0] DOUTL,
    output ENDL,
    input PDL,
    input SAMPL)/*synthesis syn_black_box syn_noprune=1*/;
parameter ADC_IFS = "CM3"; // "CIB"
//parameter ADC_REFS = "VCCAUX"; // "2.5V"
endmodule

(* black_box, dont_touch="true" *)
module xsPWR (PUR)/*synthesis syn_black_box syn_noprune=1*/;
  parameter RST_PULSE = 1;
  input PUR;
endmodule

(* black_box, dont_touch="true" *)
module xsVCC ( Z )/*synthesis syn_black_box syn_noprune=1*/;
    output Z ;
endmodule

(* black_box, dont_touch="true" *)
module xsGND ( Z )/*synthesis syn_black_box syn_noprune=1*/;
    output Z ;
endmodule

(* black_box, dont_touch="true" *)
module xsGSRS (GSR, CLK)/*synthesis syn_black_box syn_noprune=1*/;
   input GSR, CLK;
endmodule

(* black_box, dont_touch="true" *)
module xsJTAG (
   input    TCK, TMS, TDI, JTDO1, JTDO2,
   output   TDO, JTCK, JTDI, JSHIFT, JUPDATE, JRSTN,
            JCE1, JCE2, JRTI1, JRTI2 )/*synthesis syn_black_box syn_noprune=1*/;
   parameter  ER1 = "ENABLED";
   parameter  ER2 = "ENABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsSTART (
   input    STARTCLK )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsSEDFC (
   input    SEDENABLE, SEDSTART, SEDFRCERR, SEDEXCLK, AUTOREBOOT,
   output   SEDERR, SEDDONE, SEDINPROG, SEDCLKOUT , AUTODONE)/*synthesis syn_black_box syn_noprune=1*/;
   parameter SED_CLK_DIV = 0; // 0-63
   parameter CHECKALWAYS = "NONE"; // "ALWAYS", "ONCE"
   parameter PARTIAL = "DISABLED";
   parameter AUTOFIX = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsSEDFD (
    input ECCERR_INJECT_I, ECCERR_INJECT_SHF, AUTOREBOOT,
    output ECCERR_INJECT_O,
   input    SEDENABLE, SEDSTART, SEDFRCERR, SEDEXCLK,
   output   SEDERR, SEDDONE, SEDINPROG, SEDCLKOUT , AUTODONE)/*synthesis syn_black_box syn_noprune=1*/;
   parameter SED_CLK_DIV = 0; // 0-63
   parameter CHECKALWAYS = "NONE"; // "ALWAYS", "ONCE"
   parameter AUTOFIX = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsSEDBM (
   input    SEDSTDBY, SEDENABLE, SEDSTART, SEDFRCERR,
   output   SEDERR, SEDDONE, SEDINPROG, SEDCLKOUT )/*synthesis syn_black_box syn_noprune=1*/;
   parameter SED_CLK_FREQ = "3.5";
   parameter CHECKALWAYS = "DISABLED";
   parameter PARTIAL = "DISABLED";
   parameter DEV_DENSITY = "1200L";
endmodule

(* black_box, dont_touch="true" *)
module xsSEDOHM (
   output   SEDERR, SEDDONE, SEDINPROG, SEDCLKOUT )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsPOWCTR (
   input    CLK, USERTIMEOUT, USERSTDBY, CLRFLAG, CFGWAKE, CFGSTDBY,
   output   STDBY, STOP, SFLAG )/*synthesis syn_black_box syn_noprune=1*/;
   parameter STDBYOPT = "USER_CFG";
   parameter TIMEOUT = "BYPASS";
   parameter WAKEUP = "USER";
   parameter POROFF = "FALSE";
   parameter BGOFF = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsBOOT (
   output [15:0] LASTBOOTADDR,
   input    BOOTCLK, BOOTDIN, input [15:0] REBOOTADDR)/*synthesis syn_black_box syn_noprune=1*/;
   parameter SOURCE_SEL = "DEFAULT"; // "FUSE" "CIB" "DEFAULT"
   parameter MSPI_ADDR = 0; // 8 bit for 74e, 16 bit for later
endmodule

(* black_box, dont_touch="true" *)
module xsDBCINRD (
   input    INRDENI )/*synthesis syn_black_box syn_noprune=1*/;
   parameter BANKID = 0;
   parameter PULLMODE = "DEFAULT"; // "VCCIO"
endmodule

(* black_box, dont_touch="true" *)
module xsDBCLVDS (
   input    LVDSENI )/*synthesis syn_black_box syn_noprune=1*/;
   parameter ISET = 0; // -4 ---- 3
   parameter BANKID = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsBCTMDSO (
   input    TMDSENI )/*synthesis syn_black_box syn_noprune=1*/;
   parameter BANKID = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsBCODT (
   input    CLK, CAL_LSRN, CAL_EN, LOADN, SEL_CTRL,
   input [5:0] CTRL_INN, CTRL_INP,
   output CAL_LOCK, CNOUT, CPOUT, NOUT, POUT,
   output [5:0] NCTRL, PCTRL)/*synthesis syn_black_box syn_noprune=1*/;
   parameter BANKID = 0;
   parameter CALINR = "ENABLED"; // "DISABLED"
   parameter CTRL_SRC = "CIB"; // "MASTER" "UP" "DOWN"
endmodule

(* black_box, dont_touch="true" *)
module xsIRDB (
   input    D, E,
   output   Q )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsOBUFLVDS (
   input    D, E,
   output   Q )/*synthesis syn_black_box syn_noprune=1*/;
   parameter BANKID = 0;
endmodule

(* black_box, dont_touch="true" *)
module xsPOWG (
   input    D, E,
   output   Q )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsDMP(
    input DMPCLK, DMPRST, DMPEN, DMPWE,
    input [14:0] DMPADR,
    input [7:0] DMPDIN,
    output [7:0] DMPDOUT,
    output DMPACK)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsCEM (
   input  WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI,
          WBADRI7, WBADRI6, WBADRI5, WBADRI4, WBADRI3, WBADRI2, WBADRI1, WBADRI0,
          WBDATI7, WBDATI6, WBDATI5, WBDATI4, WBDATI3, WBDATI2, WBDATI1, WBDATI0,
          PLL0DATI7, PLL0DATI6, PLL0DATI5, PLL0DATI4, PLL0DATI3, PLL0DATI2, PLL0DATI1, PLL0DATI0, PLL0ACKI,
          PLL1DATI7, PLL1DATI6, PLL1DATI5, PLL1DATI4, PLL1DATI3, PLL1DATI2, PLL1DATI1, PLL1DATI0, PLL1ACKI,
          I2C1SCLI, I2C1SDAI, I2C2SCLI, I2C2SDAI,
          SPISCKI, SPIMISOI, SPIMOSII, SPISCSN,
          TCCLKI, TCRSTN, TCIC, UFMSN,
   output WBDATO7, WBDATO6, WBDATO5, WBDATO4, WBDATO3, WBDATO2, WBDATO1, WBDATO0, WBACKO,
          PLLCLKO, PLLRSTO, PLL0STBO, PLL1STBO, PLLWEO,
          PLLADRO4, PLLADRO3, PLLADRO2, PLLADRO1, PLLADRO0,
          PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0,
          I2C1SCLO, I2C1SCLOEN, I2C1SDAO, I2C1SDAOEN, I2C2SCLO, I2C2SCLOEN, I2C2SDAO, I2C2SDAOEN, I2C1IRQO, I2C2IRQO,
          SPISCKO, SPISCKEN, SPIMISOO, SPIMISOEN, SPIMOSIO, SPIMOSIEN,
          SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, SPIIRQO,
          TCINT, TCOC, WBCUFMIRQ, CFGWAKE, CFGSTDBY )/*synthesis syn_black_box syn_noprune=1*/;
   parameter EFB_I2C1= "DISABLED";
   parameter EFB_I2C2= "DISABLED";
   parameter EFB_SPI = "DISABLED";
   parameter EFB_TC = "DISABLED";
   parameter EFB_TC_PORTMODE = "NO_WB";
   parameter EFB_UFM = "DISABLED";
   parameter EFB_WB_CLK_FREQ = "50.0";
   parameter DEV_DENSITY = "1200L";
   parameter UFM_INIT_PAGES = 0;
   parameter UFM_INIT_START_PAGE = 0;
   parameter UFM_INIT_ALL_ZEROS = "ENABLED";
   parameter UFM_INIT_FILE_NAME = "NONE";
   parameter UFM_INIT_FILE_FORMAT = "HEX";
   parameter I2C1_ADDRESSING = "7BIT";
   parameter I2C2_ADDRESSING = "7BIT";
   parameter I2C1_SLAVE_ADDR = "0b1000001";
   parameter I2C2_SLAVE_ADDR = "0b1000010";
   parameter I2C1_BUS_PERF = "100kHz";
   parameter I2C2_BUS_PERF = "100kHz";
   parameter I2C1_CLK_DIVIDER = 1;
   parameter I2C2_CLK_DIVIDER = 1;
   parameter I2C1_GEN_CALL = "DISABLED";
   parameter I2C2_GEN_CALL = "DISABLED";
   parameter I2C1_WAKEUP = "DISABLED";
   parameter I2C2_WAKEUP = "DISABLED";
   parameter SPI_MODE = "SLAVE";
   parameter SPI_CLK_DIVIDER = 1;
   parameter SPI_LSB_FIRST = "DISABLED";
   parameter SPI_CLK_INV = "DISABLED";
   parameter SPI_PHASE_ADJ = "DISABLED";
   parameter SPI_SLAVE_HANDSHAKE = "DISABLED";
   parameter SPI_INTR_TXRDY = "DISABLED";
   parameter SPI_INTR_RXRDY = "DISABLED";
   parameter SPI_INTR_TXOVR = "DISABLED";
   parameter SPI_INTR_RXOVR = "DISABLED";
   parameter SPI_WAKEUP = "DISABLED";
   parameter TC_MODE = "CTCM";
   parameter TC_SCLK_SEL = "PCLOCK";
   parameter TC_CCLK_SEL = 1;
   parameter GSR = "ENABLED";
   parameter TC_TOP_SET = 65535;
   parameter TC_OCR_SET = 32767;
   parameter TC_OC_MODE = "TOGGLE";
   parameter TC_RESETN = "ENABLED";
   parameter TC_TOP_SEL = "ON";
   parameter TC_OV_INT = "OFF";
   parameter TC_OCR_INT = "OFF";
   parameter TC_ICR_INT = "OFF";
   parameter TC_OVERFLOW = "ENABLED";
   parameter TC_ICAPTURE = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsEFB (
   input  WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI,
          WBADRI7, WBADRI6, WBADRI5, WBADRI4, WBADRI3, WBADRI2, WBADRI1, WBADRI0,
          WBDATI7, WBDATI6, WBDATI5, WBDATI4, WBDATI3, WBDATI2, WBDATI1, WBDATI0,
          PLL0DATI7, PLL0DATI6, PLL0DATI5, PLL0DATI4, PLL0DATI3, PLL0DATI2, PLL0DATI1, PLL0DATI0, PLL0ACKI,
          PLL1DATI7, PLL1DATI6, PLL1DATI5, PLL1DATI4, PLL1DATI3, PLL1DATI2, PLL1DATI1, PLL1DATI0, PLL1ACKI,
          I2C1SCLI, I2C1SDAI, I2C2SCLI, I2C2SDAI,
          SPISCKI, SPIMISOI, SPIMOSII, SPISCSN,
          TCCLKI, TCRSTN, TCIC, UFMSN,
   output WBDATO7, WBDATO6, WBDATO5, WBDATO4, WBDATO3, WBDATO2, WBDATO1, WBDATO0, WBACKO,
          PLLCLKO, PLLRSTO, PLL0STBO, PLL1STBO, PLLWEO,
          PLLADRO4, PLLADRO3, PLLADRO2, PLLADRO1, PLLADRO0,
          PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0,
          I2C1SCLO, I2C1SCLOEN, I2C1SDAO, I2C1SDAOEN, I2C2SCLO, I2C2SCLOEN, I2C2SDAO, I2C2SDAOEN, I2C1IRQO, I2C2IRQO,
          SPISCKO, SPISCKEN, SPIMISOO, SPIMISOEN, SPIMOSIO, SPIMOSIEN,
          SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, SPIIRQO,
          TCINT, TCOC, WBCUFMIRQ, CFGWAKE, CFGSTDBY )/*synthesis syn_black_box syn_noprune=1*/;
   parameter EFB_I2C1= "DISABLED";
   parameter EFB_I2C2= "DISABLED";
   parameter EFB_SPI = "DISABLED";
   parameter EFB_TC = "DISABLED";
   parameter EFB_TC_PORTMODE = "NO_WB";
   parameter EFB_UFM = "DISABLED";
   parameter EFB_WB_CLK_FREQ = "50.0";
   parameter DEV_DENSITY = "1200L";
   parameter UFM_INIT_PAGES = 0;
   parameter UFM_INIT_START_PAGE = 0;
   parameter UFM_INIT_ALL_ZEROS = "ENABLED";
   parameter UFM_INIT_FILE_NAME = "NONE";
   parameter UFM_INIT_FILE_FORMAT = "HEX";
   parameter I2C1_ADDRESSING = "7BIT";
   parameter I2C2_ADDRESSING = "7BIT";
   parameter I2C1_SLAVE_ADDR = "0b1000001";
   parameter I2C2_SLAVE_ADDR = "0b1000010";
   parameter I2C1_BUS_PERF = "100kHz";
   parameter I2C2_BUS_PERF = "100kHz";
   parameter I2C1_CLK_DIVIDER = 1;
   parameter I2C2_CLK_DIVIDER = 1;
   parameter I2C1_GEN_CALL = "DISABLED";
   parameter I2C2_GEN_CALL = "DISABLED";
   parameter I2C1_WAKEUP = "DISABLED";
   parameter I2C2_WAKEUP = "DISABLED";
   parameter SPI_MODE = "SLAVE";
   parameter SPI_CLK_DIVIDER = 1;
   parameter SPI_LSB_FIRST = "DISABLED";
   parameter SPI_CLK_INV = "DISABLED";
   parameter SPI_PHASE_ADJ = "DISABLED";
   parameter SPI_SLAVE_HANDSHAKE = "DISABLED";
   parameter SPI_INTR_TXRDY = "DISABLED";
   parameter SPI_INTR_RXRDY = "DISABLED";
   parameter SPI_INTR_TXOVR = "DISABLED";
   parameter SPI_INTR_RXOVR = "DISABLED";
   parameter SPI_WAKEUP = "DISABLED";
   parameter TC_MODE = "CTCM";
   parameter TC_SCLK_SEL = "PCLOCK";
   parameter TC_CCLK_SEL = 1;
   parameter GSR = "ENABLED";
   parameter TC_TOP_SET = 65535;
   parameter TC_OCR_SET = 32767;
   parameter TC_OC_MODE = "TOGGLE";
   parameter TC_RESETN = "ENABLED";
   parameter TC_TOP_SEL = "ON";
   parameter TC_OV_INT = "OFF";
   parameter TC_OCR_INT = "OFF";
   parameter TC_ICR_INT = "OFF";
   parameter TC_OVERFLOW = "ENABLED";
   parameter TC_ICAPTURE = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsGSR (GSR)/*synthesis syn_black_box syn_noprune=1*/;
input GSR ;
endmodule

(* black_box, dont_touch="true" *)
module xsGTI (
   input TSALL )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsFBCLKPLL (
   input    A,
   output   Z )/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsWAKEUP (WAKEUP)/*synthesis syn_black_box syn_noprune=1*/;
input WAKEUP ;
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL(
    input [1:0] BURSTDET,
    output CLOCKING_GOOD,
    input [1:0] DATAVALID_O,
    output [7:0] DDR3_DM_IN,
    output [1:0] DDR3_DQSOUT_IN,
    input [63:0] DDR3_READ_DATA_OUT,
    output [63:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CKE_DA,
    output DDR_CKE_DB,
    output DDR_CS_DA,
    output DDR_CS_DA1,
    output DDR_CS_DB1,
    output DDR_ODT_DA,
    output DDR_ODT_DB,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_WE_DA,
    output DDR_WE_DB,
    input DDRDLL_LOCK,
    input [15:0] DDRIN,
    output DLL_FREEZE,
    output DQ_TRI,
    output DQSBUFD_PAUSE,
    input [15:0] EDGE_MINUS,
    output [1:0] EDGE_MON_ACK,
    input [15:0] EDGE_PLUS,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
//-Daniel-//082120//    input GLOBAL_RST_N,
    input MEM_RST_N,
    input PLL_LOCK,
    output RD_DIRECTION_0,
    output RD_DIRECTION_1,
    output RD_LOADN,
    output RD_MOVE_0,
    output RD_MOVE_1,
    input [1:0] RDCFLAG,
    output RL_ERR,
    output [3:0] RL_MON_DIS,
    input RST_N,
    output [7:0] RT_DQS_READ,
    output RT_ERR,
    output [5:0] RT_RDCLKSEL,
    input SCLK,
//    output SCLK_OUT,
    output UDDCNTLN,
    input [29:0] USR_ADDR_0,
    input [29:0] USR_ADDR_1,
    input USR_CLK_0,
    input USR_CLK_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    output USR_CMD_EMPTY_0,
    output USR_CMD_EMPTY_1,
    output USR_CMD_FULL_0,
    output USR_CMD_FULL_1,
    input [2:0] USR_CMD_ID_0,
    input [2:0] USR_CMD_ID_1,
    output USR_CMD_OVERFLOW_0,
    output USR_CMD_OVERFLOW_1,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output USR_CMD_UNDERFLOW_0,
    output USR_CMD_UNDERFLOW_1,
    input USR_CMD_WE_0,
    input USR_CMD_WE_1,
    output USR_DR_EMPTY_0,
    output USR_DR_EMPTY_1,
    output USR_DR_FULL_0,
    output USR_DR_FULL_1,
    output USR_DR_OVERFLOW_0,
    output USR_DR_OVERFLOW_1,
    input USR_DR_RE_0,
    input USR_DR_RE_1,
    output [5:0] USR_DR_SPACE_0,
    output [5:0] USR_DR_SPACE_1,
    output USR_DR_UNDERFLOW_0,
    output USR_DR_UNDERFLOW_1,
    output USR_DW_EMPTY_0,
    output USR_DW_EMPTY_1,
    output USR_DW_ERR_0,
    output USR_DW_ERR_1,
    output USR_DW_FULL_0,
    output USR_DW_FULL_1,
    output USR_DW_OVERFLOW_0,
    output USR_DW_OVERFLOW_1,
    output [5:0] USR_DW_SPACE_0,
    output [5:0] USR_DW_SPACE_1,
    output USR_DW_UNDERFLOW_0,
    output USR_DW_UNDERFLOW_1,
    input USR_DW_WE_0,
    input USR_DW_WE_1,
    input USR_OFLY_BURST_LEN_0,
    input USR_OFLY_BURST_LEN_1,
    output [2:0] USR_READ_CMD_ID_0,
    output [2:0] USR_READ_CMD_ID_1,
    output [63:0] USR_READ_DATA_0,
    output [63:0] USR_READ_DATA_1,
    output USR_READ_LAST_0,
    output USR_READ_LAST_1,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [63:0] USR_WRITE_DATA_0,
    input [63:0] USR_WRITE_DATA_1,
    input USR_WRITE_LAST_0,
    input USR_WRITE_LAST_1,
    input [7:0] USR_WRITE_MASK_0,
    input [7:0] USR_WRITE_MASK_1,
    output WL_ACT_CNTL_R,
    output [15:0] WL_DYNDELAY,
    output WL_ERR,
    output WR_DQS_ONEGA_IN,
    output WR_DQS_TRI_IN)/*synthesis syn_black_box syn_noprune=1*/;
parameter ADDR_SEQ = "FALSE";
parameter DDR_MODE = "FALSE";
parameter DLL_FREEZE_EN = "FALSE";
parameter EXT_AUTO_REF_EN = "FALSE";
parameter HALF_DQ = "FALSE";
parameter IDLE_AUTO_REF_EN = "FALSE";
parameter RL_EN = "FALSE";
parameter RT_EN = "FALSE";
parameter WL_EN = "FALSE";
parameter [7:0] WL_DELAY_1 = 8'h0;
parameter [7:0] WL_DELAY_0 = 8'h0;
parameter [1:0] SPD_BIN = 2'h0;
parameter [4:0] ROW_WIDTH = 5'h0;
parameter [3:0] PARAM_RL_MON_DIS = 4'h0;
parameter [6:0] PARAM_TZQS = 7'h0;
parameter [8:0] PARAM_TZQOPER = 9'h0;
parameter [10:0] PARAM_TZQINIT = 11'h0;
parameter [7:0] PARAM_TXPR = 8'h0;
parameter [3:0] PARAM_TXPDLL = 4'h0;
parameter [2:0] PARAM_TWTR = 3'h0;
parameter [3:0] PARAM_TWR = 4'h0;
parameter [2:0] PARAM_TRTP = 3'h0;
parameter [4:0] PARAM_TRRD = 5'h0;
parameter [3:0] PARAM_TRP = 4'h0;
parameter [6:0] PARAM_TRFC = 7'h0;
parameter [16:0] PARAM_TREFI = 17'h0;
parameter [3:0] PARAM_TRCD = 4'h0;
parameter [4:0] PARAM_TRC = 5'h0;
parameter [4:0] PARAM_TRAS = 5'h0;
parameter [2:0] PARAM_TPD = 3'h0;
parameter [4:0] PARAM_TMRD = 5'h0;
parameter [4:0] PARAM_TMOD = 5'h0;
parameter [4:0] PARAM_TFAW = 5'h0;
parameter [2:0] PARAM_TCKESR = 3'h0;
parameter [2:0] PARAM_TCKE = 3'h0;
parameter [3:0] COL_WIDTH = 4'h0;
parameter [1:0] BANK_WIDTH = 2'h0;
parameter [3:0] AR_BURST_EN = 4'h0;
parameter [15:0] ADDR_INIT_3 = 16'h0;
parameter [15:0] ADDR_INIT_2 = 16'h0;
parameter [15:0] ADDR_INIT_1 = 16'h0;
parameter [15:0] ADDR_INIT_0 = 16'h0;
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL64(
    input [1:0] BURSTDET,
    output CLOCKING_GOOD,
    input [1:0] DATAVALID_O,
    output [7:0] DDR3_DM_IN,
    output [1:0] DDR3_DQSOUT_DB0,
    output [1:0] DDR3_DQSOUT_DB1,
    input [63:0] DDR3_READ_DATA_OUT,
    output [63:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CKE_DA,
    output DDR_CKE_DB,
    output DDR_CS_DA,
    output DDR_CS_DA1,
    output DDR_CS_DB1,
    output DDR_ODT_DA,
    output DDR_ODT_DB,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_WE_DA,
    output DDR_WE_DB,
    input DDRDLL_LOCK,
    input [15:0] DDRIN,
    output DLL_FREEZE,
    output DQ_TRI,
    output DQSBUFD_PAUSE,
    output DQSTRI_N,
    output DQSTRI_P,
    input [15:0] EDGE_MINUS,
    output [1:0] EDGE_MON_ACK,
    input [15:0] EDGE_PLUS,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input PLL_LOCK,
    output [1:0] RD_DIRECTION,
    output RD_LOADN,
    output [1:0] RD_MOVE,
    input [1:0] RDCFLAG,
    input REFCLK,
    output RESET_CLK,
    output RL_ERR,
    output [3:0] RL_MON_DIS,
    input RST_N,
    output [7:0] RT_DQS_READ,
    output RT_ERR,
    output [5:0] RT_RDCLKSEL,
    input SCLK,
//    output SCLK_OUT,
    output UDDCNTLN,
    input [29:0] USR_ADDR_0,
    input [29:0] USR_ADDR_1,
    input [1:0] USR_CLK,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [2:0] USR_CMD_ID_0,
    input [2:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [5:0] USR_DR_SPACE_0,
    output [5:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [5:0] USR_DW_SPACE_0,
    output [5:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    input [1:0] USR_OFLY_BURST_LEN,
    output [2:0] USR_READ_CMD_ID_0,
    output [2:0] USR_READ_CMD_ID_1,
    output [63:0] USR_READ_DATA_0,
    output [63:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [63:0] USR_WRITE_DATA_0,
    input [63:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [7:0] USR_WRITE_MASK_0,
    input [7:0] USR_WRITE_MASK_1,
    output [15:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter [15:0] ADDR_INIT_0 = 16'h0;
    parameter [15:0] ADDR_INIT_1 = 16'h0;
    parameter [15:0] ADDR_INIT_2 = 16'h0;
    parameter [15:0] ADDR_INIT_3 = 16'h0;
    parameter ADDR_MIRROR = "FALSE";
    parameter ADDR_SEQ = "FALSE";
    parameter [3:0] AR_BURST_EN = 4'h0;
    parameter [1:0] BANK_WIDTH = 2'h0;
    parameter [3:0] COL_WIDTH = 4'h0;
    parameter DDR_MODE = "FALSE";
    parameter DLL_FREEZE_EN = "FALSE";
    parameter [2:0] DQS_WIDTH = 3'h0;
    parameter DUAL_RANK = "FALSE";
    parameter EXT_AUTO_REF_EN = "FALSE";
    parameter IDLE_AUTO_REF_EN = "FALSE";
    parameter MPR_CALIB = "FALSE";
    parameter [2:0] PARAM_TCKE = 3'h0;
    parameter [2:0] PARAM_TCKESR = 3'h0;
    parameter [4:0] PARAM_TFAW = 5'h0;
    parameter [4:0] PARAM_TMOD = 5'h0;
    parameter [4:0] PARAM_TMRD = 5'h0;
    parameter [2:0] PARAM_TPD = 3'h0;
    parameter [4:0] PARAM_TRAS = 5'h0;
    parameter [4:0] PARAM_TRC = 5'h0;
    parameter [3:0] PARAM_TRCD = 4'h0;
    parameter [16:0] PARAM_TREFI = 17'h0;
    parameter [6:0] PARAM_TRFC = 7'h0;
    parameter [3:0] PARAM_TRP = 4'h0;
    parameter [4:0] PARAM_TRRD = 5'h0;
    parameter [2:0] PARAM_TRTP = 3'h0;
    parameter [3:0] PARAM_TWR = 4'h0;
    parameter [2:0] PARAM_TWTR = 3'h0;
    parameter [3:0] PARAM_TXPDLL = 4'h0;
    parameter [7:0] PARAM_TXPR = 8'h0;
    parameter [10:0] PARAM_TZQINIT = 11'h0;
    parameter [8:0] PARAM_TZQOPER = 9'h0;
    parameter [6:0] PARAM_TZQS = 7'h0;
    parameter RDIMM = "FALSE";
    parameter RL_EN = "FALSE";
    parameter [3:0] PARAM_RL_MON_DIS = 4'h0;
    parameter [4:0] ROW_WIDTH = 5'h0;
    parameter RT_EN = "FALSE";
    parameter [7:0] S_RD_0 = 8'h0;
    parameter [7:0] S_RD_1 = 8'h0;
    parameter [7:0] S_WR_0 = 8'h0;
    parameter [7:0] S_WR_1 = 8'h0;
    parameter [1:0] SIGN_RD = 2'h0;
    parameter [1:0] SIGN_WR = 2'h0;
    parameter [1:0] SPD_BIN = 2'h0;
    parameter [15:0] WL_DELAY = 16'h0;
    parameter WL_EN = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL128(
    input [3:0] BURSTDET,
    output CLOCKING_GOOD,
    input [3:0] DATAVALID_O,
    output [15:0] DDR3_DM_IN,
    output [3:0] DDR3_DQSOUT_DB0,
    output [3:0] DDR3_DQSOUT_DB1,
    input [127:0] DDR3_READ_DATA_OUT,
    output [127:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output [1:0] DDR_CKE_DA,
    output [1:0] DDR_CKE_DB,
    output [1:0] DDR_CS_DA,
    output [1:0] DDR_CS_DA1,
    output [1:0] DDR_CS_DB1,
//    output [7:0] DDR_MIB_WDATA,
    output [1:0] DDR_ODT_DA,
    output [1:0] DDR_ODT_DB,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_WE_DA,
    output DDR_WE_DB,
    input DDRDLL_LOCK,
    input [31:0] DDRIN,
    output DLL_FREEZE,
    output DQ_TRI,
    output DQSBUFD_PAUSE,
    output DQSTRI_N,
    output DQSTRI_P,
    input [31:0] EDGE_MINUS,
    output [3:0] EDGE_MON_ACK,
    input [31:0] EDGE_PLUS,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
//    input GLOBAL_RST_N,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input PLL_LOCK,
    output [3:0] RD_DIRECTION,
    output RD_LOADN,
    output [3:0] RD_MOVE,
    input [3:0] RDCFLAG,
    input REFCLK,
    output RESET_CLK,
    output RL_ERR,
    output [7:0] RL_MON_DIS,
    input RST_N,
    output [15:0] RT_DQS_READ,
    output RT_ERR,
    output [11:0] RT_RDCLKSEL,
    input SCLK,
//    output SCLK_OUT,
    output UDDCNTLN,
    input [30:0] USR_ADDR_0,
    input [30:0] USR_ADDR_1,
    input [1:0] USR_CLK,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [2:0] USR_CMD_ID_0,
    input [2:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [5:0] USR_DR_SPACE_0,
    output [5:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [5:0] USR_DW_SPACE_0,
    output [5:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [7:0] USR_ECC_DEC_ERR_0,
    output [7:0] USR_ECC_DEC_ERR_1,
    input [7:0] USR_ECC_INSERR,
    input [1:0] USR_OFLY_BURST_LEN,
    output [2:0] USR_READ_CMD_ID_0,
    output [2:0] USR_READ_CMD_ID_1,
    output [127:0] USR_READ_DATA_0,
    output [127:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [127:0] USR_WRITE_DATA_0,
    input [127:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [15:0] USR_WRITE_MASK_0,
    input [15:0] USR_WRITE_MASK_1,
    output WB_ACK_O_CIB,
//    output WB_ACK_O_EFB,
//    input WB_ACK_PRE_EFB,
    input [4:0] WB_ADR_I_CIB,
//    input [4:0] WB_ADR_I_EFB,
    input WB_CLK_I_CIB,
//    input WB_CLK_I_EFB,
    input [7:0] WB_DAT_I_CIB,
//    input [7:0] WB_DAT_I_EFB,
    output [7:0] WB_DAT_O_CIB,
//    output [7:0] WB_DAT_O_EFB,
//    input [7:0] WB_DAT_PRE_EFB,
    input WB_RST_I_CIB,
//    input WB_RST_I_EFB,
    input WB_STB_I_CIB,
//    input WB_STB_I_EFB,
    input WB_WE_I_CIB,
//    input WB_WE_I_EFB,
    output [31:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter ADDR_MIRROR = "FALSE";
    parameter ADDR_SEQ = "FALSE";
    parameter DDR_MODE = "FALSE";
    parameter DLL_FREEZE_EN = "FALSE";
    parameter DUAL_RANK = "FALSE";
    parameter ECC_EN = "FALSE";
    parameter EXT_AUTO_REF_EN = "FALSE";
    parameter IDLE_AUTO_REF_EN = "FALSE";
    parameter MPR_CALIB = "FALSE";
    parameter PATH_SEL_CIB = "FALSE";
    parameter RDIMM = "FALSE";
    parameter RL_EN = "FALSE";
    parameter RT_EN = "FALSE";
    parameter WL_EN = "FALSE";
    parameter [10:0] PARAM_TZQINIT = 11'h0;
    parameter [15:0] ADDR_INIT_0 = 16'h0;
    parameter [15:0] ADDR_INIT_1 = 16'h0;
    parameter [15:0] ADDR_INIT_2 = 16'h0;
    parameter [15:0] ADDR_INIT_3 = 16'h0;
    parameter [16:0] PARAM_TREFI = 17'h0;
    parameter [1:0] BANK_WIDTH = 2'h0;
    parameter [1:0] SPD_BIN = 2'h0;
    parameter [2:0] DQS_WIDTH = 3'h0;
    parameter [2:0] PARAM_TCKE = 3'h0;
    parameter [2:0] PARAM_TCKESR = 3'h0;
    parameter [2:0] PARAM_TPD = 3'h0;
    parameter [2:0] PARAM_TRTP = 3'h0;
    parameter [2:0] PARAM_TWTR = 3'h0;
    parameter [31:0] WL_DELAY = 32'h0;
    parameter [3:0] AR_BURST_EN = 4'h0;
    parameter [3:0] COL_WIDTH = 4'h0;
    parameter [3:0] PARAM_TRCD = 4'h0;
    parameter [3:0] PARAM_TRP = 4'h0;
    parameter [3:0] PARAM_TWR = 4'h0;
    parameter [3:0] PARAM_TXPDLL = 4'h0;
    parameter [3:0] SIGN_RD = 4'h0;
    parameter [3:0] SIGN_WR = 4'h0;
    parameter [4:0] PARAM_TFAW = 5'h0;
    parameter [4:0] PARAM_TMOD = 5'h0;
    parameter [4:0] PARAM_TMRD = 5'h0;
    parameter [4:0] PARAM_TRAS = 5'h0;
    parameter [4:0] PARAM_TRC = 5'h0;
    parameter [4:0] PARAM_TRRD = 5'h0;
    parameter [4:0] ROW_WIDTH = 5'h0;
    parameter [6:0] DELAY_0 = 7'h0;
    parameter [6:0] DELAY_1 = 7'h0;
    parameter [6:0] DELAY_10 = 7'h0;
    parameter [6:0] DELAY_11 = 7'h0;
    parameter [6:0] DELAY_12 = 7'h0;
    parameter [6:0] DELAY_13 = 7'h0;
    parameter [6:0] DELAY_14 = 7'h0;
    parameter [6:0] DELAY_15 = 7'h0;
    parameter [6:0] DELAY_16 = 7'h0;
    parameter [6:0] DELAY_2 = 7'h0;
    parameter [6:0] DELAY_3 = 7'h0;
    parameter [6:0] DELAY_4 = 7'h0;
    parameter [6:0] DELAY_5 = 7'h0;
    parameter [6:0] DELAY_6 = 7'h0;
    parameter [6:0] DELAY_7 = 7'h0;
    parameter [6:0] DELAY_8 = 7'h0;
    parameter [6:0] DELAY_9 = 7'h0;
    parameter [6:0] PARAM_TRFC = 7'h0;
    parameter [6:0] PARAM_TZQS = 7'h0;
    parameter [7:0] PARAM_TXPR = 8'h0;
    parameter [7:0] PARAM_RL_MON_DIS = 8'h0;
    parameter [7:0] S_RD_0 = 8'h0;
    parameter [7:0] S_RD_1 = 8'h0;
    parameter [7:0] S_RD_2 = 8'h0;
    parameter [7:0] S_RD_3 = 8'h0;
    parameter [7:0] S_WR_0 = 8'h0;
    parameter [7:0] S_WR_1 = 8'h0;
    parameter [7:0] S_WR_2 = 8'h0;
    parameter [7:0] S_WR_3 = 8'h0;
    parameter [8:0] PARAM_TZQOPER = 9'h0;
endmodule

(* black_box, dont_touch="true" *)
module xsIBUFDS_DYN (
    input CLKCM_CFG,
    input CLKRCV_TRST,       
    input [1:0] CLKSWING_CFG,
	input [1:0] REFCLK_CTRL,
	input DIV2RST_B,
	input CLKTESTSIG,

    output O_INT,
    output ODIV2_EXT,

    input CEB,
    input I,
    input IB
)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsIBUFDS (
    O_INT,
    ODIV2_EXT,

    CEB,
    I,
    IB
)/*synthesis syn_black_box syn_noprune=1*/;
    parameter CLKCM_CFG = "TRUE";
    parameter CLKRCV_TRST = "TRUE";       
    parameter [1:0] CLKSWING_CFG = 3; //always set to 2'b11
	parameter [1:0] REFCLK_CTRL = 1;  //00: output reference clock; 01: output reference clock divided-by-2; 10: ground; 11: reserved.
	parameter DIV2RST_B = 1; //0: div2 block reset, output=0, 1: div2 block normal working.
	parameter CLKTESTSIG = 1; //alwasy set to 1'b1
    output O_INT;
    output ODIV2_EXT;
    input CEB;
    input I;
    input IB;
endmodule

(* black_box, dont_touch="true" *)
module xsSERDES_CH (
    // from com
    input QPLLCLK,
    input QPLLREFCLK,
    // to clk
    output TXOUTCLK_INT,
    output RXRECCLK_INT,
    // to IOPAD
    output TXDN,
    output TXDP,
    input RXDN,
    input RXDP,
    // CIB
    input AFECFOKEN,
    input AFECFOKNTRL,
    input [4:0] AGCCTRL,
    input ALT_SIGVALID_CLK,
    input CDRFRRESET,
    input CDRHOLD,
    output CDRLOCK_B,
    input CDROVREN,
    input CDRPHRESET,
    input CDRRESET,
    input CFGRESET,
    output CFOKDONE_B,
    output CFOKFORCEDONE_B,
    output CFOKFSTARTED_B,
    input CFOKRESET,
    output CFOKSTART_B,
    output [3:0] CH_DEBUG_TSTO,
    input CKPINRSRVD0,
    input CKPINRSRVD1,
    output COMFINISH_B,
    output COMINITDET_B,
    output COMSASDET_B,
    output COMWAKEDET_B,
    input COREREFCLK,
    output CPLFBLOSS_B,
    output CPLFREQLOCK_B,
    input CPLLDMONCLK,
    input CPLLKDETEN,
    input CPLPWRDN,
    output CPLREFLOSS_B,
    input [2:0] CPLREFSELDYN,
    input CPLRESET,
    input [8:0] DADDR,
    input DCLK,
    input DEN,
    input [3:0] DFECFOKCFNUM,
    input [3:0] DFECFOKFCFN,
    input DFECFOKFEN,
    input DFECFOKFPULSE,
    input DFECFOKHOLD,
    input DFECFOKOVREN,
    input DFECM1DETEN,
    output [6:0] DFEDOUT_B,
    input [1:0] DFEDOUTMODE,
    input DFEGCHOLD,
    input DFEGCOVREN,
    input DFEH2HOLD,
    input DFEH2OVREN,
    input DFEH3HOLD,
    input DFEH3OVREN,
    input DFEH4HOLD,
    input DFEH4OVREN,
    input DFEH5HOLD,
    input DFEH5OVREN,
    input DFEH6HOLD,
    input DFEH6OVREN,
    input DFEH7HOLD,
    input DFEH7OVREN,
    input DFEKLHOLD,
    input DFEKLOVREN,
    input DFERESET,
    output DFESTDONE_B,
    input [4:0] DFESTFDAC,
    input DFESTFEN,
    output DFESTFORCEDONE_B,
    input DFESTFPULSE,
    output DFESTFSTARTED_B,
    input [5:0] DFESTFTAPNUM,
    input DFESTHOLD,
    input DFESTOVREN,
    output DFESTSTART_B,
    input DFESTTAPCHKEN,
    input DFESTTAPSCNEN,
    input DFEUTHOLD,
    input DFEUTOVREN,
    input DFEVPHOLD,
    input DFEVPOVREN,
    input DFEVSEN,
    input DFEYEN,
    input [15:0] DI,
    input DMONCLK,
    input DMONFIFORESET,
    output [14:0] DMONOUT_B,
    output DRDY_B,
    output [15:0] DRPDO_B,
    input DWE,
    input ENPPM,
    output EYESCANDATAERROR_B,
    input EYESCANTRIGGER,
    input [1:0] GATERXELECIDLE,
    input GTRXRST,
    input GTTXRST,
    input ISCANRESET,
    input ISERRDETEN,
    input [2:0] LOOPBACK,
    input [13:0] LOOPENSEL,
    input LPMKHHOLD,
    input LPMKHOVREN,
    input LPMKLHOLD,
    input LPMKLOVREN,
    output MGTREFCLKFA_B,
    input OSHOLD,
    input OSOVREN,
    input [15:0] PCS_RSVD_IN,
    output [14:0] PCS_RSVD_OUT_B,
    output PHYSTATUS_B,
    input [15:0] PINRSRVD,
    input [4:0] PMASCANCLK,
    input PMASCANENB,
    input [6:0] PMASCANIN,
    input PMASCANMODEB,
    output [6:0] PMASCANOUT_B,
    input PMASCANRSTEN,
    input PRBSCNTRST,
    input [4:0] RCAL_INT,
    input RCODAPWDN,
    input RCODARESET,
    input RCOOVREN,
    input RDASOFTRESET,
    output RDASOFTRSTDONE_B,
    input RESETOVRD,
    input RING_OSC_CLK_INT,
    input RXBUFRST,
    output [2:0] RXBUFSTATUS_B,
    output RXBYTEISALIGNED_B,
    output RXBYTEREALIGN_B,
    output RXCHANBONDSEQ_B,
    output RXCHANREALIGN_B,
    output [7:0] RXCHARISCOMMA_B,
    output [7:0] RXCHARISK_B,
    input [4:0] RXCHBONDI,
    input [2:0] RXCHBONDLEVEL,
    input RXCHBONDMASTER,
    output [4:0] RXCHBONDO_B,
    input RXCHBONDSLAVE,
    output RXCHISALIGNED_B,
    output [1:0] RXCKCORCNT_B,
    input RXCOALGNEN,
    output [4:0] RXCOCKPSOUT_B,
    output [4:0] RXCOCKSELOUT_B,
    output RXCOMMADET_B,
    input RXCOMMADETUSE,
    output RXCOPHDONE_B,
    input RXCOSETPHS,
    input RXDAALGNEN,
    input RXDABYPASS,
    input RXDAOVREN,
    output [63:0] RXDATA_B,
    output [1:0] RXDATAVALID_B,
    input RXDATESTENB,
    input RXDBGPULSE,
    input RXDDIEN,
    input RXDEC8B10BUSE,
    output [7:0] RXDISPERR_B,
    output RXELECIDLE_B,
    input RXENCHANSYNC,
    input RXENMCOMMAALIGN,
    input RXENPCOMMAALIGN,
    input RXFSMRESET,
    input RXGEARBOXSLIP,
    output [5:0] RXHEADER_B,
    output [1:0] RXHEADERVALID_B,
    output RXLINKSYNCDONE_B,
    input RXLPMEN,
    input RXMSTRSETPHDONE,
    output [7:0] RXNOTINTABLE_B,
    input RXOOBRESET,
    input [2:0] RXOUTCKCTL,
    input RXPMARESET,
    output RXPMARESETDONE_B,
    input RXPOLARITY,
    output RXPRBSERR_B,
    input [2:0] RXPRBSPTN,
    input [1:0] RXPWRDN,
    input RXQPIEN,
    output RXQPISENN_B,
    output RXQPISENP_B,
    input [2:0] RXRATE,
    input RXRATEASYNCH,
    output RXRATEDONE_B,
    output RXRECCLK_B,
    output RXRECCLKPCS_B,
    input RXRESET,
    output RXRESETDONE_B,
    input [4:0] RXSIGVALDLY,
    input RXSLIDE,
    input RXSLVSYNCEN,
    output [1:0] RXSTARTOFSEQ_B,
    output [2:0] RXSTATUS_B,
    output RXSYNCEN2SLV_B,
    input RXSYNCFSMMASTER,
    input [1:0] RXSYSCKSEL,
    input [4:0] RXTERMPROG,
    input RXUSRCLK2,
    input RXUSRCLK,
    input RXUSRRDY,
    output RXVALID_B,
    input SCANCLK,
    input SCANENB,
    input [5:0] SCANIN,
    input SCANMODEB,
    output [5:0] SCANOUT_B,
    input [4:0] STEPSIZEPPM,
    input TCOCLKFSMFROUT,
    input TCODABYPASS,
    input TCODAOVREN,
    input TCODAPWDN,
    input TCODARESET,
    input TCOHOLDFROUT,
    output TCOINITDONE_B,
    input TCOINITSET,
    input TCOPIOVREN,
    input TCOUPDNFROUT,
    input TDASOFTRESET,
    output TDASOFTRSTDONE_B,
    input TSTCLK0,
    input TSTCLK1,
    input [19:0] TSTIN,
    input [4:0] TSTPWRDN,
    input TSTPWRDNOVRDB,
    output [1:0] TXBUFSTATUS_B,
    input [7:0] TXBYPASS8B10B,
    input [7:0] TXCHARDISPMODE,
    input [7:0] TXCHARDISPVAL,
    input [7:0] TXCHARISK,
    input TXCODAALGNEN,
    input TXCOMINIT,
    input TXCOMSAS,
    input TXCOMWAKE,
    input TXCOPIALGNEN,
    output TXCOPIPHDONE_B,
    input TXCOPISETPHS,
    input [63:0] TXDATA,
    input TXDATESTENB,
    input TXDEEMPH,
    input TXDETECTRX,
    input [3:0] TXDRVAMP,
    input TXDRVPWRDN,
    input TXELECIDLE,
    input TXEMPINVPO,
    input TXEMPINVPR,
    input [6:0] TXEMPMAIN,
    input [4:0] TXEMPPOS,
    input [4:0] TXEMPPRE,
    input TXENC8B10BUSE,
    output TXGEARBOXRDY_B,
    input [2:0] TXHEADER,
    input TXINHIBIT,
    output TXLINKSYNCDONE_B,
    input [2:0] TXMARGIN,
    input TXMSTRSETPHDONE,
    input [2:0] TXOUTCKCTL,
    output TXOUTCLK_B,
    output TXOUTCLKPCS_B,
    input TXPDOWNASYNCH,
    input TXPIPPMPWDN,
    input TXPMARESET,
    output TXPMARESETDONE_B,
    input TXPOLARITY,
    input TXPPMOVRDEN,
    input TXPPMSEL,
    input TXPRBSINERR,
    input [2:0] TXPRBSPTN,
    input [2:0] TXPREAMP,
    input [1:0] TXPWRDN,
    input TXQPIBIASEN,
    output TXQPISENN_B,
    output TXQPISENP_B,
    input TXQPISTRGPD,
    input TXQPIWEAKPU,
    input [2:0] TXRATE,
    input TXRATEASYNCH,
    output TXRATEDONE_B,
    input TXRESET,
    output TXRESETDONE_B,
    output [7:0] TXRUNDISP_B,
    input [6:0] TXSEQUENCE,
    input TXSERPWRDN,
    input TXSLVSYNCEN,
    input TXSTARTSEQ,
    input TXSWING,
    output TXSYNCEN2SLV_B,
    input TXSYNCFSMMASTER,
    input [1:0] TXSYSCKSEL,
    input TXUSRCLK2,
    input TXUSRCLK,
    input TXUSRRDY,
    input USRCODEERR,
	input GTNORTHREFCLK0, //mod by sdfu 2023-03-17 11:31:01
	input GTNORTHREFCLK1,
	input GTSOUTHREFCLK0,
	input GTSOUTHREFCLK1,
	input GTREFCLK0,
	input GTREFCLK1
	)/*synthesis syn_black_box syn_noprune=1*/;
    parameter A_AFECFOKEN = "FALSE";
    parameter A_AFECFOKNTRL = "FALSE";
    parameter [4:0] A_AGCCTRL = 5'h0;
    parameter A_CDRFRRESET = "FALSE";
    parameter A_CDRHOLD = "FALSE";
    parameter A_CDROVREN = "FALSE";
    parameter A_CDRPHRESET = "FALSE";
    parameter A_CDRRESET = "FALSE";
    parameter A_CFGRESET = "FALSE";
    parameter A_CPLLKDETEN = "FALSE";
    parameter A_CPLPWRDN = "FALSE";
    parameter A_CPLRESET = "FALSE";
    parameter [3:0] A_DFECFOKCFNUM = 4'h0;
    parameter [3:0] A_DFECFOKFCFN = 4'h0;
    parameter A_DFECFOKFEN = "FALSE";
    parameter A_DFECFOKFPULSE = "FALSE";
    parameter A_DFECFOKHOLD = "FALSE";
    parameter A_DFECFOKOVREN = "FALSE";
    parameter A_DFECM1DETEN = "FALSE";
    parameter [1:0] A_DFEDOUTMODE = 2'h0;
    parameter A_DFEGCHOLD = "FALSE";
    parameter A_DFEGCOVREN = "FALSE";
    parameter A_DFEH2HOLD = "FALSE";
    parameter A_DFEH2OVREN = "FALSE";
    parameter A_DFEH3HOLD = "FALSE";
    parameter A_DFEH3OVREN = "FALSE";
    parameter A_DFEH4HOLD = "FALSE";
    parameter A_DFEH4OVREN = "FALSE";
    parameter A_DFEH5HOLD = "FALSE";
    parameter A_DFEH5OVREN = "FALSE";
    parameter A_DFEH6HOLD = "FALSE";
    parameter A_DFEH6OVREN = "FALSE";
    parameter A_DFEH7HOLD = "FALSE";
    parameter A_DFEH7OVREN = "FALSE";
    parameter A_DFEKLHOLD = "FALSE";
    parameter A_DFEKLOVREN = "FALSE";
    parameter A_DFEOSHOLD = "FALSE";
    parameter A_DFEOSOVREN = "FALSE";
    parameter A_DFERESET = "FALSE";
    parameter [4:0] A_DFESTFDAC = 5'h0;
    parameter A_DFESTFEN = "FALSE";
    parameter A_DFESTFPULSE = "FALSE";
    parameter [5:0] A_DFESTFTAPNUM = 6'h0;
    parameter A_DFESTHOLD = "FALSE";
    parameter A_DFESTOVREN = "FALSE";
    parameter A_DFESTTAPCHKEN = "FALSE";
    parameter A_DFESTTAPSCNEN = "FALSE";
    parameter A_DFEUTHOLD = "FALSE";
    parameter A_DFEUTOVREN = "FALSE";
    parameter A_DFEVPHOLD = "FALSE";
    parameter A_DFEVPOVREN = "FALSE";
    parameter A_DFEVSEN = "FALSE";
    parameter A_DFEYEN = "FALSE";
    parameter A_GTRXRST = "FALSE";
    parameter A_GTTXRST = "FALSE";
    parameter A_ISCANRESET = "FALSE";
    parameter A_ISERRDETEN = "FALSE";
    parameter [2:0] A_LOOPBACK = 3'h0;
    parameter [13:0] A_LOOPENSEL = 14'h0;
    parameter A_LPMKHHOLD = "FALSE";
    parameter A_LPMKHOVREN = "FALSE";
    parameter A_LPMKLHOLD = "FALSE";
    parameter A_LPMKLOVREN = "FALSE";
    parameter A_PRBSCNTRST = "FALSE";
    parameter A_RCODABYPASS = "FALSE";
    parameter A_RCODAPWDN = "FALSE";
    parameter A_RCODARESET = "FALSE";
    parameter A_RCOOVREN = "FALSE";
    parameter A_RDASOFTRESET = "FALSE";
    parameter A_RESETOVRDB = "FALSE";
    parameter A_RXBUFRST = "FALSE";
    parameter A_RXCFOKRESET = "FALSE";
    parameter A_RXCOALGNEN = "FALSE";
    parameter A_RXCOSETPHS = "FALSE";
    parameter A_RXDAALGNEN = "FALSE";
    parameter A_RXDAOVREN = "FALSE";
    parameter A_RXFSMRESET = "FALSE";
    parameter A_RXLPMEN = "FALSE";
    parameter A_RXOOBRESET = "FALSE";
    parameter [2:0] A_RXOUTCKCTL = 3'h0;
    parameter A_RXPMARESET = "FALSE";
    parameter A_RXPOLARITY = "FALSE";
    parameter [2:0] A_RXPRBSPTN = 3'h0;
    parameter [1:0] A_RXPWRDN = 2'h0;
    parameter A_RXRESET = "FALSE";
    parameter [1:0] A_RXSYSCKSEL = 2'h0;
    parameter A_TCODABYPASS = "FALSE";
    parameter A_TCODAOVREN = "FALSE";
    parameter A_TCODAPWDN = "FALSE";
    parameter A_TCODARESET = "FALSE";
    parameter A_TCOINITSET = "FALSE";
    parameter A_TCOPIOVREN = "FALSE";
    parameter A_TDASOFTRESET = "FALSE";
    parameter A_TXCODAALGNEN = "FALSE";
    parameter A_TXCOPIALGNEN = "FALSE";
    parameter A_TXCOPISETPHS = "FALSE";
    parameter A_TXDEEMPH = "FALSE";
    parameter [3:0] A_TXDRVAMP = 4'h0;
    parameter A_TXELEIDLE = "FALSE";
    parameter A_TXEMPINVPO = "FALSE";
    parameter A_TXEMPINVPR = "FALSE";
    parameter [6:0] A_TXEMPMAIN = 7'h0;
    parameter [4:0] A_TXEMPPOS = 5'h0;
    parameter [4:0] A_TXEMPPRE = 5'h0;
    parameter A_TXINHIBIT = "FALSE";
    parameter [2:0] A_TXMARGIN = 3'h0;
    parameter [2:0] A_TXOUTCKCTL = 3'h0;
    parameter A_TXPIPPMPWDN = "FALSE";
    parameter A_TXPMARESET = "FALSE";
    parameter A_TXPOLARITY = "FALSE";
    parameter A_TXPPMOVRDEN = "FALSE";
    parameter A_TXPPMSEL = "FALSE";
    parameter A_TXPRBSINERR = "FALSE";
    parameter [2:0] A_TXPRBSPTN = 3'h0;
    parameter [2:0] A_TXPREAMP = 3'h0;
    parameter [1:0] A_TXPWRDN = 2'h0;
    parameter A_TXQPIBIASEN = "FALSE";
    parameter A_TXRESET = "FALSE";
    parameter A_TXSWING = "FALSE";
    parameter [1:0] A_TXSYSCKSEL = 2'h0;
    parameter [19:0] ADAPT_EN_CNT = 20'h0;
    parameter [15:0] AMON_CFG = 16'h0;
    parameter [82:0] CDR_CFG = 83'h0;
    parameter [5:0] CDR_LKCFG = 6'h0;
    parameter [4:0] CDR_TPHADJ = 5'h0;
    parameter [4:0] CDRFR_TIME = 5'h0;
    parameter [4:0] CDRPH_TIME = 5'h0;
    parameter CHB_KEEPALGN = "FALSE";
    parameter [3:0] CHB_MXSKW = 4'h0;
    parameter [9:0] CHB_SQ1_1 = 10'h0;
    parameter [9:0] CHB_SQ1_2 = 10'h0;
    parameter [9:0] CHB_SQ1_3 = 10'h0;
    parameter [9:0] CHB_SQ1_4 = 10'h0;
    parameter [3:0] CHB_SQ1_EN = 4'h0;
    parameter [9:0] CHB_SQ2_1 = 10'h0;
    parameter [9:0] CHB_SQ2_2 = 10'h0;
    parameter [9:0] CHB_SQ2_3 = 10'h0;
    parameter [9:0] CHB_SQ2_4 = 10'h0;
    parameter [3:0] CHB_SQ2_EN = 4'h0;
    parameter CHB_SQ2_USE = "FALSE";
    parameter [1:0] CHB_SQ_LEN = 2'h0;
    parameter [2:0] CK_REF_CFG = 3'h0;
    parameter CKC_IDLEFLAG = "FALSE";
    parameter CKC_KEEPIDLE = "FALSE";
    parameter [5:0] CKC_MNLAT = 6'h0;
    parameter [5:0] CKC_MXLAT = 6'h0;
    parameter CKC_PRECDNCE = "FALSE";
    parameter [4:0] CKC_RPTWAIT = 5'h0;
    parameter [1:0] CKC_SEQLEN = 2'h0;
    parameter [9:0] CKC_SQ1_1 = 10'h0;
    parameter [9:0] CKC_SQ1_2 = 10'h0;
    parameter [9:0] CKC_SQ1_3 = 10'h0;
    parameter [9:0] CKC_SQ1_4 = 10'h0;
    parameter [3:0] CKC_SQ1_EN = 4'h0;
    parameter [9:0] CKC_SQ2_1 = 10'h0;
    parameter [9:0] CKC_SQ2_2 = 10'h0;
    parameter [9:0] CKC_SQ2_3 = 10'h0;
    parameter [9:0] CKC_SQ2_4 = 10'h0;
    parameter [3:0] CKC_SQ2_EN = 4'h0;
    parameter CKC_SQ2_USE = "FALSE";
    parameter CKC_USE = "FALSE";
    parameter [9:0] CMA_10B_EN = 10'h0;
    parameter [2:0] CMA_ALGNWORD = 3'h0;
    parameter CMA_DOUBLE = "FALSE";
    parameter CMA_SHWREALGN = "FALSE";
    parameter [3:0] CONST_GM = 4'h0;
    parameter CONST_SWING = "FALSE";
    parameter [28:0] CPL_CFG = 29'h0;
    parameter [6:0] CPL_FBDIV = 7'h0;
    parameter CPL_FDIV45 = "FALSE";
    parameter [15:0] CPL_LKDETCFG = 16'h0;
    parameter [4:0] CPL_REFDIV = 5'h0;
    parameter CPL_REFDYEN = "FALSE";
    parameter [2:0] CPL_REFSTA = 3'h0;
    parameter [1:0] CPL_SASCF = 2'h0;
    parameter [23:0] CPL_T_LKCF = 24'h0;
    parameter [1:0] CTLE1_CE = 2'h0;
    parameter [2:0] CTLE1_ITAIL = 3'h0;
    parameter CTLE1_KHKL_USED = "FALSE";
    parameter [3:0] CTLE1_RE = 4'h0;
    parameter [1:0] CTLE2_CE = 2'h0;
    parameter [2:0] CTLE2_ITAIL = 3'h0;
    parameter CTLE2_KHKL_USED = "FALSE";
    parameter [3:0] CTLE2_RE = 4'h0;
    parameter [1:0] CTLE3_CE = 2'h0;
    parameter [2:0] CTLE3_ITAIL = 3'h0;
    parameter CTLE3_KHKL_USED = "FALSE";
    parameter [3:0] CTLE3_RE = 4'h0;
    parameter [14:0] CTLE_SPARE = 15'h0;
    parameter CTLEBIASDISSTUPB = "FALSE";
    parameter DATA_ZERO_EI = "FALSE";
    parameter [5:0] DDI_DLYSEL = 6'h0;
    parameter DEC_CMAOLY = "FALSE";
    parameter DEC_MCMA_DET = "FALSE";
    parameter DEC_PCMA_DET = "FALSE";
    parameter [41:0] DFE_CFOK_CFG = 42'h0;
    parameter [5:0] DFE_CFOKF_DAC0 = 6'h0;
    parameter [5:0] DFE_CFOKF_DAC1 = 6'h0;
    parameter [22:0] DFE_GCCFG = 23'h0;
    parameter [11:0] DFE_H2CFG = 12'h0;
    parameter [11:0] DFE_H3CFG = 12'h0;
    parameter [10:0] DFE_H4CFG = 11'h0;
    parameter [10:0] DFE_H5CFG = 11'h0;
    parameter [10:0] DFE_H6CFG = 11'h0;
    parameter [10:0] DFE_H7CFG = 11'h0;
    parameter [32:0] DFE_KLCFG = 33'h0;
    parameter [12:0] DFE_OSCFG = 13'h0;
    parameter [53:0] DFE_STCFG = 54'h0;
    parameter [6:0] DFE_TIME = 7'h0;
    parameter [16:0] DFE_UTCFG = 17'h0;
    parameter [16:0] DFE_VPCFG = 17'h0;
    parameter [8:0] DFE_VSCFG = 9'h0;
    parameter [15:0] DFELPM_MISCFG = 16'h0;
    parameter [23:0] DMON_CFG = 24'h0;
    parameter DRPEN_CDR = "FALSE";
    parameter DRPEN_CPL = "FALSE";
    parameter DRPEN_DFE = "FALSE";
    parameter DRPEN_LPBK = "FALSE";
    parameter DRPEN_LPM = "FALSE";
    parameter DRPEN_MASTER = "FALSE";
    parameter DRPEN_PDIDLE = "FALSE";
    parameter DRPEN_POL = "FALSE";
    parameter DRPEN_PRBS = "FALSE";
    parameter DRPEN_QPI = "FALSE";
    parameter DRPEN_RCODA = "FALSE";
    parameter DRPEN_RESET = "FALSE";
    parameter DRPEN_RXOCKSEL = "FALSE";
    parameter DRPEN_RXSYCKSEL = "FALSE";
    parameter DRPEN_TCODA = "FALSE";
    parameter DRPEN_TXDRV = "FALSE";
    parameter DRPEN_TXOCKSEL = "FALSE";
    parameter DRPEN_TXPIPPM = "FALSE";
    parameter DRPEN_TXSYCKSEL = "FALSE";
    parameter [5:0] ES_CONTROL = 6'h0;
    parameter ES_EN_ERRDET = "FALSE";
    parameter ES_EN_EYESCAN = "FALSE";
    parameter [11:0] ES_HORZOFFSET = 12'h0;
    parameter [4:0] ES_PRESCALE = 5'h0;
    parameter [79:0] ES_QUALIFIER = 80'h0;
    parameter [79:0] ES_QUALMASK = 80'h0;
    parameter [79:0] ES_SDATAMASK = 80'h0;
    parameter [8:0] ES_VERTOFFSET = 9'h0;
    parameter [3:0] FTS_DSKW_SQEN = 4'h0;
    parameter FTS_LNDESCKEW_EN = "FALSE";
    parameter [3:0] FTS_LNDSKW_CF = 4'h0;
    parameter GEN_RXUSRCK = "FALSE";
    parameter GEN_TXUSRCK = "FALSE";
    parameter [2:0] GRBX_ENDEC = 3'h0;
    parameter GREY_SEL = "FALSE";
    parameter [9:0] GT_PWRSAVE = 10'h0;
    parameter GT_PWRUP = "FALSE";
    parameter INV_ALTSIGVALCLK = "FALSE";
    parameter INV_CKPINRSRVD0 = "FALSE";
    parameter INV_CKPINRSRVD1 = "FALSE";
    parameter INV_CORERFCK = "FALSE";
    parameter INV_CPLDMONCK = "FALSE";
    parameter INV_DCK = "FALSE";
    parameter INV_DMONCLK = "FALSE";
    parameter INV_PMASCANCK0 = "FALSE";
    parameter INV_PMASCANCK1 = "FALSE";
    parameter INV_PMASCANCK2 = "FALSE";
    parameter INV_PMASCANCK3 = "FALSE";
    parameter INV_PMASCANCK4 = "FALSE";
    parameter INV_RUCK2 = "FALSE";
    parameter INV_RUCK = "FALSE";
    parameter INV_SCANCK = "FALSE";
    parameter INV_TCOCKFSMFROUT = "FALSE";
    parameter INV_TSTCK0 = "FALSE";
    parameter INV_TSTCK1 = "FALSE";
    parameter INV_TUCK2 = "FALSE";
    parameter INV_TUCK = "FALSE";
    parameter INVSTROBE_SEL = "FALSE";
    parameter [9:0] IS_CFG = 10'h0;
    parameter ISCAN_CK_PH_SEL = "FALSE";
    parameter [4:0] ISCAN_TIME = 5'h0;
    parameter [13:0] LPM_KHCFG = 14'h0;
    parameter [17:0] LPM_KLCFG = 18'h0;
    parameter [9:0] MCMA_10BVAL = 10'h0;
    parameter MCMA_DETECT = "FALSE";
    parameter MNT_ACJTAG_ACMODE = "FALSE";
    parameter MNT_ACJTAG_EN = "FALSE";
    parameter MNT_ACJTAG_RESETB = "FALSE";
    parameter OOB_CLK_SRC = "FALSE";
    parameter PCD_TWOUI = "FALSE";
    parameter PCIE_MODE = "FALSE";
    parameter [9:0] PCMA_10BVAL = 10'h0;
    parameter PCMA_DETECT = "FALSE";
    parameter [47:0] PCS_RSVD = 48'h0;
    parameter [31:0] PMASAVEATTR = 32'h0;
    parameter PPMCLK_SEL = "FALSE";
    parameter [7:0] PPMPICFG = 8'h0;
    parameter [23:0] RCO_COMLGCFG = 24'h0;
    parameter [15:0] RCO_DACFG = 16'h0;
    parameter [15:0] RCO_DLYCFG = 16'h0;
    parameter [8:0] RCO_LPFCFG = 9'h0;
    parameter [4:0] RCO_MONSEL = 5'h0;
    parameter [23:0] RCO_PHSSETCFG = 24'h0;
    parameter RST_PWSV_DISABLE = "FALSE";
    parameter [3:0] RTERM_VCMLVL = 4'h0;
    parameter [1:0] RTERM_VCMMODE = 2'h0;
    parameter [23:0] RX_BIASSET = 24'h0;
    parameter [4:0] RX_BUF_TIME = 5'h0;
    parameter [5:0] RX_BUFFER_CFG = 6'h0;
    parameter [6:0] RX_CDRALL_TIME = 7'h0;
    parameter [4:0] RX_CFOK_TIME = 5'h0;
    parameter [4:0] RX_CFOK_TO = 5'h0;
    parameter [4:0] RX_CK25DIV = 5'h0;
    parameter [2:0] RX_DATA_WIDTH = 3'h0;
    parameter [13:0] RX_DBGCFG = 14'h0;
    parameter RX_DECSQMCH = "FALSE";
    parameter RX_DEFER_RSTBF_EN = "FALSE";
    parameter RX_DIVBYFIVE = "FALSE";
    parameter RX_GRBXUSE = "FALSE";
    parameter [4:0] RX_INIT_TIME = 5'h0;
    parameter RX_LPBKPRBS = "FALSE";
    parameter [6:0] RX_OOBCFG = 7'h0;
    parameter [4:0] RX_PCS_TIME = 5'h0;
    parameter RX_PLLSEL = "FALSE";
    parameter [2:0] RX_RATEMODE = 3'h0;
    parameter [4:0] RX_SIGVAL_DLY = 5'h0;
    parameter RX_SKP_DLY_ALIGN = "FALSE";
    parameter [1:0] RX_SLDMOD = 2'h0;
    parameter [3:0] RX_SLDWAIT = 4'h0;
    parameter [31:0] RX_SPRD = 32'h0;
    parameter RX_WIDEMODE = "FALSE";
    parameter RX_XCKSEL = "FALSE";
    parameter RXB_BFRUSE = "FALSE";
    parameter [5:0] RXB_OVFTH = 6'h0;
    parameter RXB_OVRDTH = "FALSE";
    parameter RXB_RALGNRST = "FALSE";
    parameter RXB_RCHGRSTEN = "FALSE";
    parameter RXB_RSTEN = "FALSE";
    parameter [5:0] RXB_UDFTH = 6'h0;
    parameter RXCKMUX_PWDNB = "FALSE";
    parameter RXDISPERR_SQ_MCH = "FALSE";
    parameter RXF_ADDRSEL = "FALSE";
    parameter [3:0] RXI_HICNT = 4'h0;
    parameter RXI_HLDCDR = "FALSE";
    parameter RXI_HLDDFE = "FALSE";
    parameter [3:0] RXI_LOCNT = 4'h0;
    parameter RXI_RSTBFR = "FALSE";
    parameter RXI_RSTFR = "FALSE";
    parameter RXI_RSTPH = "FALSE";
    parameter [1:0] RXIBIAS_DCDC = 2'h0;
    parameter [1:0] RXIBIAS_LA1 = 2'h0;
    parameter [1:0] RXIBIAS_MID = 2'h0;
    parameter [1:0] RXIBIAS_MIXBUF = 2'h0;
    parameter RXMIXER_ICAP = "FALSE";
    parameter RXMIXER_OCAP = "FALSE";
    parameter RXSYNC_FSM_MULTI = "FALSE";
    parameter RXSYNC_FSMOVR_EN = "FALSE";
    parameter [2:0] RXVREF = 3'h0;
    parameter [2:0] SAS_BUSTVAL = 3'h0;
    parameter [1:0] SAS_CKSRC = 2'h0;
    parameter [3:0] SAS_COMBRST = 4'h0;
    parameter [2:0] SAS_IDLEVAL = 3'h0;
    parameter [5:0] SAS_MNBRST = 6'h0;
    parameter [5:0] SAS_MNCOMS = 6'h0;
    parameter [5:0] SAS_MNINIT = 6'h0;
    parameter [5:0] SAS_MNWAKE = 6'h0;
    parameter [5:0] SAS_MXBRST = 6'h0;
    parameter [6:0] SAS_MXCOMS = 7'h0;
    parameter [5:0] SAS_MXINIT = 6'h0;
    parameter [5:0] SAS_MXWAKE = 6'h0;
    parameter [2:0] SYNFREQ_PPM = 3'h0;
    parameter [23:0] TCO_COMLGCFG = 24'h0;
    parameter [15:0] TCO_DACFG = 16'h0;
    parameter [15:0] TCO_DLYCFG = 16'h0;
    parameter [8:0] TCO_LPFCFG = 9'h0;
    parameter [4:0] TCO_MONSEL = 5'h0;
    parameter [15:0] TCO_PICFG = 16'h0;
    parameter [14:0] TERM_CTRL = 15'h0;
    parameter [2:0] TERM_OVR = 3'h0;
    parameter [11:0] TRN_T_FRMP2 = 12'h0;
    parameter [7:0] TRN_T_NONP2 = 8'h0;
    parameter [7:0] TRN_T_RATE = 8'h0;
    parameter [7:0] TRN_T_TOP2 = 8'h0;
    parameter [31:0] TST_CF = 32'h0;
    parameter [4:0] TX_CK25DIV = 5'h0;
    parameter TX_CKSEL = "FALSE";
    parameter [2:0] TX_DATA_WIDTH = 3'h0;
    parameter [1:0] TX_DCCCF = 2'h0;
    parameter [5:0] TX_DEEMPH_0 = 6'h0;
    parameter [5:0] TX_DEEMPH_1 = 6'h0;
    parameter TX_DIVBYFIVE = "FALSE";
    parameter TX_EMPMAIN_INDEP = "FALSE";
    parameter TX_GRBXEN = "FALSE";
    parameter [4:0] TX_INIT_TIME = 5'h0;
    parameter TX_OCKSEL = "FALSE";
    parameter [4:0] TX_PCS_TIME = 5'h0;
    parameter TX_PLLSEL = "FALSE";
    parameter TX_PMADATAOPT = "FALSE";
    parameter [2:0] TX_RATEMODE = 3'h0;
    parameter TX_RCHGRSTEN = "FALSE";
    parameter [2:0] TX_RCVREF = 3'h0;
    parameter [13:0] TX_RDETCF = 14'h0;
    parameter TX_SKP_DLY_ALIGN = "FALSE";
    parameter [3:0] TX_SPARE = 4'h0;
    parameter TX_WIDEMODE = "FALSE";
    parameter TXB_BFUSE = "FALSE";
    parameter TXCKMUX_PWDNB = "FALSE";
    parameter [4:0] TXD_DRVMODE = 5'h0;
    parameter TXD_LPBKHIZ = "FALSE";
    parameter [2:0] TXI_ASRTDLY = 3'h0;
    parameter [2:0] TXI_DEASDLY = 3'h0;
    parameter [1:0] TXIBIAS_DCDC = 2'h0;
    parameter [1:0] TXIBIAS_LA1 = 2'h0;
    parameter [1:0] TXIBIAS_MIXBUF = 2'h0;
    parameter [6:0] TXM_FULL_0 = 7'h0;
    parameter [6:0] TXM_FULL_1 = 7'h0;
    parameter [6:0] TXM_FULL_2 = 7'h0;
    parameter [6:0] TXM_FULL_3 = 7'h0;
    parameter [6:0] TXM_FULL_4 = 7'h0;
    parameter [6:0] TXM_LOW_0 = 7'h0;
    parameter [6:0] TXM_LOW_1 = 7'h0;
    parameter [6:0] TXM_LOW_2 = 7'h0;
    parameter [6:0] TXM_LOW_3 = 7'h0;
    parameter [6:0] TXM_LOW_4 = 7'h0;
    parameter TXMIXER_ICAP = "FALSE";
    parameter TXMIXER_OCAP = "FALSE";
    parameter TXQPI_STATEN = "FALSE";
    parameter [16:0] TXRDETPRET = 17'h0;
    parameter TXSYNC_FSM_MULTI = "FALSE";
    parameter TXSYNC_FSMOVR_EN = "FALSE";
    parameter [2:0] TXVREF = 3'h0;
    parameter UCODEER_CLR = "FALSE";
    parameter USEPCS_ISCAN_CKPH = "FALSE";
    parameter [79:0] CH_DEBUGCFG = 80'h0;
endmodule

(* black_box, dont_touch="true" *)
module xsSERDES_COM_E1(
    // to ch
    output  QPLLOUTCLK,
    // to clk and pll?
    output QDCMREFCLK_INT_CIB,
    // to PAD
    //input RREF,
//    input MGTREFCLK0N,
//    input MGTREFCLK0P,
//    input MGTREFCLK1N,
//    input MGTREFCLK1P,
	input GTNORTHREFCLK0,
	input GTNORTHREFCLK1,
	input GTSOUTHREFCLK0,
	input GTSOUTHREFCLK1,
	input GTREFCLK0,
	input GTREFCLK1,
    // CIB
    input ACJTAGRESETB_INT_CIB,
    output ACJTAGRESETB_INT_OUT_CIB,
    input ACMODE_INT_CIB,
    input ACTEST_INT_CIB,
    input BGBYPASS,
    input [4:0] BGRCALCTL,
    input BGRCALOVRDENB,
    input BGTESTEN,
//    input CFGMCLK_INT,
//    input CFGRESET,
//    input CFGRESET_INT,
    input CLKDR_INT_CIB,
    output CLKDR_INT_OUT_CIB,
    output [3:0] COM_DEBUG_TSTO_CIB,
    input COREREFCLK,
    input [7:0] DADDR_COM,
    input DCLK_COM,
    input DEN_COM,
    input [15:0] DI_COM,
    output [7:0] DMONOUT_QDCM_B,
    output DRDY_B_COM,
    output [15:0] DRPDO_B_COM,
    input DWE_COM,
    input EXTEST_INT_CIB,
    input EXTEST_SMPL_INT_CIB,
    input GHIGH_B_INT,
    input GPWRDWN_B_INT,
//    input GRESTORE_INT,
//    input GWE_INT,
//////    input IBUFDS0_CEB,
//////    output IBUFDS0_O_CIB,
//////    output IBUFDS0_ODIV2_CIB,
//
//////    input IBUFDS0_CLKCM_CFG,
//////    input IBUFDS0_CLKRCV_TRST,
//////    input [1:0] IBUFDS0_CLKSWING_CFG,
//////    input IBUFDS0_CLKTESTSIG,
//////    input IBUFDS0_DIV2RST_B,
//////    input [1:0] IBUFDS0_REFCLK_CTRL,
//
//////    input IBUFDS1_CEB,
//////    input IBUFDS1_CLKCM_CFG,
//////    input IBUFDS1_CLKRCV_TRST,
//////    input [1:0] IBUFDS1_CLKSWING_CFG,
//////    input IBUFDS1_CLKTESTSIG,
//////    input IBUFDS1_DIV2RST_B,
//////    output IBUFDS1_O_CIB,
//////    output IBUFDS1_ODIV2_CIB,
//////    input [1:0] IBUFDS1_REFCLK_CTRL,
    input INITMEM_INT_CIB,
    output MGTREFCLKFA_B,
//    output MGTSAPOUT_CIB,
    input MNTR_ACJTAG_ACMODE_CIB,
    input MNTR_ACJTAG_EN_CIB,
    input MNTR_ACJTAG_RESETB_CIB,
//    input NORTHREFCLK0,
//    input NORTHREFCLK1,
//    input POR_B_INT,
    input PWRDNBGB,
    input QDCLKPINSPRD0,
    input QDCLKPINSPRD1,
    output [15:0] QDCMRSVDOUT_B,
    input [15:0] QDCMRSVDPIN,
    input [4:0] QDPINSPRD,
    input [7:0] QDPMAPINRSVD,
    input QDPMASCANCLK0,
    input QDPMASCANCLK1,
    input QDPMASCANENB,
    input [4:0] QDPMASCANIN,
    input QDPMASCANMODEB,
    output [4:0] QDPMASCANOUT_B,
    input QDPMASCANRSTEN,
    input QPLCKRESET,
    output [5:0] QPLCRSCODE_INT,
    output QPLFBLOSS_B,
    output QPLFREQLOCK_B,
    input QPLLDMONCLK,
    input QPLLKDETEN,
    input QPLPWRDN,
    input [2:0] QPLREFDYN,
    output QPLREFLOSS_B,
    input QPLRESET,
    input RCALENB,
//    input [4:0] RCALINNORTH,
//    input [4:0] RCALINSOUTH,
//    output [4:0] RCALOUTNORTH,
//    output [4:0] RCALOUTSOUTH,
    input [1:0] RCALSEL,
    input REFCKPD0,
    input REFCKPD1,
    input REFCKTESTCLK0,
    output REFCKTESTCLK0_INT,
    input REFCKTESTCLK1,
    output REFCKTESTCLK1_INT,
    output RING_OSC_CLK_CIB,
    input [3:0] SA_RX_DMONSEL_CIB,
    input SHIFTDR_INT_CIB,
    output SHIFTDR_INT_OUT_CIB,
//    input SOUTHREFCLK0,
//    input SOUTHREFCLK1,
    input TDI_CIB,
    output TDO_CIB,
    input UPDATEDR_INT_CIB)/*synthesis syn_black_box syn_noprune=1*/;
    parameter A_BGTESTEN = "FALSE";
    parameter A_PWRDNBG = "FALSE";
    parameter A_QPLCKRESET = "FALSE";
    parameter A_QPLLKDETEN = "FALSE";
    parameter A_QPLPWRDN = "FALSE";
    parameter A_QPLRESET = "FALSE";
    parameter A_REFCKPD0 = "FALSE";
    parameter A_REFCKPD1 = "FALSE";
    parameter [2:0] AQDMUXSEL = 3'h0;
    parameter [63:0] BS_MSTRCF = 64'h0;
    parameter [63:0] COM_DEBUGCFG = 64'h0;
    parameter DRPEN_BGBS = "FALSE";
    parameter DRPEN_MASTER_COM = "FALSE";
    parameter DRPEN_PD = "FALSE";
    parameter DRPEN_QPL = "FALSE";
    parameter DRPEN_REFCK = "FALSE";
    parameter DRPEN_RESET_COM = "FALSE";
    parameter INV_CORERFCK_COM = "FALSE";
    parameter INV_DCK_COM = "FALSE";
    parameter INV_PMASCANCK0_COM = "FALSE";
    parameter INV_PMASCANCK1_COM = "FALSE";
    parameter INV_QPLDMONCK = "FALSE";
    parameter INV_QPLSPRDCK0 = "FALSE";
    parameter INV_QPLSPRDCK1 = "FALSE";
    parameter INV_REFCKTESTCK0 = "FALSE";
    parameter INV_REFCKTESTCK1 = "FALSE";
    parameter [1:0] NREFCK0_SEL = 2'h0;
    parameter [1:0] NREFCK1_SEL = 2'h0;
    parameter [1:0] QDCM_AMUXSEL = 2'h0;
    parameter [3:0] QDCM_CKBFSET = 4'h0;
    parameter [31:0] QDCM_PMACFG = 32'h0;
    parameter QDCM_PWRUP = "FALSE";
    parameter [1:0] QPL_AMONSEL = 2'h0;
    parameter [26:0] QPL_CFG = 27'h0;
    parameter QPL_DIVFORMSET = "FALSE";
    parameter QPL_DMONSEL = "FALSE";
    parameter QPL_FBCKMON_EN = "FALSE";
    parameter [9:0] QPL_FBDIV = 10'h0;
    parameter QPL_ICPMON_EN = "FALSE";
    parameter [9:0] QPL_ICPSET = 10'h0;
    parameter [15:0] QPL_LKDETCF = 16'h0;
    parameter [3:0] QPL_LPFSET = 4'h0;
    parameter [4:0] QPL_PREDIV = 5'h0;
    parameter QPL_REFDYEN = "FALSE";
    parameter [2:0] QPL_REFSTA = 3'h0;
    parameter QPL_REGMON_EN = "FALSE";
    parameter [23:0] QPL_T_LKCF = 24'h0;
    parameter [5:0] QPL_VCOOVRCD = 6'h0;
    parameter QPL_VCOOVRDEN = "FALSE";
    parameter QPL_VCTMON_EN = "FALSE";
    parameter [1:0] RCAL_CFG = 2'h0;
    parameter [1:0] REFC_BSSEL = 2'h0;
    parameter [1:0] REFC_CMCF = 2'h0;
    parameter [3:0] REFC_HRWCF = 4'h0;
    parameter [1:0] REFC_RESCF = 2'h0;
    parameter RP_COMP = "FALSE";
    parameter [15:0] RSVD_ATTR0 = 16'h0;
    parameter [15:0] RSVD_ATTR1 = 16'h0;
    parameter [1:0] SREFCK0_SEL = 2'h0;
    parameter [1:0] SREFCK1_SEL = 2'h0;
    parameter [1:0] VCTRL_RESET = 2'h0;
endmodule

(* black_box, dont_touch="true" *)
module xsSERDES_COM_E2(
    // 200k new
    output [4:0] RCAL_O,
    // 200k end
    // to ch
    output  QPLLOUTCLK,
    // to clk and pll?
    output QDCMREFCLK_INT_CIB,
    // to PAD
    //input RREF,
//    input MGTREFCLK0N,
//    input MGTREFCLK0P,
//    input MGTREFCLK1N,
//    input MGTREFCLK1P,
	input GTNORTHREFCLK0,
	input GTNORTHREFCLK1,
	input GTSOUTHREFCLK0,
	input GTSOUTHREFCLK1,
	input GTREFCLK0,
	input GTREFCLK1,
    // CIB
    input ACJTAGRESETB_INT_CIB,
    output ACJTAGRESETB_INT_OUT_CIB,
    input ACMODE_INT_CIB,
    input ACTEST_INT_CIB,
    input BGBYPASS,
    input [4:0] BGRCALCTL,
    input BGRCALOVRDENB,
    input BGTESTEN,
//    input CFGMCLK_INT,
//    input CFGRESET,
//    input CFGRESET_INT,
    input CLKDR_INT_CIB,
    output CLKDR_INT_OUT_CIB,
    output [3:0] COM_DEBUG_TSTO_CIB,
    input COREREFCLK,
    input [7:0] DADDR_COM,
    input DCLK_COM,
    input DEN_COM,
    input [15:0] DI_COM,
    output [7:0] DMONOUT_QDCM_B,
    output DRDY_B_COM,
    output [15:0] DRPDO_B_COM,
    input DWE_COM,
    input EXTEST_INT_CIB,
    input EXTEST_SMPL_INT_CIB,
    input GHIGH_B_INT,
    input GPWRDWN_B_INT,
//    input GRESTORE_INT,
//    input GWE_INT,
//////    input IBUFDS0_CEB,
//////    output IBUFDS0_O_CIB,
//////    output IBUFDS0_ODIV2_CIB,
//
//////    input IBUFDS0_CLKCM_CFG,
//////    input IBUFDS0_CLKRCV_TRST,
//////    input [1:0] IBUFDS0_CLKSWING_CFG,
//////    input IBUFDS0_CLKTESTSIG,
//////    input IBUFDS0_DIV2RST_B,
//////    input [1:0] IBUFDS0_REFCLK_CTRL,
//
//////    input IBUFDS1_CEB,
//////    input IBUFDS1_CLKCM_CFG,
//////    input IBUFDS1_CLKRCV_TRST,
//////    input [1:0] IBUFDS1_CLKSWING_CFG,
//////    input IBUFDS1_CLKTESTSIG,
//////    input IBUFDS1_DIV2RST_B,
//////    output IBUFDS1_O_CIB,
//////    output IBUFDS1_ODIV2_CIB,
//////    input [1:0] IBUFDS1_REFCLK_CTRL,
    input INITMEM_INT_CIB,
    output MGTREFCLKFA_B,
//    output MGTSAPOUT_CIB,
    input MNTR_ACJTAG_ACMODE_CIB,
    input MNTR_ACJTAG_EN_CIB,
    input MNTR_ACJTAG_RESETB_CIB,
//    input NORTHREFCLK0,
//    input NORTHREFCLK1,
//    input POR_B_INT,
    input PWRDNBGB,
    input QDCLKPINSPRD0,
    input QDCLKPINSPRD1,
    output [15:0] QDCMRSVDOUT_B,
    input [15:0] QDCMRSVDPIN,
    input [4:0] QDPINSPRD,
    input [7:0] QDPMAPINRSVD,
    input QDPMASCANCLK0,
    input QDPMASCANCLK1,
    input QDPMASCANENB,
    input [4:0] QDPMASCANIN,
    input QDPMASCANMODEB,
    output [4:0] QDPMASCANOUT_B,
    input QDPMASCANRSTEN,
    input QPLCKRESET,
    output [5:0] QPLCRSCODE_INT,
    output QPLFBLOSS_B,
    output QPLFREQLOCK_B,
    input QPLLDMONCLK,
    input QPLLKDETEN,
    input QPLPWRDN,
    input [2:0] QPLREFDYN,
    output QPLREFLOSS_B,
    input QPLRESET,
    input RCALENB,
//    input [4:0] RCALINNORTH,
//    input [4:0] RCALINSOUTH,
//    output [4:0] RCALOUTNORTH,
//    output [4:0] RCALOUTSOUTH,
    input [1:0] RCALSEL,
    input REFCKPD0,
    input REFCKPD1,
    input REFCKTESTCLK0,
    output REFCKTESTCLK0_INT,
    input REFCKTESTCLK1,
    output REFCKTESTCLK1_INT,
    output RING_OSC_CLK_CIB,
    input [3:0] SA_RX_DMONSEL_CIB,
    input SHIFTDR_INT_CIB,
    output SHIFTDR_INT_OUT_CIB,
//    input SOUTHREFCLK0,
//    input SOUTHREFCLK1,
    input TDI_CIB,
    output TDO_CIB,
    input UPDATEDR_INT_CIB)/*synthesis syn_black_box syn_noprune=1*/;
    parameter A_BGTESTEN = "FALSE";
    parameter A_PWRDNBG = "FALSE";
    parameter A_QPLCKRESET = "FALSE";
    parameter A_QPLLKDETEN = "FALSE";
    parameter A_QPLPWRDN = "FALSE";
    parameter A_QPLRESET = "FALSE";
    parameter A_REFCKPD0 = "FALSE";
    parameter A_REFCKPD1 = "FALSE";
    parameter [2:0] AQDMUXSEL = 3'h0;
    parameter [63:0] BS_MSTRCF = 64'h0;
    parameter [63:0] COM_DEBUGCFG = 64'h0;
    parameter DRPEN_BGBS = "FALSE";
    parameter DRPEN_MASTER_COM = "FALSE";
    parameter DRPEN_PD = "FALSE";
    parameter DRPEN_QPL = "FALSE";
    parameter DRPEN_REFCK = "FALSE";
    parameter DRPEN_RESET_COM = "FALSE";
    parameter INV_CORERFCK_COM = "FALSE";
    parameter INV_DCK_COM = "FALSE";
    parameter INV_PMASCANCK0_COM = "FALSE";
    parameter INV_PMASCANCK1_COM = "FALSE";
    parameter INV_QPLDMONCK = "FALSE";
    parameter INV_QPLSPRDCK0 = "FALSE";
    parameter INV_QPLSPRDCK1 = "FALSE";
    parameter INV_REFCKTESTCK0 = "FALSE";
    parameter INV_REFCKTESTCK1 = "FALSE";
    parameter [1:0] NREFCK0_SEL = 2'h0;
    parameter [1:0] NREFCK1_SEL = 2'h0;
    parameter [1:0] QDCM_AMUXSEL = 2'h0;
    parameter [3:0] QDCM_CKBFSET = 4'h0;
    parameter [31:0] QDCM_PMACFG = 32'h0;
    parameter QDCM_PWRUP = "FALSE";
    parameter [1:0] QPL_AMONSEL = 2'h0;
    parameter [26:0] QPL_CFG = 27'h0;
    parameter QPL_DIVFORMSET = "FALSE";
    parameter QPL_DMONSEL = "FALSE";
    parameter QPL_FBCKMON_EN = "FALSE";
    parameter [9:0] QPL_FBDIV = 10'h0;
    parameter QPL_ICPMON_EN = "FALSE";
    parameter [9:0] QPL_ICPSET = 10'h0;
    parameter [15:0] QPL_LKDETCF = 16'h0;
    parameter [3:0] QPL_LPFSET = 4'h0;
    parameter [4:0] QPL_PREDIV = 5'h0;
    parameter QPL_REFDYEN = "FALSE";
    parameter [2:0] QPL_REFSTA = 3'h0;
    parameter QPL_REGMON_EN = "FALSE";
    parameter [23:0] QPL_T_LKCF = 24'h0;
    parameter [5:0] QPL_VCOOVRCD = 6'h0;
    parameter QPL_VCOOVRDEN = "FALSE";
    parameter QPL_VCTMON_EN = "FALSE";
    parameter [1:0] RCAL_CFG = 2'h0;
    parameter [1:0] REFC_BSSEL = 2'h0;
    parameter [1:0] REFC_CMCF = 2'h0;
    parameter [3:0] REFC_HRWCF = 4'h0;
    parameter [1:0] REFC_RESCF = 2'h0;
    parameter RP_COMP = "FALSE";
    parameter [15:0] RSVD_ATTR0 = 16'h0;
    parameter [15:0] RSVD_ATTR1 = 16'h0;
    parameter [1:0] SREFCK0_SEL = 2'h0;
    parameter [1:0] SREFCK1_SEL = 2'h0;
    parameter [1:0] VCTRL_RESET = 2'h0;
endmodule

(* black_box, dont_touch="true" *)
module xsSERDES_COM(
    // to clk and pll?
    output QDCMREFCLK_INT_CIB,
    // to PAD
    //input RREF,
    input MGTREFCLK0N,
    input MGTREFCLK0P,
    input MGTREFCLK1N,
    input MGTREFCLK1P,
//	input MGTREFCLK0,//mod by sdfu 2023-03-17 11:12:32
//	input MGTREFCLK1,
    // CIB
    input ACJTAGRESETB_INT_CIB,
    output ACJTAGRESETB_INT_OUT_CIB,
    input ACMODE_INT_CIB,
    input ACTEST_INT_CIB,
    input BGBYPASS,
    input [4:0] BGRCALCTL,
    input BGRCALOVRDENB,
    input BGTESTEN,
//    input CFGMCLK_INT,
//    input CFGRESET,
//    input CFGRESET_INT,
    input CLKDR_INT_CIB,
    output CLKDR_INT_OUT_CIB,
    output [3:0] COM_DEBUG_TSTO_CIB,
    input COREREFCLK,
    input [7:0] DADDR_COM,
    input DCLK_COM,
    input DEN_COM,
    input [15:0] DI_COM,
    output [7:0] DMONOUT_QDCM_B,
    output DRDY_B_COM,
    output [15:0] DRPDO_B_COM,
    input DWE_COM,
    input EXTEST_INT_CIB,
    input EXTEST_SMPL_INT_CIB,
    input GHIGH_B_INT,
    input GPWRDWN_B_INT,
//    input GRESTORE_INT,
//    input GWE_INT,
    input IBUFDS0_CEB,
    output IBUFDS0_O_CIB,
    output IBUFDS0_ODIV2_CIB,

    input IBUFDS0_CLKCM_CFG,
    input IBUFDS0_CLKRCV_TRST,
    input [1:0] IBUFDS0_CLKSWING_CFG,
    input IBUFDS0_CLKTESTSIG,
    input IBUFDS0_DIV2RST_B,
    input [1:0] IBUFDS0_REFCLK_CTRL,

    input IBUFDS1_CEB,
    input IBUFDS1_CLKCM_CFG,
    input IBUFDS1_CLKRCV_TRST,
    input [1:0] IBUFDS1_CLKSWING_CFG,
    input IBUFDS1_CLKTESTSIG,
    input IBUFDS1_DIV2RST_B,
    output IBUFDS1_O_CIB,
    output IBUFDS1_ODIV2_CIB,
    input [1:0] IBUFDS1_REFCLK_CTRL,

    input INITMEM_INT_CIB,
    output MGTREFCLKFA_B,
//    output MGTSAPOUT_CIB,
    input MNTR_ACJTAG_ACMODE_CIB,
    input MNTR_ACJTAG_EN_CIB,
    input MNTR_ACJTAG_RESETB_CIB,
//    input NORTHREFCLK0,
//    input NORTHREFCLK1,
//    input POR_B_INT,
    input PWRDNBGB,
    input QDCLKPINSPRD0,
    input QDCLKPINSPRD1,
    output [15:0] QDCMRSVDOUT_B,
    input [15:0] QDCMRSVDPIN,
    input [4:0] QDPINSPRD,
    input [7:0] QDPMAPINRSVD,
    input QDPMASCANCLK0,
    input QDPMASCANCLK1,
    input QDPMASCANENB,
    input [4:0] QDPMASCANIN,
    input QDPMASCANMODEB,
    output [4:0] QDPMASCANOUT_B,
    input QDPMASCANRSTEN,
    input QPLCKRESET,
    output [5:0] QPLCRSCODE_INT,
    output QPLFBLOSS_B,
    output QPLFREQLOCK_B,
    input QPLLDMONCLK,
    input QPLLKDETEN,
    input QPLPWRDN,
    input [2:0] QPLREFDYN,
    output QPLREFLOSS_B,
    input QPLRESET,
    input RCALENB,
//    input [4:0] RCALINNORTH,
//    input [4:0] RCALINSOUTH,
//    output [4:0] RCALOUTNORTH,
//    output [4:0] RCALOUTSOUTH,
    input [1:0] RCALSEL,
    input REFCKPD0,
    input REFCKPD1,
    input REFCKTESTCLK0,
    output REFCKTESTCLK0_INT,
    input REFCKTESTCLK1,
    output REFCKTESTCLK1_INT,
    output RING_OSC_CLK_CIB,
    input [3:0] SA_RX_DMONSEL_CIB,
    input SHIFTDR_INT_CIB,
    output SHIFTDR_INT_OUT_CIB,
//    input SOUTHREFCLK0,
//    input SOUTHREFCLK1,
    input TDI_CIB,
    output TDO_CIB,
    input UPDATEDR_INT_CIB)/*synthesis syn_black_box syn_noprune=1*/;
    parameter A_BGTESTEN = "FALSE";
    parameter A_PWRDNBG = "FALSE";
    parameter A_QPLCKRESET = "FALSE";
    parameter A_QPLLKDETEN = "FALSE";
    parameter A_QPLPWRDN = "FALSE";
    parameter A_QPLRESET = "FALSE";
    parameter A_REFCKPD0 = "FALSE";
    parameter A_REFCKPD1 = "FALSE";
    parameter [2:0] AQDMUXSEL = 3'h0;
    parameter [63:0] BS_MSTRCF = 64'h0;
    parameter [63:0] COM_DEBUGCFG = 64'h0;
    parameter DRPEN_BGBS = "FALSE";
    parameter DRPEN_MASTER_COM = "FALSE";
    parameter DRPEN_PD = "FALSE";
    parameter DRPEN_QPL = "FALSE";
    parameter DRPEN_REFCK = "FALSE";
    parameter DRPEN_RESET_COM = "FALSE";
    parameter INV_CORERFCK_COM = "FALSE";
    parameter INV_DCK_COM = "FALSE";
    parameter INV_PMASCANCK0_COM = "FALSE";
    parameter INV_PMASCANCK1_COM = "FALSE";
    parameter INV_QPLDMONCK = "FALSE";
    parameter INV_QPLSPRDCK0 = "FALSE";
    parameter INV_QPLSPRDCK1 = "FALSE";
    parameter INV_REFCKTESTCK0 = "FALSE";
    parameter INV_REFCKTESTCK1 = "FALSE";
    parameter [1:0] NREFCK0_SEL = 2'h0;
    parameter [1:0] NREFCK1_SEL = 2'h0;
    parameter [1:0] QDCM_AMUXSEL = 2'h0;
    parameter [3:0] QDCM_CKBFSET = 4'h0;
    parameter [31:0] QDCM_PMACFG = 32'h0;
    parameter QDCM_PWRUP = "FALSE";
    parameter [1:0] QPL_AMONSEL = 2'h0;
    parameter [26:0] QPL_CFG = 27'h0;
    parameter QPL_DIVFORMSET = "FALSE";
    parameter QPL_DMONSEL = "FALSE";
    parameter QPL_FBCKMON_EN = "FALSE";
    parameter [9:0] QPL_FBDIV = 10'h0;
    parameter QPL_ICPMON_EN = "FALSE";
    parameter [9:0] QPL_ICPSET = 10'h0;
    parameter [15:0] QPL_LKDETCF = 16'h0;
    parameter [3:0] QPL_LPFSET = 4'h0;
    parameter [4:0] QPL_PREDIV = 5'h0;
    parameter QPL_REFDYEN = "FALSE";
    parameter [2:0] QPL_REFSTA = 3'h0;
    parameter QPL_REGMON_EN = "FALSE";
    parameter [23:0] QPL_T_LKCF = 24'h0;
    parameter [5:0] QPL_VCOOVRCD = 6'h0;
    parameter QPL_VCOOVRDEN = "FALSE";
    parameter QPL_VCTMON_EN = "FALSE";
    parameter [1:0] RCAL_CFG = 2'h0;
    parameter [1:0] REFC_BSSEL = 2'h0;
    parameter [1:0] REFC_CMCF = 2'h0;
    parameter [3:0] REFC_HRWCF = 4'h0;
    parameter [1:0] REFC_RESCF = 2'h0;
    parameter RP_COMP = "FALSE";
    parameter [15:0] RSVD_ATTR0 = 16'h0;
    parameter [15:0] RSVD_ATTR1 = 16'h0;
    parameter [1:0] SREFCK0_SEL = 2'h0;
    parameter [1:0] SREFCK1_SEL = 2'h0;
    parameter [1:0] VCTRL_RESET = 2'h0;
endmodule

(* black_box, dont_touch="true" *)
module xsTEST(
    input [1:0] CLK, LSR,
    input [7:0] I0, I1, I2, I3, I4, I5, BYP, FAN,
    output [7:0] TZ, TQ, TZX)/*synthesis syn_black_box syn_noprune=1*/;
    parameter SETRESET = "SET"; // RESET, fuse mc1_sr
    parameter Z_LUT = "LUT"; // CTRL, fuse mc1_sellut
    parameter TZX_TQTZ = "TZ"; // TQ, fuse mc1_qf
endmodule

(* black_box, dont_touch="true" *)
module xsTAPTEST(input [9:0] TESTIN)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsECC_CEM(
    output CLK,
    output CS,
    output WE,
    output [10:0] ADDR,
    output [15:0] DATA,
    input [15:0] DO
)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsECC_EFB(
    output CLK,
    output CS,
    output WE,
    output [10:0] ADDR,
    output [15:0] DATA,
    input [15:0] DO
)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsECC_CEM_E1(
    output CLK,
    output CS,
    output WE,
    output [15:0] ADDR,
    output [15:0] DATA,
    input [15:0] DO
)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsECC_EFB_E1(
    output CLK,
    output CS,
    output WE,
    output [15:0] ADDR,
    output [15:0] DATA,
    input [15:0] DO
)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL_E1(
    input [4:0] BURSTDET,
    output CLOCKING_GOOD,
    input [4:0] DATAVALID_O,
    output [39:0] DDR3_DM_IN,
    output [4:0] DDR3_DQSOUT_DB0,
    output [4:0] DDR3_DQSOUT_DB1,
    output [4:0] DDR3_DQSOUT_DB2,
    output [4:0] DDR3_DQSOUT_DB3,
    input [319:0] DDR3_READ_DATA_OUT,
    output [319:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [15:0] DDR_ADDR_DC,
    output [15:0] DDR_ADDR_DD,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output [2:0] DDR_BA_DC,
    output [2:0] DDR_BA_DD,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CAS_DC,
    output DDR_CAS_DD,
    output [1:0] DDR_CKE_DA,
    output [1:0] DDR_CKE_DB,
    output [1:0] DDR_CKE_DC,
    output [1:0] DDR_CKE_DD,
    output [1:0] DDR_CS_DA,
    output [1:0] DDR_CS_DB,
    output [1:0] DDR_CS_DC,
    output [1:0] DDR_CS_DD,
    output [1:0] DDR_ODT_DA,
    output [1:0] DDR_ODT_DB,
    output [1:0] DDR_ODT_DC,
    output [1:0] DDR_ODT_DD,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_RAS_DC,
    output DDR_RAS_DD,
    output DDR_WE_DA,
    output DDR_WE_DB,
    output DDR_WE_DC,
    output DDR_WE_DD,
    input DDRDLL_LOCK,
    input [39:0] DDRIN,
    output DLL_FREEZE,
    output DQ_TRI_DA,
    output DQ_TRI_DB,
    output DQ_TRI_DC,
    output DQ_TRI_DD,
    output DQSBUFD_PAUSE,
    output DQSTRI_DA,
    output DQSTRI_DB,
    output DQSTRI_DC,
    output DQSTRI_DD,
    input [39:0] EDGE_MINUS,
    output EDGE_MON_ACK,
    input [39:0] EDGE_PLUS,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input PLL_LOCK,
    output [39:0] RD_DIR_DQ,
    output RD_LOADN_DQ,
    output [39:0] RD_MOVE_DQ,
    input [39:0] RDCFLAG_DQ,
    output RL_ERR,
    output [9:0] RL_MON_DIS,
    input RST_N,
    output [19:0] RT_DQS_READ,
    output RT_ERR,
    output [14:0] RT_RDCLKSEL,
    input SCLK,
    output UDDCNTLN,
    input [30:0] USR_ADDR_0,
    input [30:0] USR_ADDR_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    input [1:0] USR_CMD_CLK,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [2:0] USR_CMD_ID_0,
    input [2:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    input [1:0] USR_DR_CLK,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [4:0] USR_DR_SPACE_0,
    output [4:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    input [1:0] USR_DW_CLK,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [4:0] USR_DW_SPACE_0,
    output [4:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [2:0] USR_READ_CMD_ID_0,
    output [2:0] USR_READ_CMD_ID_1,
    output [319:0] USR_READ_DATA_0,
    output [319:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [319:0] USR_WRITE_DATA_0,
    input [319:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [39:0] USR_WRITE_MASK_0,
    input [39:0] USR_WRITE_MASK_1,
    output WB_ACK_O_CIB,
    //output WB_ACK_O_EFB,
    input [4:0] WB_ADR_I_CIB,
    input WB_CLK_I_CIB,
    input [7:0] WB_DAT_I_CIB,
    output [7:0] WB_DAT_O_CIB,
    input WB_RST_I_CIB,
    input WB_STB_I_CIB,
    input WB_WE_I_CIB,
    output [39:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter [15:0] ADDR_INIT_0 = 16'h0;
    parameter [15:0] ADDR_INIT_1 = 16'h0;
    parameter [15:0] ADDR_INIT_2 = 16'h0;
    parameter [15:0] ADDR_INIT_3 = 16'h0;
    parameter ADDR_MIRROR = "FALSE";
    parameter ADDR_SEQ = "FALSE";
    parameter [3:0] AR_BURST_EN = 4'h0;
    parameter [1:0] BANK_WIDTH = 2'h0;
    parameter [3:0] COL_WIDTH = 4'h0;
    parameter DDR_MODE = "FALSE";
    parameter DLL_FREEZE_EN = "FALSE";
    parameter [2:0] DQS_WIDTH = 3'h0;
    parameter DUAL_RANK = "FALSE";
    parameter EXT_AUTO_REF_EN = "FALSE";
    parameter IDLE_AUTO_REF_EN = "FALSE";
    parameter IDLE_DLL_UPDATE_EN = "FALSE";
    parameter MPR_CALIB = "FALSE";
    parameter [2:0] PARAM_TCKE = 3'h0;
    parameter [2:0] PARAM_TCKESR = 3'h0;
    parameter [5:0] PARAM_TFAW = 6'h0;
    parameter [4:0] PARAM_TMOD = 5'h0;
    parameter [4:0] PARAM_TMRD = 5'h0;
    parameter [2:0] PARAM_TPD = 3'h0;
    parameter [5:0] PARAM_TRAS = 6'h0;
    parameter [5:0] PARAM_TRC = 6'h0;
    parameter [3:0] PARAM_TRCD = 4'h0;
    parameter [16:0] PARAM_TREFI = 17'h0;
    parameter [8:0] PARAM_TRFC = 9'h0;
    parameter [3:0] PARAM_TRP = 4'h0;
    parameter [4:0] PARAM_TRRD = 5'h0;
    parameter [3:0] PARAM_TRTP = 4'h0;
    parameter [4:0] PARAM_TWR = 5'h0;
    parameter [3:0] PARAM_TWTR = 4'h0;
    parameter [4:0] PARAM_TXPDLL = 5'h0;
    parameter [7:0] PARAM_TXPR = 8'h0;
    parameter [10:0] PARAM_TZQINIT = 11'h0;
    parameter [9:0] PARAM_TZQOPER = 10'h0;
    parameter [6:0] PARAM_TZQS = 7'h0;
    parameter PATH_SEL_CIB = "FALSE";
    parameter RDIMM = "FALSE";
    parameter RL_EN = "FALSE";
    parameter [9:0] PARAM_RL_MON_DIS = 10'h0;
    parameter [4:0] ROW_WIDTH = 5'h0;
    parameter RT_EN = "FALSE";
    parameter [7:0] S_RD_0 = 8'h0;
    parameter [7:0] S_RD_1 = 8'h0;
    parameter [7:0] S_RD_2 = 8'h0;
    parameter [7:0] S_RD_3 = 8'h0;
    parameter [7:0] S_RD_4 = 8'h0;
    parameter [7:0] S_WR_0 = 8'h0;
    parameter [7:0] S_WR_1 = 8'h0;
    parameter [7:0] S_WR_2 = 8'h0;
    parameter [7:0] S_WR_3 = 8'h0;
    parameter [7:0] S_WR_4 = 8'h0;
    parameter [4:0] SIGN_RD = 5'h0;
    parameter [4:0] SIGN_WR = 5'h0;
    parameter [3:0] SPD_BIN = 4'h0;
    parameter [39:0] WL_DELAY = 40'h0;
    parameter WL_EN = "FALSE";
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL_E2(
    input [4:0] BURSTDET,
    output CLOCKING_GOOD,
    input [4:0] DATAVALID_O,
    output [39:0] DDR3_DM_IN,
    output [4:0] DDR3_DQSOUT_DB0,
    output [4:0] DDR3_DQSOUT_DB1,
    output [4:0] DDR3_DQSOUT_DB2,
    output [4:0] DDR3_DQSOUT_DB3,
    input [319:0] DDR3_READ_DATA_OUT,
    output [319:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [15:0] DDR_ADDR_DC,
    output [15:0] DDR_ADDR_DD,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output [2:0] DDR_BA_DC,
    output [2:0] DDR_BA_DD,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CAS_DC,
    output DDR_CAS_DD,
    output [1:0] DDR_CKE_DA,
    output [1:0] DDR_CKE_DB,
    output [1:0] DDR_CKE_DC,
    output [1:0] DDR_CKE_DD,
    output [1:0] DDR_CS_DA,
    output [1:0] DDR_CS_DB,
    output [1:0] DDR_CS_DC,
    output [1:0] DDR_CS_DD,
    output [1:0] DDR_ODT_DA,
    output [1:0] DDR_ODT_DB,
    output [1:0] DDR_ODT_DC,
    output [1:0] DDR_ODT_DD,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_RAS_DC,
    output DDR_RAS_DD,
    output DDR_WE_DA,
    output DDR_WE_DB,
    output DDR_WE_DC,
    output DDR_WE_DD,
    input DDRDLL_LOCK,
    input [39:0] DDRIN,
    output DLL_FREEZE,
    output DQ_TRI_DA,
    output DQ_TRI_DB,
    output DQ_TRI_DC,
    output DQ_TRI_DD,
    output DQSBUFD_PAUSE,
    output DQSTRI_DA,
    output DQSTRI_DB,
    output DQSTRI_DC,
    output DQSTRI_DD,
    input [39:0] EDGE_MINUS,
    output EDGE_MON_ACK,
    input [39:0] EDGE_PLUS,
    input EDT_BYPASS,
    input [1:0] EDT_CHANNELS_IN,
    output [1:0] EDT_CHANNELS_OUT,
    input EDT_LOW_POWER_SHIFT_EN,
    input EDT_UPDATE,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input OCC_BYPASS,
    input PLL_LOCK,
    output [39:0] RD_DIR_DQ,
    output RD_LOADN_DQ,
    output [39:0] RD_MOVE_DQ,
    input [39:0] RDCFLAG_DQ,
    output RL_ERR,
    output [9:0] RL_MON_DIS,
    input RST_N,
    output [19:0] RT_DQS_READ,
    output RT_ERR,
    output [19:0] RT_RDCLKSEL,
    input [1:0] S_AXI_ARBURST,
    input [3:0] S_AXI_ARCACHE,
    input [7:0] S_AXI_ARLEN,
    input [0:0] S_AXI_ARLOCK,
    input [2:0] S_AXI_ARPROT,
    input [3:0] S_AXI_ARQOS,
    output S_AXI_ARREADY,
    input [2:0] S_AXI_ARSIZE,
    input [1:0] S_AXI_AWBURST,
    input [3:0] S_AXI_AWCACHE,
    input [7:0] S_AXI_AWLEN,
    input [0:0] S_AXI_AWLOCK,
    input [2:0] S_AXI_AWPROT,
    input [3:0] S_AXI_AWQOS,
    output S_AXI_AWREADY,
    input [2:0] S_AXI_AWSIZE,
    output [2:0] S_AXI_BID,
    input S_AXI_BREADY,
    output [1:0] S_AXI_BRESP,
    output S_AXI_BVALID,
    input S_AXI_RREADY,
    output [1:0] S_AXI_RRESP,
    output S_AXI_WREADY,
    input SCAN_AC_MODE,
    input SCAN_CLK,
    input SCAN_EN,
    input SCAN_MODE,
    input SCAN_RST_N,
    input SCLK,
    output UDDCNTLN,
    input [31:0] USR_ADDR_0,
    input [31:0] USR_ADDR_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    input [1:0] USR_CMD_CLK,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [2:0] USR_CMD_ID_0,
    input [2:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [1:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    input [1:0] USR_DR_CLK,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [4:0] USR_DR_SPACE_0,
    output [4:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    input [1:0] USR_DW_CLK,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [4:0] USR_DW_SPACE_0,
    output [4:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [2:0] USR_READ_CMD_ID_0,
    output [2:0] USR_READ_CMD_ID_1,
    output [319:0] USR_READ_DATA_0,
    output [319:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [319:0] USR_WRITE_DATA_0,
    input [319:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [39:0] USR_WRITE_MASK_0,
    input [39:0] USR_WRITE_MASK_1,
    output WB_ACK_O_CIB,
    input [4:0] WB_ADR_I_CIB,
    input WB_CLK_I_CIB,
    input [7:0] WB_DAT_I_CIB,
    output [7:0] WB_DAT_O_CIB,
    input WB_RST_I_CIB,
    input WB_STB_I_CIB,
    input WB_WE_I_CIB,
    output [44:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter RT_MODE = "FALSE"; //,
    parameter [15:0] ADDR_INIT_0 = 16'h0; //,
    parameter [15:0] ADDR_INIT_1 = 16'h0; //,
    parameter [15:0] ADDR_INIT_2 = 16'h0; //,
    parameter [15:0] ADDR_INIT_3 = 16'h0; //,
    parameter ADDR_MIRROR = "FALSE"; //,
    parameter ADDR_SEQ = "FALSE"; //,
    parameter [3:0] AR_BURST_EN = 4'h0; //,
    parameter [2:0] AXI_ARBIT = 3'h0; //,
    parameter AXI_PORT = "FALSE"; //,
    parameter [1:0] BANK_WIDTH = 2'h0; //,
    parameter [3:0] COL_WIDTH = 4'h0; //,
    parameter DDR_MODE = "FALSE"; //,
    parameter DLL_FREEZE_EN = "FALSE"; //,
    parameter [2:0] DQS_WIDTH = 3'h0; //,
    parameter DUAL_RANK = "FALSE"; //,
    parameter EXT_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_DLL_UPDATE_EN = "FALSE"; //,
    parameter MPR_CALIB = "FALSE"; //,
    parameter [2:0] PARAM_TCKE = 3'h0; //,
    parameter [2:0] PARAM_TCKESR = 3'h0; //,
    parameter [5:0] PARAM_TFAW = 6'h0; //,
    parameter [4:0] PARAM_TMOD = 5'h0; //,
    parameter [4:0] PARAM_TMRD = 5'h0; //,
    parameter [2:0] PARAM_TPD = 3'h0; //,
    parameter [5:0] PARAM_TRAS = 6'h0; //,
    parameter [5:0] PARAM_TRC = 6'h0; //,
    parameter [3:0] PARAM_TRCD = 4'h0; //,
    parameter [16:0] PARAM_TREFI = 17'h0; //,
    parameter [8:0] PARAM_TRFC = 9'h0; //,
    parameter [3:0] PARAM_TRP = 4'h0; //,
    parameter [4:0] PARAM_TRRD = 5'h0; //,
    parameter [3:0] PARAM_TRTP = 4'h0; //,
    parameter [4:0] PARAM_TWR = 5'h0; //,
    parameter [3:0] PARAM_TWTR = 4'h0; //,
    parameter [4:0] PARAM_TXPDLL = 5'h0; //,
    parameter [7:0] PARAM_TXPR = 8'h0; //,
    parameter [10:0] PARAM_TZQINIT = 11'h0; //,
    parameter [9:0] PARAM_TZQOPER = 10'h0; //,
    parameter [6:0] PARAM_TZQS = 7'h0; //,
    parameter PATH_SEL_CIB = "FALSE"; //,
    parameter RDIMM = "FALSE"; //,
    parameter RL_EN = "FALSE"; //,
    parameter [9:0] PARAM_RL_MON_DIS = 10'h0; //,
    parameter [4:0] ROW_WIDTH = 5'h0; //,
    parameter RT_EN = "FALSE"; //,
    parameter [8:0] S_RD_0 = 9'h0; //,
    parameter [8:0] S_RD_1 = 9'h0; //,
    parameter [8:0] S_RD_2 = 9'h0; //,
    parameter [8:0] S_RD_3 = 9'h0; //,
    parameter [8:0] S_RD_4 = 9'h0; //,
    parameter [8:0] S_WR_0 = 9'h0; //,
    parameter [8:0] S_WR_1 = 9'h0; //,
    parameter [8:0] S_WR_2 = 9'h0; //,
    parameter [8:0] S_WR_3 = 9'h0; //,
    parameter [8:0] S_WR_4 = 9'h0; //,
    parameter [4:0] SIGN_RD = 5'h0; //,
    parameter [4:0] SIGN_WR = 5'h0; //,
    parameter [3:0] SPD_BIN = 4'h0; //,
    parameter [44:0] WL_DELAY = 45'h0; //,
    parameter WL_EN = "FALSE"; //,
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL_E3(
    input [4:0] BURSTDET,
    output CLOCKING_GOOD,
    input [4:0] DATAVALID_O,
    output [39:0] DDR3_DM_IN,
    output [4:0] DDR3_DQSOUT_DB0,
    output [4:0] DDR3_DQSOUT_DB1,
    output [4:0] DDR3_DQSOUT_DB2,
    output [4:0] DDR3_DQSOUT_DB3,
    input [319:0] DDR3_READ_DATA_OUT,
    output [319:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [15:0] DDR_ADDR_DC,
    output [15:0] DDR_ADDR_DD,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output [2:0] DDR_BA_DC,
    output [2:0] DDR_BA_DD,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CAS_DC,
    output DDR_CAS_DD,
    output [1:0] DDR_CKE_DA,
    output [1:0] DDR_CKE_DB,
    output [1:0] DDR_CKE_DC,
    output [1:0] DDR_CKE_DD,
    output [1:0] DDR_CS_DA,
    output [1:0] DDR_CS_DB,
    output [1:0] DDR_CS_DC,
    output [1:0] DDR_CS_DD,
    output [1:0] DDR_ODT_DA,
    output [1:0] DDR_ODT_DB,
    output [1:0] DDR_ODT_DC,
    output [1:0] DDR_ODT_DD,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_RAS_DC,
    output DDR_RAS_DD,
    output DDR_WE_DA,
    output DDR_WE_DB,
    output DDR_WE_DC,
    output DDR_WE_DD,
    input DDRDLL_LOCK,
    input [39:0] DDRIN,
    output DLL_FREEZE,
    output DQ_TRI_DA,
    output DQ_TRI_DB,
    output DQ_TRI_DC,
    output DQ_TRI_DD,
    output DQSBUFD_PAUSE,
    output DQSTRI_DA,
    output DQSTRI_DB,
    output DQSTRI_DC,
    output DQSTRI_DD,
    input [39:0] EDGE_MINUS,
    output EDGE_MON_ACK,
    input [39:0] EDGE_PLUS,
    input EDT_BYPASS,
    input [1:0] EDT_CHANNELS_IN,
    output [1:0] EDT_CHANNELS_OUT,
    input EDT_LOW_POWER_SHIFT_EN,
    input EDT_UPDATE,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input OCC_BYPASS,
    input PLL_LOCK,
    output [39:0] RD_DIR_DQ,
    output RD_LOADN_DQ,
    output [39:0] RD_MOVE_DQ,
    input [39:0] RDCFLAG_DQ,
    output RL_ERR,
    output [9:0] RL_MON_DIS,
    input RST_N,
    output [19:0] RT_DQS_READ,
    output RT_ERR,
    output [19:0] RT_RDCLKSEL,
    input [1:0] S_AXI_ARBURST,
    input [3:0] S_AXI_ARCACHE,
    input [7:0] S_AXI_ARLEN,
    input [0:0] S_AXI_ARLOCK,
    input [2:0] S_AXI_ARPROT,
    input [3:0] S_AXI_ARQOS,
    output S_AXI_ARREADY,
    input [2:0] S_AXI_ARSIZE,
    input [1:0] S_AXI_AWBURST,
    input [3:0] S_AXI_AWCACHE,
    input [7:0] S_AXI_AWLEN,
    input [0:0] S_AXI_AWLOCK,
    input [2:0] S_AXI_AWPROT,
    input [3:0] S_AXI_AWQOS,
    output S_AXI_AWREADY,
    input [2:0] S_AXI_AWSIZE,
    output [2:0] S_AXI_BID,
    input S_AXI_BREADY,
    output [1:0] S_AXI_BRESP,
    output S_AXI_BVALID,
    input S_AXI_RREADY,
    output [1:0] S_AXI_RRESP,
    output S_AXI_WREADY,
    input SCAN_AC_MODE,
    input SCAN_CLK,
    input SCAN_EN,
    input SCAN_MODE,
    input SCAN_RST_N,
    input SCLK,
    output UDDCNTLN,
    input [34:0] USR_ADDR_0,
    input [34:0] USR_ADDR_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    input [1:0] USR_CMD_CLK,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [2:0] USR_CMD_ID_0,
    input [2:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    input [1:0] USR_DR_CLK,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [3:0] USR_DR_SPACE_0,
    output [3:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    input [1:0] USR_DW_CLK,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [3:0] USR_DW_SPACE_0,
    output [3:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [2:0] USR_READ_CMD_ID_0,
    output [2:0] USR_READ_CMD_ID_1,
    output [319:0] USR_READ_DATA_0,
    output [319:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [319:0] USR_WRITE_DATA_0,
    input [319:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [39:0] USR_WRITE_MASK_0,
    input [39:0] USR_WRITE_MASK_1,
    output WB_ACK_O_CIB,
    input [4:0] WB_ADR_I_CIB,
    input WB_CLK_I_CIB,
    input [7:0] WB_DAT_I_CIB,
    output [7:0] WB_DAT_O_CIB,
    input WB_RST_I_CIB,
    input WB_STB_I_CIB,
    input WB_WE_I_CIB,
    output [44:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter RT_MODE = "FALSE"; //,
    parameter [15:0] ADDR_INIT_0 = 16'h0; //,
    parameter [15:0] ADDR_INIT_1 = 16'h0; //,
    parameter [15:0] ADDR_INIT_2 = 16'h0; //,
    parameter [15:0] ADDR_INIT_3 = 16'h0; //,
    parameter ADDR_MIRROR = "FALSE"; //,
    parameter ADDR_SEQ = "FALSE"; //,
    parameter [3:0] AR_BURST_EN = 4'h0; //,
    parameter [2:0] AXI_ARBIT = 3'h0; //,
    parameter AXI_PORT = "FALSE"; //,
    parameter [1:0] BANK_WIDTH = 2'h0; //,
    parameter [3:0] COL_WIDTH = 4'h0; //,
    parameter DDR_MODE = "FALSE"; //,
    parameter DLL_FREEZE_EN = "FALSE"; //,
    parameter [2:0] DQS_WIDTH = 3'h0; //,
    parameter DUAL_RANK = "FALSE"; //,
    parameter EXT_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_DLL_UPDATE_EN = "FALSE"; //,
    parameter MPR_CALIB = "FALSE"; //,
    parameter [2:0] PARAM_TCKE = 3'h0; //,
    parameter [2:0] PARAM_TCKESR = 3'h0; //,
    parameter [5:0] PARAM_TFAW = 6'h0; //,
    parameter [4:0] PARAM_TMOD = 5'h0; //,
    parameter [4:0] PARAM_TMRD = 5'h0; //,
    parameter [2:0] PARAM_TPD = 3'h0; //,
    parameter [5:0] PARAM_TRAS = 6'h0; //,
    parameter [5:0] PARAM_TRC = 6'h0; //,
    parameter [3:0] PARAM_TRCD = 4'h0; //,
    parameter [16:0] PARAM_TREFI = 17'h0; //,
    parameter [8:0] PARAM_TRFC = 9'h0; //,
    parameter [3:0] PARAM_TRP = 4'h0; //,
    parameter [4:0] PARAM_TRRD = 5'h0; //,
    parameter [3:0] PARAM_TRTP = 4'h0; //,
    parameter [4:0] PARAM_TWR = 5'h0; //,
    parameter [3:0] PARAM_TWTR = 4'h0; //,
    parameter [4:0] PARAM_TXPDLL = 5'h0; //,
    parameter [7:0] PARAM_TXPR = 8'h0; //,
    parameter [10:0] PARAM_TZQINIT = 11'h0; //,
    parameter [9:0] PARAM_TZQOPER = 10'h0; //,
    parameter [6:0] PARAM_TZQS = 7'h0; //,
    //parameter PATH_SEL_CIB = "FALSE"; //,
    parameter DDR_REORDER = "FALSE"; //,
    parameter RDIMM = "FALSE"; //,
    parameter RL_EN = "FALSE"; //,
    parameter [9:0] PARAM_RL_MON_DIS = 10'h0; //,
    parameter [4:0] ROW_WIDTH = 5'h0; //,
    parameter RT_EN = "FALSE"; //,
    parameter [8:0] S_RD_0 = 9'h0; //,
    parameter [8:0] S_RD_1 = 9'h0; //,
    parameter [8:0] S_RD_2 = 9'h0; //,
    parameter [8:0] S_RD_3 = 9'h0; //,
    parameter [8:0] S_RD_4 = 9'h0; //,
    parameter [8:0] S_WR_0 = 9'h0; //,
    parameter [8:0] S_WR_1 = 9'h0; //,
    parameter [8:0] S_WR_2 = 9'h0; //,
    parameter [8:0] S_WR_3 = 9'h0; //,
    parameter [8:0] S_WR_4 = 9'h0; //,
    parameter [4:0] SIGN_RD = 5'h0; //,
    parameter [4:0] SIGN_WR = 5'h0; //,
    parameter [3:0] SPD_BIN = 4'h0; //,
    parameter [44:0] WL_DELAY = 45'h0; //,
    parameter WL_EN = "FALSE"; //,
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL_E4(
    input [4:0] BURSTDET,
    output CLOCKING_GOOD,
    output [3:0] CORE_CMD,
    output [3:0] CORE_CMD_ID,
    output CORE_CMD_PORT,
    output CORE_CMD_VALID,
    input [4:0] DATAVALID_O,
    output [39:0] DDR3_DM_IN,
    output [4:0] DDR3_DQSOUT_DB0,
    output [4:0] DDR3_DQSOUT_DB1,
    output [4:0] DDR3_DQSOUT_DB2,
    output [4:0] DDR3_DQSOUT_DB3,
    input [319:0] DDR3_READ_DATA_OUT,
    output [319:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [15:0] DDR_ADDR_DC,
    output [15:0] DDR_ADDR_DD,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output [2:0] DDR_BA_DC,
    output [2:0] DDR_BA_DD,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CAS_DC,
    output DDR_CAS_DD,
    output [1:0] DDR_CKE_DA,
    output [1:0] DDR_CKE_DB,
    output [1:0] DDR_CKE_DC,
    output [1:0] DDR_CKE_DD,
    output [1:0] DDR_CS_DA,
    output [1:0] DDR_CS_DB,
    output [1:0] DDR_CS_DC,
    output [1:0] DDR_CS_DD,
    output [1:0] DDR_ODT_DA,
    output [1:0] DDR_ODT_DB,
    output [1:0] DDR_ODT_DC,
    output [1:0] DDR_ODT_DD,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_RAS_DC,
    output DDR_RAS_DD,
    output DDR_WE_DA,
    output DDR_WE_DB,
    output DDR_WE_DC,
    output DDR_WE_DD,
    input DDRDLL_LOCK,
    input [39:0] DDRIN,
    input [6:0] DEBUG_ADDR,
    output [7:0] DEBUG_OUT,
    input DEBUG_RD,
    output DLL_FREEZE,
    output DQ_TRI_DA,
    output DQ_TRI_DB,
    output DQ_TRI_DC,
    output DQ_TRI_DD,
    output DQSBUFD_PAUSE,
    output DQSTRI_DA,
    output DQSTRI_DB,
    output DQSTRI_DC,
    output DQSTRI_DD,
    input [39:0] EDGE_MINUS,
    output EDGE_MON_ACK,
    input [39:0] EDGE_PLUS,
    input EDT_BYPASS,
    input [1:0] EDT_CHANNELS_IN,
    output [1:0] EDT_CHANNELS_OUT,
    input EDT_LOW_POWER_SHIFT_EN,
    input EDT_UPDATE,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    input FIFO_PORT_RST_N,
//    input GLOBAL_RST_N,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input OCC_BYPASS,
    input PLL_LOCK,
    output [39:0] RD_DIR_DQ,
    output RD_LOADN_DQ,
    output [39:0] RD_MOVE_DQ,
    input [39:0] RDCFLAG_DQ,
    output RL_ERR,
    output [9:0] RL_MON_DIS,
    input RST_N,
    output [19:0] RT_DQS_READ,
    output RT_ERR,
    output [19:0] RT_RDCLKSEL,
    input [1:0] S_AXI_ARBURST,
    input [3:0] S_AXI_ARCACHE,
    input [7:0] S_AXI_ARLEN,
    input [0:0] S_AXI_ARLOCK,
    input [2:0] S_AXI_ARPROT,
    input [3:0] S_AXI_ARQOS,
    output S_AXI_ARREADY,
    input [2:0] S_AXI_ARSIZE,
    input [1:0] S_AXI_AWBURST,
    input [3:0] S_AXI_AWCACHE,
    input [7:0] S_AXI_AWLEN,
    input [0:0] S_AXI_AWLOCK,
    input [2:0] S_AXI_AWPROT,
    input [3:0] S_AXI_AWQOS,
    output S_AXI_AWREADY,
    input [2:0] S_AXI_AWSIZE,
    output [3:0] S_AXI_BID,
    input S_AXI_BREADY,
    output [1:0] S_AXI_BRESP,
    output S_AXI_BVALID,
    input S_AXI_RREADY,
    output [1:0] S_AXI_RRESP,
    output S_AXI_WREADY,
    input SCAN_AC_MODE,
    input SCAN_CLK,
    input SCAN_EN,
    input SCAN_MODE,
    input SCAN_RST_N,
    input SCLK,
    output UDDCNTLN,
    input [34:0] USR_ADDR_0,
    input [34:0] USR_ADDR_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    input [1:0] USR_CMD_CLK,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [3:0] USR_CMD_ID_0,
    input [3:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    input [1:0] USR_DR_CLK,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [3:0] USR_DR_SPACE_0,
    output [3:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    input [1:0] USR_DW_CLK,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [3:0] USR_DW_SPACE_0,
    output [3:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [3:0] USR_READ_CMD_ID_0,
    output [3:0] USR_READ_CMD_ID_1,
    output [319:0] USR_READ_DATA_0,
    output [319:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [319:0] USR_WRITE_DATA_0,
    input [319:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [39:0] USR_WRITE_MASK_0,
    input [39:0] USR_WRITE_MASK_1,
    output [44:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter [15:0] ADDR_INIT_0 = 0; //,
    parameter [15:0] ADDR_INIT_1 = 0; //,
    parameter [15:0] ADDR_INIT_2 = 0; //,
    parameter [15:0] ADDR_INIT_3 = 0; //,
    parameter ADDR_MIRROR = "FALSE"; //,
    parameter ADDR_SEQ = "FALSE"; //,
    parameter [3:0] AR_BURST_EN = 0; //,
    parameter [2:0] AXI_ARBIT = 0; //,
    parameter AXI_PORT = "FALSE"; //,
    parameter [1:0] BANK_WIDTH = 0; //,
    parameter [3:0] COL_WIDTH = 0; //,
    parameter DDR_MODE = "FALSE"; //,
    parameter DDR_REORDER = "FALSE"; //,
    parameter DLL_FREEZE_EN = "FALSE"; //,
    parameter [2:0] DQS_WIDTH = 0; //,
    parameter DUAL_RANK = "FALSE"; //,
    parameter EDGE_MONITOR_EN = "FALSE"; //,
    parameter EXT_AUTO_REF_EN = "FALSE"; //,
    parameter FIFO_SINGLE_PORT = "FALSE"; //,
    parameter IDLE_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_DLL_UPDATE_EN = "FALSE"; //,
    parameter MPR_CALIB = "FALSE"; //,
    parameter [2:0] PARAM_TCKE = 0; //,
    parameter [2:0] PARAM_TCKESR = 0; //,
    parameter [5:0] PARAM_TFAW = 0; //,
    parameter [4:0] PARAM_TMOD = 0; //,
    parameter [4:0] PARAM_TMRD = 0; //,
    parameter [2:0] PARAM_TPD = 0; //,
    parameter [5:0] PARAM_TRAS = 0; //,
    parameter [5:0] PARAM_TRC = 0; //,
    parameter [3:0] PARAM_TRCD = 0; //,
    parameter [16:0] PARAM_TREFI = 0; //,
    parameter [8:0] PARAM_TRFC = 0; //,
    parameter [3:0] PARAM_TRP = 0; //,
    parameter [4:0] PARAM_TRRD = 0; //,
    parameter [3:0] PARAM_TRTP = 0; //,
    parameter [4:0] PARAM_TWR = 0; //,
    parameter [3:0] PARAM_TWTR = 0; //,
    parameter [4:0] PARAM_TXPDLL = 0; //,
    parameter [7:0] PARAM_TXPR = 0; //,
    parameter [10:0] PARAM_TZQINIT = 0; //,
    parameter [9:0] PARAM_TZQOPER = 0; //,
    parameter [6:0] PARAM_TZQS = 0; //,
    parameter RDIMM = "FALSE"; //,
    parameter RL_EN = "FALSE"; //,
    parameter [9:0] PARAM_RL_MON_DIS = 0; //,
    parameter [4:0] ROW_WIDTH = 0; //,
    parameter RT_EN = "FALSE"; //,
    parameter RT_MODE = "FALSE"; //,
    parameter [3:0] SPD_BIN = 0; //,
    parameter [44:0] WL_DELAY = 0; //,
    parameter WL_EN = "FALSE"; //,
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL_E5(
    input [4:0] BURSTDET,
    input CA_PARITY_ERR_INJECT,
    output CLOCKING_GOOD,
    output [3:0] CORE_CMD,
    output [3:0] CORE_CMD_ID,
    output CORE_CMD_PORT,
    output CORE_CMD_VALID,
    input CRC_ERR_INJECT,
    input [4:0] DATAVALID_O,
    output [39:0] DDR3_DM_IN,
    output [4:0] DDR3_DQSOUT_DB0,
    output [4:0] DDR3_DQSOUT_DB1,
    output [4:0] DDR3_DQSOUT_DB2,
    output [4:0] DDR3_DQSOUT_DB3,
    input [319:0] DDR3_READ_DATA_OUT,
    output [319:0] DDR3_WR_DATA_IN,
    input [39:0] DDR4_READ_DBI,
    output DDR_ACT_DA,
    output DDR_ACT_DB,
    output DDR_ACT_DC,
    output DDR_ACT_DD,
    output [16:0] DDR_ADDR_DA,
    output [16:0] DDR_ADDR_DB,
    output [16:0] DDR_ADDR_DC,
    output [16:0] DDR_ADDR_DD,
    input DDR_ALERT_N,
    output [3:0] DDR_BA_DA,
    output [3:0] DDR_BA_DB,
    output [3:0] DDR_BA_DC,
    output [3:0] DDR_BA_DD,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CAS_DC,
    output DDR_CAS_DD,
    output [3:0] DDR_CKE_DA,
    output [3:0] DDR_CKE_DB,
    output [3:0] DDR_CKE_DC,
    output [3:0] DDR_CKE_DD,
    output [3:0] DDR_CS_DA,
    output [3:0] DDR_CS_DB,
    output [3:0] DDR_CS_DC,
    output [3:0] DDR_CS_DD,
    output [3:0] DDR_ODT_DA,
    output [3:0] DDR_ODT_DB,
    output [3:0] DDR_ODT_DC,
    output [3:0] DDR_ODT_DD,
    output DDR_PAR_DA,
    output DDR_PAR_DB,
    output DDR_PAR_DC,
    output DDR_PAR_DD,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_RAS_DC,
    output DDR_RAS_DD,
    output DDR_WE_DA,
    output DDR_WE_DB,
    output DDR_WE_DC,
    output DDR_WE_DD,
    input DDRDLL_LOCK,
    input [39:0] DDRIN,
    input [6:0] DEBUG_ADDR,
    output [7:0] DEBUG_OUT,
    input DEBUG_RD,
    output DLL_FREEZE,
    output DQ_TRI_DA,
    output DQ_TRI_DB,
    output DQ_TRI_DC,
    output DQ_TRI_DD,
    output DQSBUFD_PAUSE,
    output DQSTRI_DA,
    output DQSTRI_DB,
    output DQSTRI_DC,
    output DQSTRI_DD,
    input [39:0] EDGE_MINUS,
    output EDGE_MON_ACK,
    input [39:0] EDGE_PLUS,
    input EDT_BYPASS,
    input [1:0] EDT_CHANNELS_IN,
    output [1:0] EDT_CHANNELS_OUT,
    input EDT_LOW_POWER_SHIFT_EN,
    input EDT_UPDATE,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    input FIFO_PORT_RST_N,
//    input GLOBAL_RST_N,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input OCC_BYPASS,
    input PLL_LOCK,
    output [39:0] RD_DIR_DQ,
    output RD_LOADN_DQ,
    output [39:0] RD_MOVE_DQ,
    input [39:0] RDCFLAG_DQ,
    output RL_ERR,
    output [9:0] RL_MON_DIS,
    input RST_N,
    output [19:0] RT_DQS_READ,
    output RT_ERR,
    output [19:0] RT_RDCLKSEL,
    input [1:0] S_AXI_ARBURST,
    input [3:0] S_AXI_ARCACHE,
    input [7:0] S_AXI_ARLEN,
    input [0:0] S_AXI_ARLOCK,
    input [2:0] S_AXI_ARPROT,
    input [3:0] S_AXI_ARQOS,
    output S_AXI_ARREADY,
    input [2:0] S_AXI_ARSIZE,
    input [1:0] S_AXI_AWBURST,
    input [3:0] S_AXI_AWCACHE,
    input [7:0] S_AXI_AWLEN,
    input [0:0] S_AXI_AWLOCK,
    input [2:0] S_AXI_AWPROT,
    input [3:0] S_AXI_AWQOS,
    output S_AXI_AWREADY,
    input [2:0] S_AXI_AWSIZE,
    output [3:0] S_AXI_BID,
    input S_AXI_BREADY,
    output [1:0] S_AXI_BRESP,
    output S_AXI_BVALID,
    input S_AXI_RREADY,
    output [1:0] S_AXI_RRESP,
    output S_AXI_WREADY,
    input SCAN_AC_MODE,
    input SCAN_CLK,
    input SCAN_EN,
    input SCAN_MODE,
    input SCAN_RST_N,
    input SCLK,
    output UDDCNTLN,
    input [37:0] USR_ADDR_0,
    input [37:0] USR_ADDR_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    input [1:0] USR_CMD_CLK,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [3:0] USR_CMD_ID_0,
    input [3:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    input [1:0] USR_DR_CLK,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [3:0] USR_DR_SPACE_0,
    output [3:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    input [1:0] USR_DW_CLK,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [3:0] USR_DW_SPACE_0,
    output [3:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [3:0] USR_READ_CMD_ID_0,
    output [3:0] USR_READ_CMD_ID_1,
    output [319:0] USR_READ_DATA_0,
    output [319:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [319:0] USR_WRITE_DATA_0,
    input [319:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [39:0] USR_WRITE_MASK_0,
    input [39:0] USR_WRITE_MASK_1,
    output [44:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter [15:0] ADDR_INIT_0 = 0; //,
    parameter [15:0] ADDR_INIT_1 = 0; //,
    parameter [15:0] ADDR_INIT_2 = 0; //,
    parameter [15:0] ADDR_INIT_3 = 0; //,
    parameter [15:0] ADDR_INIT_4 = 0; //,
    parameter [15:0] ADDR_INIT_5 = 0; //,
    parameter [15:0] ADDR_INIT_6 = 0; //,
    parameter ADDR_MIRROR = "FALSE"; //,
    parameter [1:0] ADDR_SEQ = 0; //,
    parameter [3:0] AR_BURST_EN = 0; //,
    parameter [2:0] AXI_ARBIT = 0; //,
    parameter AXI_PORT = "FALSE"; //,
    parameter [2:0] BANK_WIDTH = 0; //,
    parameter [3:0] COL_WIDTH = 0; //,
    parameter [1:0] DDR_MODE = 0; //,
    parameter DDR_REORDER = "FALSE"; //,
    parameter DLL_FREEZE_EN = "FALSE"; //,
    parameter [2:0] DQS_WIDTH = 0; //,
    parameter EDGE_MONITOR_EN = "FALSE"; //,
    parameter EXT_AUTO_REF_EN = "FALSE"; //,
    parameter FIFO_SINGLE_PORT = "FALSE"; //,
    parameter IDLE_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_DLL_UPDATE_EN = "FALSE"; //,
    parameter MPR_CALIB = "FALSE"; //,
    parameter [2:0] PARAM_TCKE = 0; //,
    parameter [3:0] PARAM_TCKESR = 0; //,
    parameter [5:0] PARAM_TFAW = 0; //,
    parameter [4:0] PARAM_TMOD = 0; //,
    parameter [4:0] PARAM_TMRD = 0; //,
    parameter [2:0] PARAM_TPD = 0; //,
    parameter [5:0] PARAM_TRAS = 0; //,
    parameter [5:0] PARAM_TRC = 0; //,
    parameter [4:0] PARAM_TRCD = 0; //,
    parameter [16:0] PARAM_TREFI = 0; //,
    parameter [9:0] PARAM_TRFC = 0; //,
    parameter [4:0] PARAM_TRP = 0; //,
    parameter [4:0] PARAM_TRRD = 0; //,
    parameter [3:0] PARAM_TRTP = 0; //,
    parameter [4:0] PARAM_TWR = 0; //,
    parameter [3:0] PARAM_TWTR = 0; //,
    parameter [4:0] PARAM_TXPDLL = 0; //,
    parameter [9:0] PARAM_TXPR = 0; //,
    parameter [10:0] PARAM_TZQINIT = 0; //,
    parameter [9:0] PARAM_TZQOPER = 0; //,
    parameter [7:0] PARAM_TZQS = 0; //,
    parameter [2:0] RANK_NUM = 0; //,
    parameter RDIMM = "FALSE"; //,
    parameter RL_EN = "FALSE"; //,
    parameter [9:0] PARAM_RL_MON_DIS = 0; //,
    parameter [4:0] ROW_WIDTH = 0; //,
    parameter RT_EN = "FALSE"; //,
    parameter RT_MODE = "FALSE"; //,
    parameter [3:0] SPD_BIN = 0; //,
    parameter [4:0] TRRD_L = 0; //,
    parameter [4:0] TWR_CRC_DM = 0; //,
    parameter [3:0] TWTR_CRC_DM_L = 0; //,
    parameter [3:0] TWTR_CRC_DM_S = 0; //,
    parameter [3:0] TWTR_L = 0; //,
    parameter [44:0] WL_DELAY = 0; //,
    parameter WL_EN = "FALSE"; //,
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL_E6(
    output WL_DONE,
    input WL_DONE_SYNC,
    input RL_DONE_SYNC,
    input [4:0] BURSTDET,
    input CA_PARITY_ERR_INJECT,
    output CLOCKING_GOOD,
    output [3:0] CORE_CMD,
    output [3:0] CORE_CMD_ID,
    output CORE_CMD_PORT,
    output CORE_CMD_VALID,
    input CRC_ERR_INJECT,
    input [4:0] DATAVALID_O,
    output [39:0] DDR3_DM_IN,
    output [4:0] DDR3_DQSOUT_DB0,
    output [4:0] DDR3_DQSOUT_DB1,
    output [4:0] DDR3_DQSOUT_DB2,
    output [4:0] DDR3_DQSOUT_DB3,
    input [319:0] DDR3_READ_DATA_OUT,
    output [319:0] DDR3_WR_DATA_IN,
    input [39:0] DDR4_READ_DBI,
    output DDR_ACT_DA,
    output DDR_ACT_DB,
    output DDR_ACT_DC,
    output DDR_ACT_DD,
    output [16:0] DDR_ADDR_DA,
    output [16:0] DDR_ADDR_DB,
    output [16:0] DDR_ADDR_DC,
    output [16:0] DDR_ADDR_DD,
    input DDR_ALERT_N,
    output [3:0] DDR_BA_DA,
    output [3:0] DDR_BA_DB,
    output [3:0] DDR_BA_DC,
    output [3:0] DDR_BA_DD,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CAS_DC,
    output DDR_CAS_DD,
    output [3:0] DDR_CKE_DA,
    output [3:0] DDR_CKE_DB,
    output [3:0] DDR_CKE_DC,
    output [3:0] DDR_CKE_DD,
    output [3:0] DDR_CS_DA,
    output [3:0] DDR_CS_DB,
    output [3:0] DDR_CS_DC,
    output [3:0] DDR_CS_DD,
    output [3:0] DDR_ODT_DA,
    output [3:0] DDR_ODT_DB,
    output [3:0] DDR_ODT_DC,
    output [3:0] DDR_ODT_DD,
    output DDR_PAR_DA,
    output DDR_PAR_DB,
    output DDR_PAR_DC,
    output DDR_PAR_DD,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_RAS_DC,
    output DDR_RAS_DD,
    output DDR_WE_DA,
    output DDR_WE_DB,
    output DDR_WE_DC,
    output DDR_WE_DD,
    input DDRDLL_LOCK,
    input [39:0] DDRIN,
    input [6:0] DEBUG_ADDR,
    output [7:0] DEBUG_OUT,
    input DEBUG_RD,
    output DLL_FREEZE,
    output DQ_TRI_DA,
    output DQ_TRI_DB,
    output DQ_TRI_DC,
    output DQ_TRI_DD,
    output DQSBUFD_PAUSE,
    output DQSTRI_DA,
    output DQSTRI_DB,
    output DQSTRI_DC,
    output DQSTRI_DD,
    input [39:0] EDGE_MINUS,
    output EDGE_MON_ACK,
    input [39:0] EDGE_PLUS,
    input EDT_BYPASS,
    input [1:0] EDT_CHANNELS_IN,
    output [1:0] EDT_CHANNELS_OUT,
    input EDT_LOW_POWER_SHIFT_EN,
    input EDT_UPDATE,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    input FIFO_PORT_RST_N,
//    input GLOBAL_RST_N,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input OCC_BYPASS,
    input PLL_LOCK,
    output [39:0] RD_DIR_DQ,
    output RD_LOADN_DQ,
    output [39:0] RD_MOVE_DQ,
    input [39:0] RDCFLAG_DQ,
    output RL_ERR,
    output [9:0] RL_MON_DIS,
    input RST_N,
    output [19:0] RT_DQS_READ,
    output RT_ERR,
    output [19:0] RT_RDCLKSEL,
    input [1:0] S_AXI_ARBURST,
    input [3:0] S_AXI_ARCACHE,
    input [7:0] S_AXI_ARLEN,
    input [0:0] S_AXI_ARLOCK,
    input [2:0] S_AXI_ARPROT,
    input [3:0] S_AXI_ARQOS,
    output S_AXI_ARREADY,
    input [2:0] S_AXI_ARSIZE,
    input [1:0] S_AXI_AWBURST,
    input [3:0] S_AXI_AWCACHE,
    input [7:0] S_AXI_AWLEN,
    input [0:0] S_AXI_AWLOCK,
    input [2:0] S_AXI_AWPROT,
    input [3:0] S_AXI_AWQOS,
    output S_AXI_AWREADY,
    input [2:0] S_AXI_AWSIZE,
    output [3:0] S_AXI_BID,
    input S_AXI_BREADY,
    output [1:0] S_AXI_BRESP,
    output S_AXI_BVALID,
    input S_AXI_RREADY,
    output [1:0] S_AXI_RRESP,
    output S_AXI_WREADY,
    input SCAN_AC_MODE,
    input SCAN_CLK,
    input SCAN_EN,
    input SCAN_MODE,
    input SCAN_RST_N,
    input SCLK,
    output UDDCNTLN,
    input [37:0] USR_ADDR_0,
    input [37:0] USR_ADDR_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    input [1:0] USR_CMD_CLK,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [3:0] USR_CMD_ID_0,
    input [3:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    input [1:0] USR_DR_CLK,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [3:0] USR_DR_SPACE_0,
    output [3:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    input [1:0] USR_DW_CLK,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [3:0] USR_DW_SPACE_0,
    output [3:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [3:0] USR_READ_CMD_ID_0,
    output [3:0] USR_READ_CMD_ID_1,
    output [319:0] USR_READ_DATA_0,
    output [319:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [319:0] USR_WRITE_DATA_0,
    input [319:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [39:0] USR_WRITE_MASK_0,
    input [39:0] USR_WRITE_MASK_1,
    output [44:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter [15:0] ADDR_INIT_0 = 0; //,
    parameter [15:0] ADDR_INIT_1 = 0; //,
    parameter [15:0] ADDR_INIT_2 = 0; //,
    parameter [15:0] ADDR_INIT_3 = 0; //,
    parameter [15:0] ADDR_INIT_4 = 0; //,
    parameter [15:0] ADDR_INIT_5 = 0; //,
    parameter [15:0] ADDR_INIT_6 = 0; //,
    parameter ADDR_MIRROR = "FALSE"; //,
    parameter [1:0] ADDR_SEQ = 0; //,
    parameter [3:0] AR_BURST_EN = 0; //,
    parameter [2:0] AXI_ARBIT = 0; //,
    parameter AXI_PORT = "FALSE"; //,
    parameter [2:0] BANK_WIDTH = 0; //,
    parameter [3:0] COL_WIDTH = 0; //,
    parameter [1:0] DDR_MODE = 0; //,
    parameter DDR_REORDER = "FALSE"; //,
    parameter DLL_FREEZE_EN = "FALSE"; //,
    parameter [2:0] DQS_WIDTH = 0; //,
    parameter EDGE_MONITOR_EN = "FALSE"; //,
    parameter EXT_AUTO_REF_EN = "FALSE"; //,
    parameter FIFO_SINGLE_PORT = "FALSE"; //,
    parameter IDLE_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_DLL_UPDATE_EN = "FALSE"; //,
    parameter MPR_CALIB = "FALSE"; //,
    parameter [2:0] PARAM_TCKE = 0; //,
    parameter [3:0] PARAM_TCKESR = 0; //,
    parameter [5:0] PARAM_TFAW = 0; //,
    parameter [4:0] PARAM_TMOD = 0; //,
    parameter [4:0] PARAM_TMRD = 0; //,
    parameter [2:0] PARAM_TPD = 0; //,
    parameter [5:0] PARAM_TRAS = 0; //,
    parameter [5:0] PARAM_TRC = 0; //,
    parameter [4:0] PARAM_TRCD = 0; //,
    parameter [16:0] PARAM_TREFI = 0; //,
    parameter [9:0] PARAM_TRFC = 0; //,
    parameter [4:0] PARAM_TRP = 0; //,
    parameter [4:0] PARAM_TRRD = 0; //,
    parameter [3:0] PARAM_TRTP = 0; //,
    parameter [4:0] PARAM_TWR = 0; //,
    parameter [3:0] PARAM_TWTR = 0; //,
    parameter [4:0] PARAM_TXPDLL = 0; //,
    parameter [9:0] PARAM_TXPR = 0; //,
    parameter [10:0] PARAM_TZQINIT = 0; //,
    parameter [9:0] PARAM_TZQOPER = 0; //,
    parameter [7:0] PARAM_TZQS = 0; //,
    parameter [2:0] RANK_NUM = 0; //,
    parameter RDIMM = "FALSE"; //,
    parameter RL_EN = "FALSE"; //,
    parameter [9:0] PARAM_RL_MON_DIS = 0; //,
    parameter [4:0] ROW_WIDTH = 0; //,
    parameter RT_EN = "FALSE"; //,
    parameter RT_MODE = "FALSE"; //,
    parameter [3:0] SPD_BIN = 0; //,
    parameter [4:0] TRRD_L = 0; //,
    parameter [4:0] TWR_CRC_DM = 0; //,
    parameter [3:0] TWTR_CRC_DM_L = 0; //,
    parameter [3:0] TWTR_CRC_DM_S = 0; //,
    parameter [3:0] TWTR_L = 0; //,
    parameter [44:0] WL_DELAY = 0; //,
    parameter WL_EN = "FALSE"; //,
    parameter [1:0] TRAINING_FORMAT = 0; // 420k new
endmodule

(* black_box, dont_touch="true" *)
module xsDDRCTRL_E7(
    output WL_DONE,
    input WL_DONE_SYNC,
    input RL_DONE_SYNC,
    input [4:0] BURSTDET,
    output CLOCKING_GOOD,
    output [3:0] CORE_CMD,
    output [3:0] CORE_CMD_ID,
    output CORE_CMD_PORT,
    output CORE_CMD_VALID,
    input [4:0] DATAVALID_O,
    output [39:0] DDR3_DM_IN,
    output [4:0] DDR3_DQSOUT_DB0,
    output [4:0] DDR3_DQSOUT_DB1,
    output [4:0] DDR3_DQSOUT_DB2,
    output [4:0] DDR3_DQSOUT_DB3,
    input [319:0] DDR3_READ_DATA_OUT,
    output [319:0] DDR3_WR_DATA_IN,
    output [15:0] DDR_ADDR_DA,
    output [15:0] DDR_ADDR_DB,
    output [15:0] DDR_ADDR_DC,
    output [15:0] DDR_ADDR_DD,
    output [2:0] DDR_BA_DA,
    output [2:0] DDR_BA_DB,
    output [2:0] DDR_BA_DC,
    output [2:0] DDR_BA_DD,
    output DDR_CAS_DA,
    output DDR_CAS_DB,
    output DDR_CAS_DC,
    output DDR_CAS_DD,
    output [1:0] DDR_CKE_DA,
    output [1:0] DDR_CKE_DB,
    output [1:0] DDR_CKE_DC,
    output [1:0] DDR_CKE_DD,
    output [1:0] DDR_CS_DA,
    output [1:0] DDR_CS_DB,
    output [1:0] DDR_CS_DC,
    output [1:0] DDR_CS_DD,
    output [1:0] DDR_ODT_DA,
    output [1:0] DDR_ODT_DB,
    output [1:0] DDR_ODT_DC,
    output [1:0] DDR_ODT_DD,
    output DDR_RAS_DA,
    output DDR_RAS_DB,
    output DDR_RAS_DC,
    output DDR_RAS_DD,
    output DDR_WE_DA,
    output DDR_WE_DB,
    output DDR_WE_DC,
    output DDR_WE_DD,
    input DDRDLL_LOCK,
    input [39:0] DDRIN,
    input [6:0] DEBUG_ADDR,
    output [7:0] DEBUG_OUT,
    input DEBUG_RD,
    output DLL_FREEZE,
    output DQ_TRI_DA,
    output DQ_TRI_DB,
    output DQ_TRI_DC,
    output DQ_TRI_DD,
    output DQSBUFD_PAUSE,
    output DQSTRI_DA,
    output DQSTRI_DB,
    output DQSTRI_DC,
    output DQSTRI_DD,
    input [39:0] EDGE_MINUS,
    output EDGE_MON_ACK,
    input [39:0] EDGE_PLUS,
    input EDT_BYPASS,
    input [1:0] EDT_CHANNELS_IN,
    output [1:0] EDT_CHANNELS_OUT,
    input EDT_LOW_POWER_SHIFT_EN,
    input EDT_UPDATE,
    output EM_DDR_RESET_N,
    input EXT_AUTO_REF,
    output EXT_AUTO_REF_ACK,
    input FIFO_PORT_RST_N,
//    input GLOBAL_RST_N,
    output INIT_DONE,
    output INIT_START,
    input MEM_RST_N,
    input OCC_BYPASS,
    input PLL_LOCK,
    output [39:0] RD_DIR_DQ,
    output RD_LOADN_DQ,
    output [39:0] RD_MOVE_DQ,
    input [39:0] RDCFLAG_DQ,
    output RL_ERR,
    output [9:0] RL_MON_DIS,
    input RST_N,
    output [19:0] RT_DQS_READ,
    output RT_ERR,
    output [19:0] RT_RDCLKSEL,
    input [1:0] S_AXI_ARBURST,
    input [3:0] S_AXI_ARCACHE,
    input [7:0] S_AXI_ARLEN,
    input [0:0] S_AXI_ARLOCK,
    input [2:0] S_AXI_ARPROT,
    input [3:0] S_AXI_ARQOS,
    output S_AXI_ARREADY,
    input [2:0] S_AXI_ARSIZE,
    input [1:0] S_AXI_AWBURST,
    input [3:0] S_AXI_AWCACHE,
    input [7:0] S_AXI_AWLEN,
    input [0:0] S_AXI_AWLOCK,
    input [2:0] S_AXI_AWPROT,
    input [3:0] S_AXI_AWQOS,
    output S_AXI_AWREADY,
    input [2:0] S_AXI_AWSIZE,
    output [3:0] S_AXI_BID,
    input S_AXI_BREADY,
    output [1:0] S_AXI_BRESP,
    output S_AXI_BVALID,
    input S_AXI_RREADY,
    output [1:0] S_AXI_RRESP,
    output S_AXI_WREADY,
    input SCAN_AC_MODE,
    input SCAN_CLK,
    input SCAN_EN,
    input SCAN_MODE,
    input SCAN_RST_N,
    input SCLK,
    output UDDCNTLN,
    input [34:0] USR_ADDR_0,
    input [34:0] USR_ADDR_1,
    input [3:0] USR_CMD_0,
    input [3:0] USR_CMD_1,
    input [4:0] USR_CMD_BURST_CNT_0,
    input [4:0] USR_CMD_BURST_CNT_1,
    input [1:0] USR_CMD_CLK,
    output [1:0] USR_CMD_EMPTY,
    output [1:0] USR_CMD_FULL,
    input [3:0] USR_CMD_ID_0,
    input [3:0] USR_CMD_ID_1,
    output [1:0] USR_CMD_OVERFLOW,
    output [3:0] USR_CMD_SPACE_0,
    output [3:0] USR_CMD_SPACE_1,
    output [1:0] USR_CMD_UNDERFLOW,
    input [1:0] USR_CMD_WE,
    input [1:0] USR_DR_CLK,
    output [1:0] USR_DR_EMPTY,
    output [1:0] USR_DR_FULL,
    output [1:0] USR_DR_OVERFLOW,
    input [1:0] USR_DR_RE,
    output [3:0] USR_DR_SPACE_0,
    output [3:0] USR_DR_SPACE_1,
    output [1:0] USR_DR_UNDERFLOW,
    input [1:0] USR_DW_CLK,
    output [1:0] USR_DW_EMPTY,
    output [1:0] USR_DW_ERR,
    output [1:0] USR_DW_FULL,
    output [1:0] USR_DW_OVERFLOW,
    output [3:0] USR_DW_SPACE_0,
    output [3:0] USR_DW_SPACE_1,
    output [1:0] USR_DW_UNDERFLOW,
    input [1:0] USR_DW_WE,
    output [3:0] USR_READ_CMD_ID_0,
    output [3:0] USR_READ_CMD_ID_1,
    output [319:0] USR_READ_DATA_0,
    output [319:0] USR_READ_DATA_1,
    output [1:0] USR_READ_LAST,
    output USR_RL_DONE,
    input USR_RL_EN,
    input [319:0] USR_WRITE_DATA_0,
    input [319:0] USR_WRITE_DATA_1,
    input [1:0] USR_WRITE_LAST,
    input [39:0] USR_WRITE_MASK_0,
    input [39:0] USR_WRITE_MASK_1,
    output [44:0] WL_DYNDELAY,
    output WL_ERR)/*synthesis syn_black_box syn_noprune=1*/;
    parameter [15:0] ADDR_INIT_0 = 0; //,
    parameter [15:0] ADDR_INIT_1 = 0; //,
    parameter [15:0] ADDR_INIT_2 = 0; //,
    parameter [15:0] ADDR_INIT_3 = 0; //,
    parameter ADDR_MIRROR = "FALSE"; //,
    parameter ADDR_SEQ = "FALSE"; //,
    parameter [3:0] AR_BURST_EN = 0; //,
    parameter [2:0] AXI_ARBIT = 0; //,
    parameter AXI_PORT = "FALSE"; //,
    parameter [1:0] BANK_WIDTH = 0; //,
    parameter [3:0] COL_WIDTH = 0; //,
    parameter DDR_MODE = "FALSE"; //,
    parameter DDR_REORDER = "FALSE"; //,
    parameter DLL_FREEZE_EN = "FALSE"; //,
    parameter [2:0] DQS_WIDTH = 0; //,
    parameter DUAL_RANK = "FALSE"; //,
    parameter EDGE_MONITOR_EN = "FALSE"; //,
    parameter EXT_AUTO_REF_EN = "FALSE"; //,
    parameter FIFO_SINGLE_PORT = "FALSE"; //,
    parameter IDLE_AUTO_REF_EN = "FALSE"; //,
    parameter IDLE_DLL_UPDATE_EN = "FALSE"; //,
    parameter MPR_CALIB = "FALSE"; //,
    parameter [2:0] PARAM_TCKE = 0; //,
    parameter [2:0] PARAM_TCKESR = 0; //,
    parameter [5:0] PARAM_TFAW = 0; //,
    parameter [4:0] PARAM_TMOD = 0; //,
    parameter [4:0] PARAM_TMRD = 0; //,
    parameter [2:0] PARAM_TPD = 0; //,
    parameter [5:0] PARAM_TRAS = 0; //,
    parameter [5:0] PARAM_TRC = 0; //,
    parameter [3:0] PARAM_TRCD = 0; //,
    parameter [16:0] PARAM_TREFI = 0; //,
    parameter [8:0] PARAM_TRFC = 0; //,
    parameter [3:0] PARAM_TRP = 0; //,
    parameter [4:0] PARAM_TRRD = 0; //,
    parameter [3:0] PARAM_TRTP = 0; //,
    parameter [4:0] PARAM_TWR = 0; //,
    parameter [3:0] PARAM_TWTR = 0; //,
    parameter [4:0] PARAM_TXPDLL = 0; //,
    parameter [7:0] PARAM_TXPR = 0; //,
    parameter [10:0] PARAM_TZQINIT = 0; //,
    parameter [9:0] PARAM_TZQOPER = 0; //,
    parameter [6:0] PARAM_TZQS = 0; //,
    parameter RDIMM = "FALSE"; //,
    parameter RL_EN = "FALSE"; //,
    parameter [9:0] PARAM_RL_MON_DIS = 0; //,
    parameter [4:0] ROW_WIDTH = 0; //,
    parameter RT_EN = "FALSE"; //,
    parameter RT_MODE = "FALSE"; //,
    parameter [3:0] SPD_BIN = 0; //,
    parameter [44:0] WL_DELAY = 0; //,
    parameter WL_EN = "FALSE"; //,
endmodule

(* black_box, dont_touch="true" *)
module xsCM33(
    // non-cib
    output MTX_CLK,
    input CLK_PAD,
    input PLL_OUT,
    input PLL_USRCLK,
    // cib
    input CIB_CLK,
    input CLK_TREE,
    output CLKOUT,
    output CORECLKEN,
    output COREQACCEPTN,
    output COREQACTIVE,
    output COREQDENY,
    input COREQREQN,
    input CORERET,
    output CPCDP,
    output [7:0] CPENABLED,
    input CPERROR,
    output CPMCR,
    output CPMRC,
    output CPNSATTR,
    input [7:0] CPNSPRESENT,
    output [2:0] CPNUM,
    output [8:0] CPOPC,
    output CPPRIV,
    output [7:0] CPPWRSU,
    input [63:0] CPRDATA,
    input CPREADY,
    output [11:0] CPREGS,
    output CPSIZE,
    input [7:0] CPSPRESENT,
    output CPVALID,
    output [63:0] CPWDATA,
    input CS_TCK,
    input CS_TDI,
    output CS_TRACECLK,
    output [3:0] CS_TRACEDATA,
    input CS_NSRST,
    input CS_NTRST,
    output CURRNS,
    output DBGQACCEPTN,
    output DBGQACTIVE,
    output DBGQDENY,
    input DBGQREQN,
    input DBGRET,
    input [3:0] DMACBREQ,
    output [3:0] DMACCLR,
    input [3:0] DMACLBREQ,
    input [3:0] DMACLSREQ,
    input [3:0] DMACSREQ,
    output [3:0] DMACTC,
    input [15:0] EXTINT,
    input FABRIC_CPU_RSTN,
    input FABRIC_MTX_RSTN,
    output FPDZC,
    output FPIDC,
    output FPIOC,
    output FPIXC,
    output FPOFC,
    output FPUFC,
    output FPUQACCEPTN,
    output FPUQACTIVE,
    output FPUQDENY,
    input FPUQREQN,
    input FPURET,
    input [31:0] INITEXP0HADDR,
    input [2:0] INITEXP0HBURST,
    input INITEXP0HMASTLOCK,
    input [3:0] INITEXP0HPROT,
    output [31:0] INITEXP0HRDATA,
    output INITEXP0HREADY,
    output INITEXP0HRESP,
    input INITEXP0HSEL,
    input [2:0] INITEXP0HSIZE,
    input [1:0] INITEXP0HTRANS,
    input [31:0] INITEXP0HWDATA,
    input INITEXP0HWRITE,
    input [31:0] INITEXP1HADDR,
    input [2:0] INITEXP1HBURST,
    input INITEXP1HMASTLOCK,
    input [3:0] INITEXP1HPROT,
    output [31:0] INITEXP1HRDATA,
    output INITEXP1HREADY,
    output INITEXP1HRESP,
    input INITEXP1HSEL,
    input [2:0] INITEXP1HSIZE,
    input [1:0] INITEXP1HTRANS,
    input [31:0] INITEXP1HWDATA,
    input INITEXP1HWRITE,
    output MTBQACCEPTN,
    output MTBQACTIVE,
    output MTBQDENY,
    input MTBQREQN,
    output PCLK,
    output PCLKEN,
    output QSPICSN,
    input [3:0] QSPIDI,
    output [3:0] QSPIDO,
    output [3:0] QSPIDOEN,
    output QSPISCK,
    output RAMSQACCEPTN,
    output RAMSQACTIVE,
    output RAMSQDENY,
    input RAMSQREQN,
    input RAMSRET,
    input [2:0] REMAP,
    output [31:0] TARGEXP0HADDR,
    output [2:0] TARGEXP0HBURST,
    output TARGEXP0HMASTLOCK,
    output [3:0] TARGEXP0HPROT,
    input [31:0] TARGEXP0HRDATA,
    output TARGEXP0HREADYMUX,
    input TARGEXP0HREADYOUT,
    input TARGEXP0HRESP,
    output TARGEXP0HSEL,
    output [2:0] TARGEXP0HSIZE,
    output [1:0] TARGEXP0HTRANS,
    output [31:0] TARGEXP0HWDATA,
    output TARGEXP0HWRITE,
    output [31:0] TARGEXP1HADDR,
    output [2:0] TARGEXP1HBURST,
    output TARGEXP1HMASTLOCK,
    output [3:0] TARGEXP1HPROT,
    input [31:0] TARGEXP1HRDATA,
    output TARGEXP1HREADYMUX,
    input TARGEXP1HREADYOUT,
    input TARGEXP1HRESP,
    output TARGEXP1HSEL,
    output [2:0] TARGEXP1HSIZE,
    output [1:0] TARGEXP1HTRANS,
    output [31:0] TARGEXP1HWDATA,
    output TARGEXP1HWRITE,
    output TCMCLKEN,
    input DBG_SWDI_TMS,
    output DBG_SWDO,
    output DBG_SWDO_EN,
    input [31:0] IO_EXP_PORT_I,
    output [31:0] IO_EXP_PORT_O_INT,
    output [31:0] IO_EXP_PORT_OEN_INT,
    output TDO_ENABLE,
    output TDO_TMS)/*synthesis syn_black_box syn_noprune=1*/;
    // these 2 parameter not compatible with CM3
    parameter [2:0] CORECLK_SEL = 0; //,
    parameter MTXCLK_SEL = "FALSE"; //,
    parameter [3:0] CFGDTCMSZ = 4'h0; //,
    parameter [11:0] CFGFMADDR = 12'h0; //,
    parameter [3:0] CFGITCMSZ = 4'h0; //,
    parameter [4:0] CFGMEMALIAS = 5'h0; //,
    parameter [7:0] CFGNOCDECP = 8'h0; //,
    parameter CORECLK_EN = "FALSE"; //,
    parameter CORE_SET = "FALSE"; //,
    parameter [51:0] CPU0ECOREVNUM = 52'h0; //,
    parameter INITL1RSTDIS = "FALSE"; //,
    parameter [24:0] INITNSVTOR = 25'h0; //,
    parameter INITQSPIADDRSEL = "FALSE"; //,
    parameter INITQSPISCKMODE = "FALSE"; //,
    parameter INITQSPIXPRALBSIZE = "FALSE"; //,
    parameter [7:0] INITQSPIXPRALTBYTES = 8'h0; //,
    parameter INITQSPIXPRDDRMODE = "FALSE"; //,
    parameter INITQSPIXPREN = "FALSE"; //,
    parameter [4:0] INITQSPIXPRNUMDC = 5'h0; //,
    parameter [1:0] INITQSPIXPRXFERMODE = 2'h0; //,
    parameter [24:0] INITSVTOR = 25'h0; //,
    parameter [1:0] INITTCMEN = 2'h0; //,
    parameter LOCKDTGU = "FALSE"; //,
    parameter LOCKITGU = "FALSE"; //,
    parameter LOCKTCM = "FALSE"; //,
    parameter MPUNSDISABLE = "FALSE"; //,
    parameter MPUSDISABLE = "FALSE"; //,
    parameter [25:0] NSSTCALIB = 26'h0; //,
    parameter NSTCLKEN = "FALSE"; //,
    parameter [2:0] PCLK_DIV = 3'h0; //,
    parameter RSTN_ENABLE = "FALSE"; //,
    parameter SAUDISABLE = "FALSE"; //,
    parameter [25:0] SSTCALIB = 26'h0; //,
    parameter SSTCLKEN = "FALSE"; //,
endmodule

(* black_box, dont_touch="true" *)
module xsSTAR(
    // non-cib
    output MTX_CLK,
    input CLK_PAD,
    input PLL_OUT,
    input PLL_USRCLK,
    // cib
    input CIB_CLK,
    input CLK_TREE,
    output CLKOUT,
    output CORECLKEN,
    output COREQACCEPTN,
    output COREQACTIVE,
    output COREQDENY,
    input COREQREQN,
    input CORERET,
    output CPCDP,
    output [7:0] CPENABLED,
    input CPERROR,
    output CPMCR,
    output CPMRC,
    output CPNSATTR,
    input [7:0] CPNSPRESENT,
    output [2:0] CPNUM,
    output [8:0] CPOPC,
    output CPPRIV,
    output [7:0] CPPWRSU,
    input [63:0] CPRDATA,
    input CPREADY,
    output [11:0] CPREGS,
    output CPSIZE,
    input [7:0] CPSPRESENT,
    output CPVALID,
    output [63:0] CPWDATA,
    input CS_TCK,
    input CS_TDI,
    output CS_TRACECLK,
    output [3:0] CS_TRACEDATA,
    input CS_NSRST,
    input CS_NTRST,
    output CURRNS,
    output DBGQACCEPTN,
    output DBGQACTIVE,
    output DBGQDENY,
    input DBGQREQN,
    input DBGRET,
    input [3:0] DMACBREQ,
    output [3:0] DMACCLR,
    input [3:0] DMACLBREQ,
    input [3:0] DMACLSREQ,
    input [3:0] DMACSREQ,
    output [3:0] DMACTC,
    input [15:0] EXTINT,
    input FABRIC_CPU_RSTN,
    input FABRIC_MTX_RSTN,
    output FPDZC,
    output FPIDC,
    output FPIOC,
    output FPIXC,
    output FPOFC,
    output FPUFC,
    output FPUQACCEPTN,
    output FPUQACTIVE,
    output FPUQDENY,
    input FPUQREQN,
    input FPURET,
    input [31:0] INITEXP0HADDR,
    input [2:0] INITEXP0HBURST,
    input INITEXP0HMASTLOCK,
    input [3:0] INITEXP0HPROT,
    output [31:0] INITEXP0HRDATA,
    output INITEXP0HREADY,
    output INITEXP0HRESP,
    input INITEXP0HSEL,
    input [2:0] INITEXP0HSIZE,
    input [1:0] INITEXP0HTRANS,
    input [31:0] INITEXP0HWDATA,
    input INITEXP0HWRITE,
    input [31:0] INITEXP1HADDR,
    input [2:0] INITEXP1HBURST,
    input INITEXP1HMASTLOCK,
    input [3:0] INITEXP1HPROT,
    output [31:0] INITEXP1HRDATA,
    output INITEXP1HREADY,
    output INITEXP1HRESP,
    input INITEXP1HSEL,
    input [2:0] INITEXP1HSIZE,
    input [1:0] INITEXP1HTRANS,
    input [31:0] INITEXP1HWDATA,
    input INITEXP1HWRITE,
    output MTBQACCEPTN,
    output MTBQACTIVE,
    output MTBQDENY,
    input MTBQREQN,
    output PCLK,
    output PCLKEN,
    output QSPICSN,
    input [3:0] QSPIDI,
    output [3:0] QSPIDO,
    output [3:0] QSPIDOEN,
    output QSPISCK,
    output RAMSQACCEPTN,
    output RAMSQACTIVE,
    output RAMSQDENY,
    input RAMSQREQN,
    input RAMSRET,
    input [2:0] REMAP,
    output [31:0] TARGEXP0HADDR,
    output [2:0] TARGEXP0HBURST,
    output TARGEXP0HMASTLOCK,
    output [3:0] TARGEXP0HPROT,
    input [31:0] TARGEXP0HRDATA,
    output TARGEXP0HREADYMUX,
    input TARGEXP0HREADYOUT,
    input TARGEXP0HRESP,
    output TARGEXP0HSEL,
    output [2:0] TARGEXP0HSIZE,
    output [1:0] TARGEXP0HTRANS,
    output [31:0] TARGEXP0HWDATA,
    output TARGEXP0HWRITE,
    output [31:0] TARGEXP1HADDR,
    output [2:0] TARGEXP1HBURST,
    output TARGEXP1HMASTLOCK,
    output [3:0] TARGEXP1HPROT,
    input [31:0] TARGEXP1HRDATA,
    output TARGEXP1HREADYMUX,
    input TARGEXP1HREADYOUT,
    input TARGEXP1HRESP,
    output TARGEXP1HSEL,
    output [2:0] TARGEXP1HSIZE,
    output [1:0] TARGEXP1HTRANS,
    output [31:0] TARGEXP1HWDATA,
    output TARGEXP1HWRITE,
    output TCMCLKEN,
    input DBG_SWDI_TMS,
    output DBG_SWDO,
    output DBG_SWDO_EN,
    input [31:0] IO_EXP_PORT_I,
    output [31:0] IO_EXP_PORT_O_INT,
    output [31:0] IO_EXP_PORT_OEN_INT,
    output TDO_ENABLE,
    output TDO_TMS)/*synthesis syn_black_box syn_noprune=1*/;
    // these 2 parameter not compatible with CM3
    parameter [2:0] CORECLK_SEL = 0; //,
    parameter MTXCLK_SEL = "FALSE"; //,
    parameter [3:0] CFGDTCMSZ = 4'h0; //,
    parameter [11:0] CFGFMADDR = 12'h0; //,
    parameter [3:0] CFGITCMSZ = 4'h0; //,
    parameter [4:0] CFGMEMALIAS = 5'h0; //,
    parameter [7:0] CFGNOCDECP = 8'h0; //,
    parameter CORECLK_EN = "FALSE"; //,
    parameter CORE_SET = "FALSE"; //,
    parameter [51:0] CPU0ECOREVNUM = 52'h0; //,
    parameter INITL1RSTDIS = "FALSE"; //,
    parameter [24:0] INITNSVTOR = 25'h0; //,
    parameter INITQSPIADDRSEL = "FALSE"; //,
    parameter INITQSPISCKMODE = "FALSE"; //,
    parameter INITQSPIXPRALBSIZE = "FALSE"; //,
    parameter [7:0] INITQSPIXPRALTBYTES = 8'h0; //,
    parameter INITQSPIXPRDDRMODE = "FALSE"; //,
    parameter INITQSPIXPREN = "FALSE"; //,
    parameter [4:0] INITQSPIXPRNUMDC = 5'h0; //,
    parameter [1:0] INITQSPIXPRXFERMODE = 2'h0; //,
    parameter [24:0] INITSVTOR = 25'h0; //,
    parameter [1:0] INITTCMEN = 2'h0; //,
    parameter LOCKDTGU = "FALSE"; //,
    parameter LOCKITGU = "FALSE"; //,
    parameter LOCKTCM = "FALSE"; //,
    parameter MPUNSDISABLE = "FALSE"; //,
    parameter MPUSDISABLE = "FALSE"; //,
    parameter [25:0] NSSTCALIB = 26'h0; //,
    parameter NSTCLKEN = "FALSE"; //,
    parameter [2:0] PCLK_DIV = 3'h0; //,
    parameter RSTN_ENABLE = "FALSE"; //,
    parameter SAUDISABLE = "FALSE"; //,
    parameter [25:0] SSTCALIB = 26'h0; //,
    parameter SSTCLKEN = "FALSE"; //,
endmodule

(* black_box, dont_touch="true" *)
module xsRCLKDIV (CLKI, CDIVO)/*synthesis syn_black_box syn_noprune=1*/;
   input CLKI;
   output CDIVO;
endmodule

(* black_box, dont_touch="true" *)
module xsCFG_PERSIST(input PERSIST_EN)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsDNA_PORT(input CLK, SHIFT, output DOUT)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsISCPU(
    output INIT, DONE,
    input CLK, CSN, RDWR_N,
    input [15:0] DIN,
    output [15:0] DOUT)/*synthesis syn_black_box syn_noprune=1*/;
  parameter SED = "DISABLED";
endmodule

(* black_box, dont_touch="true" *)
module xsPCIE(
    input CFG_CONFIG_SPACE_ENABLE,
    output [2:0] CFG_CURRENT_SPEED,
    input [15:0] CFG_DEV_ID,
    output [1:0] CFG_DPA_SUBSTATE_CHANGE,
    input [7:0] CFG_DS_BUS_NUMBER,
    input [4:0] CFG_DS_DEVICE_NUMBER,
    input [2:0] CFG_DS_FUNCTION_NUMBER,
    input [7:0] CFG_DS_PORT_NUMBER,
    input [63:0] CFG_DSN,
    input CFG_ERR_COR_IN,
    output CFG_ERR_COR_OUT,
    output CFG_ERR_FATAL_OUT,
    output CFG_ERR_NONFATAL_OUT,
    input CFG_ERR_UNCOR_IN,
    output [7:0] CFG_EXT_FUNCTION_NUMBER,
    input [31:0] CFG_EXT_READ_DATA,
    input CFG_EXT_READ_DATA_VALID,
    output CFG_EXT_READ_RECEIVED,
    output [9:0] CFG_EXT_REGISTER_NUMBER,
    output [3:0] CFG_EXT_WRITE_BYTE_ENABLE,
    output [31:0] CFG_EXT_WRITE_DATA,
    output CFG_EXT_WRITE_RECEIVED,
    output [11:0] CFG_FC_CPLD,
    output [7:0] CFG_FC_CPLH,
    output [11:0] CFG_FC_NPD,
    output [7:0] CFG_FC_NPH,
    output [11:0] CFG_FC_PD,
    output [7:0] CFG_FC_PH,
    input [2:0] CFG_FC_SEL,
    input [1:0] CFG_FLR_DONE,
    output [1:0] CFG_FLR_IN_PROCESS,
    output [5:0] CFG_FUNCTION_POWER_STATE,
    output [7:0] CFG_FUNCTION_STATUS,
    input CFG_HOT_RESET_IN,
    output CFG_HOT_RESET_OUT,
    output CFG_INPUT_UPDATE_DONE,
    input CFG_INPUT_UPDATE_REQUEST,
    input [3:0] CFG_INTERRUPT_INT,
    input [2:0] CFG_INTERRUPT_MSI_ATTR,
    output [31:0] CFG_INTERRUPT_MSI_DATA,
    output [1:0] CFG_INTERRUPT_MSI_ENABLE,
    output CFG_INTERRUPT_MSI_FAIL,
    input [2:0] CFG_INTERRUPT_MSI_FUNCTION_NUMBER,
    input [31:0] CFG_INTERRUPT_MSI_INT,
    output CFG_INTERRUPT_MSI_MASK_UPDATE,
    output [5:0] CFG_INTERRUPT_MSI_MMENABLE,
    input [63:0] CFG_INTERRUPT_MSI_PENDING_STATUS,
    input [3:0] CFG_INTERRUPT_MSI_SELECT,
    output CFG_INTERRUPT_MSI_SENT,
    input CFG_INTERRUPT_MSI_TPH_PRESENT,
    input [8:0] CFG_INTERRUPT_MSI_TPH_ST_TAG,
    input [1:0] CFG_INTERRUPT_MSI_TPH_TYPE,
    output [5:0] CFG_INTERRUPT_MSI_VF_ENABLE,
    input [63:0] CFG_INTERRUPT_MSIX_ADDRESS,
    input [31:0] CFG_INTERRUPT_MSIX_DATA,
    output [1:0] CFG_INTERRUPT_MSIX_ENABLE,
    output CFG_INTERRUPT_MSIX_FAIL,
    input CFG_INTERRUPT_MSIX_INT,
    output [1:0] CFG_INTERRUPT_MSIX_MASK,
    output CFG_INTERRUPT_MSIX_SENT,
    output [5:0] CFG_INTERRUPT_MSIX_VF_ENABLE,
    output [5:0] CFG_INTERRUPT_MSIX_VF_MASK,
    input [1:0] CFG_INTERRUPT_PENDING,
    output CFG_INTERRUPT_SENT,
    output CFG_INTERRUPTA_OUTPUT,
    output CFG_INTERRUPTB_OUTPUT,
    output CFG_INTERRUPTC_OUTPUT,
    output CFG_INTERRUPTD_OUTPUT,
    output [1:0] CFG_LINK_POWER_STATE,
    input CFG_LINK_TRAINING_ENABLE,
    output CFG_LOCAL_ERROR,
    output CFG_LTR_ENABLE,
    output [5:0] CFG_LTSSM_STATE,
    output [2:0] CFG_MAX_PAYLOAD,
    output [2:0] CFG_MAX_READ_REQ,
    output CFG_MC_UPDATE_DONE,
    input CFG_MC_UPDATE_REQUEST,
    input [18:0] CFG_MGMT_ADDR,
    input [3:0] CFG_MGMT_BYTE_ENABLE,
    input CFG_MGMT_READ,
    output [31:0] CFG_MGMT_READ_DATA,
    output CFG_MGMT_READ_WRITE_DONE,
    input CFG_MGMT_TYPE1_CFG_REG_ACCESS,
    input CFG_MGMT_WRITE,
    input [31:0] CFG_MGMT_WRITE_DATA,
    output CFG_MSG_RECEIVED,
    output [7:0] CFG_MSG_RECEIVED_DATA,
    output [4:0] CFG_MSG_RECEIVED_TYPE,
    input CFG_MSG_TRANSMIT,
    input [31:0] CFG_MSG_TRANSMIT_DATA,
    output CFG_MSG_TRANSMIT_DONE,
    input [2:0] CFG_MSG_TRANSMIT_TYPE,
    output [3:0] CFG_NEGOTIATED_WIDTH,
    output [1:0] CFG_OBFF_ENABLE,
    input [2:0] CFG_PER_FUNC_STATUS_CONTROL,
    output [15:0] CFG_PER_FUNC_STATUS_DATA,
    input [2:0] CFG_PER_FUNCTION_NUMBER,
    input CFG_PER_FUNCTION_OUTPUT_REQUEST,
    output CFG_PER_FUNCTION_UPDATE_DONE,
    output CFG_PHY_LINK_DOWN,
    output [1:0] CFG_PHY_LINK_STATUS,
    output CFG_PL_STATUS_CHANGE,
    input CFG_POWER_STATE_CHANGE_ACK,
    output CFG_POWER_STATE_CHANGE_INTERRUPT,
    output [1:0] CFG_RCB_STATUS,
    input CFG_REQ_PM_TRANSITION_L23_READY,
    input [7:0] CFG_REV_ID,
    input [15:0] CFG_SUBSYS_ID,
    input [15:0] CFG_SUBSYS_VEND_ID,
    output [2:0] CFG_TPH_FUNCTION_NUM,
    output [1:0] CFG_TPH_REQUESTER_ENABLE,
    output [5:0] CFG_TPH_ST_MODE,
    output [4:0] CFG_TPH_STT_ADDRESS,
    input [31:0] CFG_TPH_STT_READ_DATA,
    input CFG_TPH_STT_READ_DATA_VALID,
    output CFG_TPH_STT_READ_ENABLE,
    output [3:0] CFG_TPH_STT_WRITE_BYTE_VALID,
    output [31:0] CFG_TPH_STT_WRITE_DATA,
    output CFG_TPH_STT_WRITE_ENABLE,
    input [15:0] CFG_VEND_ID,
    input [5:0] CFG_VF_FLR_DONE,
    output [5:0] CFG_VF_FLR_IN_PROCESS,
    output [17:0] CFG_VF_POWER_STATE,
    output [11:0] CFG_VF_STATUS,
    output [5:0] CFG_VF_TPH_REQUESTER_ENABLE,
    output [17:0] CFG_VF_TPH_ST_MODE,
    input CORE_CLK,
    input CORE_CLK_MI_COMPLETION_RAM_L,
//    input CORE_CLK_MI_COMPLETION_RAM_L_R,
    input CORE_CLK_MI_COMPLETION_RAM_U,
//    input CORE_CLK_MI_COMPLETION_RAM_U_R,
    input CORE_CLK_MI_REPLAY_RAM,
//    input CORE_CLK_MI_REPLAY_RAM_R,
    input CORE_CLK_MI_REQUEST_RAM,
//    input CORE_CLK_MI_REQUEST_RAM_R,
//    input CORE_CLK_R,
    output [15:0] DBG_DATA_OUT,
    input [10:0] DRP_ADDR,
    input DRP_CLK,
    input [15:0] DRP_DI,
    output [15:0] DRP_DO,
    input DRP_EN,
    output DRP_RDY,
    input DRP_WE,
    output [255:0] M_AXIS_CQ_TDATA,
    output [7:0] M_AXIS_CQ_TKEEP,
    output M_AXIS_CQ_TLAST,
    input [21:0] M_AXIS_CQ_TREADY,
    output [84:0] M_AXIS_CQ_TUSER,
    output M_AXIS_CQ_TVALID,
    output [255:0] M_AXIS_RC_TDATA,
    output [7:0] M_AXIS_RC_TKEEP,
    output M_AXIS_RC_TLAST,
    input [21:0] M_AXIS_RC_TREADY,
    output [74:0] M_AXIS_RC_TUSER,
    output M_AXIS_RC_TVALID,
    input MGMT_RESET_N,
    input MGMT_STICKY_RESET_N,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_A_L,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_A_U,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_B_L,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_B_U,
    input [143:0] MI_COMPLETION_RAM_READ_DATA,
    output [3:0] MI_COMPLETION_RAM_READ_ENABLE_L,
    output [3:0] MI_COMPLETION_RAM_READ_ENABLE_U,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_A_L,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_A_U,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_B_L,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_B_U,
    output [71:0] MI_COMPLETION_RAM_WRITE_DATA_L,
    output [71:0] MI_COMPLETION_RAM_WRITE_DATA_U,
    output [3:0] MI_COMPLETION_RAM_WRITE_ENABLE_L,
    output [3:0] MI_COMPLETION_RAM_WRITE_ENABLE_U,
    output [8:0] MI_REPLAY_RAM_ADDRESS,
    input [143:0] MI_REPLAY_RAM_READ_DATA,
    output [1:0] MI_REPLAY_RAM_READ_ENABLE,
    output [143:0] MI_REPLAY_RAM_WRITE_DATA,
    output [1:0] MI_REPLAY_RAM_WRITE_ENABLE,
    output [8:0] MI_REQUEST_RAM_READ_ADDRESS_A,
    output [8:0] MI_REQUEST_RAM_READ_ADDRESS_B,
    input [143:0] MI_REQUEST_RAM_READ_DATA,
    output [3:0] MI_REQUEST_RAM_READ_ENABLE,
    output [8:0] MI_REQUEST_RAM_WRITE_ADDRESS_A,
    output [8:0] MI_REQUEST_RAM_WRITE_ADDRESS_B,
    output [143:0] MI_REQUEST_RAM_WRITE_DATA,
    output [3:0] MI_REQUEST_RAM_WRITE_ENABLE,
    input PCIE_CQ_NP_REQ,
    output [5:0] PCIE_CQ_NP_REQ_COUNT,
    output [3:0] PCIE_RQ_SEQ_NUM,
    output PCIE_RQ_SEQ_NUM_VLD,
    output [5:0] PCIE_RQ_TAG,
    output [1:0] PCIE_RQ_TAG_AV,
    output PCIE_RQ_TAG_VLD,
    output [1:0] PCIE_TFC_NPD_AV,
    output [1:0] PCIE_TFC_NPH_AV,
    input PIPE_CLK,
//    input PIPE_CLK_R,
    input [5:0] PIPE_EQ_FS,
    input [5:0] PIPE_EQ_LF,
    input PIPE_RESET_N,
    input [1:0] PIPE_RX0_CHAR_IS_K,
    input [31:0] PIPE_RX0_DATA,
    input PIPE_RX0_DATA_VALID,
    input PIPE_RX0_ELEC_IDLE,
    output [1:0] PIPE_RX0_EQ_CONTROL,
    input PIPE_RX0_EQ_DONE,
    input PIPE_RX0_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX0_EQ_LP_LF_FS,
    input PIPE_RX0_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX0_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX0_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX0_EQ_PRESET,
    input PIPE_RX0_PHY_STATUS,
    output PIPE_RX0_POLARITY,
    input PIPE_RX0_START_BLOCK,
    input [2:0] PIPE_RX0_STATUS,
    input [1:0] PIPE_RX0_SYNC_HEADER,
    input PIPE_RX0_VALID,
    input [1:0] PIPE_RX1_CHAR_IS_K,
    input [31:0] PIPE_RX1_DATA,
    input PIPE_RX1_DATA_VALID,
    input PIPE_RX1_ELEC_IDLE,
    output [1:0] PIPE_RX1_EQ_CONTROL,
    input PIPE_RX1_EQ_DONE,
    input PIPE_RX1_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX1_EQ_LP_LF_FS,
    input PIPE_RX1_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX1_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX1_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX1_EQ_PRESET,
    input PIPE_RX1_PHY_STATUS,
    output PIPE_RX1_POLARITY,
    input PIPE_RX1_START_BLOCK,
    input [2:0] PIPE_RX1_STATUS,
    input [1:0] PIPE_RX1_SYNC_HEADER,
    input PIPE_RX1_VALID,
    input [1:0] PIPE_RX2_CHAR_IS_K,
    input [31:0] PIPE_RX2_DATA,
    input PIPE_RX2_DATA_VALID,
    input PIPE_RX2_ELEC_IDLE,
    output [1:0] PIPE_RX2_EQ_CONTROL,
    input PIPE_RX2_EQ_DONE,
    input PIPE_RX2_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX2_EQ_LP_LF_FS,
    input PIPE_RX2_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX2_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX2_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX2_EQ_PRESET,
    input PIPE_RX2_PHY_STATUS,
    output PIPE_RX2_POLARITY,
    input PIPE_RX2_START_BLOCK,
    input [2:0] PIPE_RX2_STATUS,
    input [1:0] PIPE_RX2_SYNC_HEADER,
    input PIPE_RX2_VALID,
    input [1:0] PIPE_RX3_CHAR_IS_K,
    input [31:0] PIPE_RX3_DATA,
    input PIPE_RX3_DATA_VALID,
    input PIPE_RX3_ELEC_IDLE,
    output [1:0] PIPE_RX3_EQ_CONTROL,
    input PIPE_RX3_EQ_DONE,
    input PIPE_RX3_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX3_EQ_LP_LF_FS,
    input PIPE_RX3_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX3_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX3_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX3_EQ_PRESET,
    input PIPE_RX3_PHY_STATUS,
    output PIPE_RX3_POLARITY,
    input PIPE_RX3_START_BLOCK,
    input [2:0] PIPE_RX3_STATUS,
    input [1:0] PIPE_RX3_SYNC_HEADER,
    input PIPE_RX3_VALID,
    input [1:0] PIPE_RX4_CHAR_IS_K,
    input [31:0] PIPE_RX4_DATA,
    input PIPE_RX4_DATA_VALID,
    input PIPE_RX4_ELEC_IDLE,
    output [1:0] PIPE_RX4_EQ_CONTROL,
    input PIPE_RX4_EQ_DONE,
    input PIPE_RX4_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX4_EQ_LP_LF_FS,
    input PIPE_RX4_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX4_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX4_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX4_EQ_PRESET,
    input PIPE_RX4_PHY_STATUS,
    output PIPE_RX4_POLARITY,
    input PIPE_RX4_START_BLOCK,
    input [2:0] PIPE_RX4_STATUS,
    input [1:0] PIPE_RX4_SYNC_HEADER,
    input PIPE_RX4_VALID,
    input [1:0] PIPE_RX5_CHAR_IS_K,
    input [31:0] PIPE_RX5_DATA,
    input PIPE_RX5_DATA_VALID,
    input PIPE_RX5_ELEC_IDLE,
    output [1:0] PIPE_RX5_EQ_CONTROL,
    input PIPE_RX5_EQ_DONE,
    input PIPE_RX5_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX5_EQ_LP_LF_FS,
    input PIPE_RX5_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX5_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX5_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX5_EQ_PRESET,
    input PIPE_RX5_PHY_STATUS,
    output PIPE_RX5_POLARITY,
    input PIPE_RX5_START_BLOCK,
    input [2:0] PIPE_RX5_STATUS,
    input [1:0] PIPE_RX5_SYNC_HEADER,
    input PIPE_RX5_VALID,
    input [1:0] PIPE_RX6_CHAR_IS_K,
    input [31:0] PIPE_RX6_DATA,
    input PIPE_RX6_DATA_VALID,
    input PIPE_RX6_ELEC_IDLE,
    output [1:0] PIPE_RX6_EQ_CONTROL,
    input PIPE_RX6_EQ_DONE,
    input PIPE_RX6_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX6_EQ_LP_LF_FS,
    input PIPE_RX6_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX6_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX6_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX6_EQ_PRESET,
    input PIPE_RX6_PHY_STATUS,
    output PIPE_RX6_POLARITY,
    input PIPE_RX6_START_BLOCK,
    input [2:0] PIPE_RX6_STATUS,
    input [1:0] PIPE_RX6_SYNC_HEADER,
    input PIPE_RX6_VALID,
    input [1:0] PIPE_RX7_CHAR_IS_K,
    input [31:0] PIPE_RX7_DATA,
    input PIPE_RX7_DATA_VALID,
    input PIPE_RX7_ELEC_IDLE,
    output [1:0] PIPE_RX7_EQ_CONTROL,
    input PIPE_RX7_EQ_DONE,
    input PIPE_RX7_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX7_EQ_LP_LF_FS,
    input PIPE_RX7_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX7_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX7_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX7_EQ_PRESET,
    input PIPE_RX7_PHY_STATUS,
    output PIPE_RX7_POLARITY,
    input PIPE_RX7_START_BLOCK,
    input [2:0] PIPE_RX7_STATUS,
    input [1:0] PIPE_RX7_SYNC_HEADER,
    input PIPE_RX7_VALID,
    output [1:0] PIPE_TX0_CHAR_IS_K,
    output PIPE_TX0_COMPLIANCE,
    output [31:0] PIPE_TX0_DATA,
    output PIPE_TX0_DATA_VALID,
    output PIPE_TX0_ELEC_IDLE,
    input [17:0] PIPE_TX0_EQ_COEFF,
    output [1:0] PIPE_TX0_EQ_CONTROL,
    output [5:0] PIPE_TX0_EQ_DEEMPH,
    input PIPE_TX0_EQ_DONE,
    output [3:0] PIPE_TX0_EQ_PRESET,
    output [1:0] PIPE_TX0_POWERDOWN,
    output PIPE_TX0_START_BLOCK,
    output [1:0] PIPE_TX0_SYNC_HEADER,
    output [1:0] PIPE_TX1_CHAR_IS_K,
    output PIPE_TX1_COMPLIANCE,
    output [31:0] PIPE_TX1_DATA,
    output PIPE_TX1_DATA_VALID,
    output PIPE_TX1_ELEC_IDLE,
    input [17:0] PIPE_TX1_EQ_COEFF,
    output [1:0] PIPE_TX1_EQ_CONTROL,
    output [5:0] PIPE_TX1_EQ_DEEMPH,
    input PIPE_TX1_EQ_DONE,
    output [3:0] PIPE_TX1_EQ_PRESET,
    output [1:0] PIPE_TX1_POWERDOWN,
    output PIPE_TX1_START_BLOCK,
    output [1:0] PIPE_TX1_SYNC_HEADER,
    output [1:0] PIPE_TX2_CHAR_IS_K,
    output PIPE_TX2_COMPLIANCE,
    output [31:0] PIPE_TX2_DATA,
    output PIPE_TX2_DATA_VALID,
    output PIPE_TX2_ELEC_IDLE,
    input [17:0] PIPE_TX2_EQ_COEFF,
    output [1:0] PIPE_TX2_EQ_CONTROL,
    output [5:0] PIPE_TX2_EQ_DEEMPH,
    input PIPE_TX2_EQ_DONE,
    output [3:0] PIPE_TX2_EQ_PRESET,
    output [1:0] PIPE_TX2_POWERDOWN,
    output PIPE_TX2_START_BLOCK,
    output [1:0] PIPE_TX2_SYNC_HEADER,
    output [1:0] PIPE_TX3_CHAR_IS_K,
    output PIPE_TX3_COMPLIANCE,
    output [31:0] PIPE_TX3_DATA,
    output PIPE_TX3_DATA_VALID,
    output PIPE_TX3_ELEC_IDLE,
    input [17:0] PIPE_TX3_EQ_COEFF,
    output [1:0] PIPE_TX3_EQ_CONTROL,
    output [5:0] PIPE_TX3_EQ_DEEMPH,
    input PIPE_TX3_EQ_DONE,
    output [3:0] PIPE_TX3_EQ_PRESET,
    output [1:0] PIPE_TX3_POWERDOWN,
    output PIPE_TX3_START_BLOCK,
    output [1:0] PIPE_TX3_SYNC_HEADER,
    output [1:0] PIPE_TX4_CHAR_IS_K,
    output PIPE_TX4_COMPLIANCE,
    output [31:0] PIPE_TX4_DATA,
    output PIPE_TX4_DATA_VALID,
    output PIPE_TX4_ELEC_IDLE,
    input [17:0] PIPE_TX4_EQ_COEFF,
    output [1:0] PIPE_TX4_EQ_CONTROL,
    output [5:0] PIPE_TX4_EQ_DEEMPH,
    input PIPE_TX4_EQ_DONE,
    output [3:0] PIPE_TX4_EQ_PRESET,
    output [1:0] PIPE_TX4_POWERDOWN,
    output PIPE_TX4_START_BLOCK,
    output [1:0] PIPE_TX4_SYNC_HEADER,
    output [1:0] PIPE_TX5_CHAR_IS_K,
    output PIPE_TX5_COMPLIANCE,
    output [31:0] PIPE_TX5_DATA,
    output PIPE_TX5_DATA_VALID,
    output PIPE_TX5_ELEC_IDLE,
    input [17:0] PIPE_TX5_EQ_COEFF,
    output [1:0] PIPE_TX5_EQ_CONTROL,
    output [5:0] PIPE_TX5_EQ_DEEMPH,
    input PIPE_TX5_EQ_DONE,
    output [3:0] PIPE_TX5_EQ_PRESET,
    output [1:0] PIPE_TX5_POWERDOWN,
    output PIPE_TX5_START_BLOCK,
    output [1:0] PIPE_TX5_SYNC_HEADER,
    output [1:0] PIPE_TX6_CHAR_IS_K,
    output PIPE_TX6_COMPLIANCE,
    output [31:0] PIPE_TX6_DATA,
    output PIPE_TX6_DATA_VALID,
    output PIPE_TX6_ELEC_IDLE,
    input [17:0] PIPE_TX6_EQ_COEFF,
    output [1:0] PIPE_TX6_EQ_CONTROL,
    output [5:0] PIPE_TX6_EQ_DEEMPH,
    input PIPE_TX6_EQ_DONE,
    output [3:0] PIPE_TX6_EQ_PRESET,
    output [1:0] PIPE_TX6_POWERDOWN,
    output PIPE_TX6_START_BLOCK,
    output [1:0] PIPE_TX6_SYNC_HEADER,
    output [1:0] PIPE_TX7_CHAR_IS_K,
    output PIPE_TX7_COMPLIANCE,
    output [31:0] PIPE_TX7_DATA,
    output PIPE_TX7_DATA_VALID,
    output PIPE_TX7_ELEC_IDLE,
    input [17:0] PIPE_TX7_EQ_COEFF,
    output [1:0] PIPE_TX7_EQ_CONTROL,
    output [5:0] PIPE_TX7_EQ_DEEMPH,
    input PIPE_TX7_EQ_DONE,
    output [3:0] PIPE_TX7_EQ_PRESET,
    output [1:0] PIPE_TX7_POWERDOWN,
    output PIPE_TX7_START_BLOCK,
    output [1:0] PIPE_TX7_SYNC_HEADER,
    output PIPE_TX_DEEMPH,
    output [2:0] PIPE_TX_MARGIN,
    output [1:0] PIPE_TX_RATE,
    output PIPE_TX_RCVR_DET,
    output PIPE_TX_RESET,
    output PIPE_TX_SWING,
    input PL_DISABLE_SCRAMBLER,
    output PL_EQ_IN_PROGRESS,
    output [1:0] PL_EQ_PHASE,
    input PL_EQ_RESET_EIEOS_COUNT,
    input PL_GEN3_PCS_DISABLE,
    output [7:0] PL_GEN3_PCS_RXSLIDE,
    input [7:0] PL_GEN3_PCS_RXSYNC_DONE,
    input REC_CLK,
//    input REC_CLK_R,
    input RESET_N,
    input [255:0] S_AXIS_CC_TDATA,
    input [7:0] S_AXIS_CC_TKEEP,
    input S_AXIS_CC_TLAST,
    output [3:0] S_AXIS_CC_TREADY,
    input [32:0] S_AXIS_CC_TUSER,
    input S_AXIS_CC_TVALID,
    input [255:0] S_AXIS_RQ_TDATA,
    input [7:0] S_AXIS_RQ_TKEEP,
    input S_AXIS_RQ_TLAST,
    output [3:0] S_AXIS_RQ_TREADY,
    input [59:0] S_AXIS_RQ_TUSER,
    input S_AXIS_RQ_TVALID,
    input SCANENABLE_N,
    input [24:0] SCANIN,
    input SCANMODE_N,
    output [24:0] SCANOUT,
    input USER_CLK)/*synthesis syn_black_box syn_noprune=1*/;
    parameter ARI_CAP_ENABLE = "FALSE"; //,
    parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_CC_PARITY_CHK = "FALSE"; //,
    parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; //,
    parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h0; //,
    parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; //,
    parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; //,
    parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_RQ_PARITY_CHK = "FALSE"; //,
    parameter [1:0] AXISTEN_IF_WIDTH = 2'h0; //,
    //parameter CORE_CLK_MI_COMPLETION_RAM_L_SEL = "FALSE"; //,
    //parameter CORE_CLK_MI_COMPLETION_RAM_U_SEL = "FALSE"; //,
    //parameter CORE_CLK_MI_REPLAY_RAM_SEL = "FALSE"; //,
    //parameter CORE_CLK_MI_REQUEST_RAM_SEL = "FALSE"; //,
    //parameter CORE_CLK_SEL = "FALSE"; //,
    parameter CRM_CORE_CLK_FREQ_500 = "FALSE"; //,
    parameter [1:0] CRM_USER_CLK_FREQ = 2'h0; //,
    parameter [7:0] DNSTREAM_LINK_NUM = 8'h0; //,
    parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h0; //,
    parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "FALSE"; //,
    parameter [8:0] LL_ACK_TIMEOUT = 9'h0; //,
    parameter LL_ACK_TIMEOUT_EN = "FALSE"; //,
    parameter [1:0] LL_ACK_TIMEOUT_FUNC = 2'h0; //,
    parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [8:0] LL_REPLAY_TIMEOUT = 9'h0; //,
    parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; //,
    parameter [1:0] LL_REPLAY_TIMEOUT_FUNC = 2'h0; //,
    parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0; //,
    parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; //,
    parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; //,
    parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; //,
    parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; //,
    parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h0; //,
    parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h0; //,
    parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [3:0] PF0_ARI_CAP_VER = 4'h0; //,
    parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR5_CONTROL = 3'h0; //,
    parameter [7:0] PF0_BIST_REGISTER = 8'h0; //,
    parameter [7:0] PF0_CAPABILITY_POINTER = 8'h0; //,
    parameter [23:0] PF0_CLASS_CODE = 24'h0; //,
    parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "FALSE"; //,
    parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "FALSE"; //,
    parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "FALSE"; //,
    parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "FALSE"; //,
    parameter PF0_DEV_CAP2_LTR_SUPPORT = "FALSE"; //,
    parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; //,
    parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; //,
    parameter [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 3'h0; //,
    parameter [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 3'h0; //,
    parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "FALSE"; //,
    parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; //,
    parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h0; //,
    parameter [15:0] PF0_DEVICE_ID = 16'h0; //,
    parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h0; //,
    parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "FALSE"; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h0; //,
    parameter [3:0] PF0_DPA_CAP_VER = 4'h0; //,
    parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h0; //,
    parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; //,
    parameter [7:0] PF0_INTERRUPT_LINE = 8'h0; //,
    parameter [2:0] PF0_INTERRUPT_PIN = 3'h0; //,
    parameter [1:0] PF0_LINK_CAP_ASPM_SUPPORT = 2'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 3'h0; //,
    parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE"; //,
    parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h0; //,
    parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h0; //,
    parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h0; //,
    parameter [3:0] PF0_LTR_CAP_VER = 4'h0; //,
    parameter [2:0] PF0_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h0; //,
    parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] PF0_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] PF0_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h0; //,
    parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; //,
    parameter [3:0] PF0_PB_CAP_VER = 4'h0; //,
    parameter [7:0] PF0_PM_CAP_ID = 8'h0; //,
    parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h0; //,
    parameter PF0_PM_CAP_PMESUPPORT_D0 = "FALSE"; //,
    parameter PF0_PM_CAP_PMESUPPORT_D1 = "FALSE"; //,
    parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "FALSE"; //,
    parameter PF0_PM_CAP_SUPP_D1_STATE = "FALSE"; //,
    parameter [2:0] PF0_PM_CAP_VER_ID = 3'h0; //,
    parameter PF0_PM_CSR_NOSOFTRESET = "FALSE"; //,
    parameter PF0_RBAR_CAP_ENABLE = "FALSE"; //,
    parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0; //,
    parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0; //,
    parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0; //,
    parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h0; //,
    parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h0; //,
    parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h0; //,
    parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h0; //,
    parameter [3:0] PF0_RBAR_CAP_VER = 4'h0; //,
    parameter [2:0] PF0_RBAR_NUM = 3'h0; //,
    parameter [7:0] PF0_REVISION_ID = 8'h0; //,
    parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; //,
    parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0; //,
    parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h0; //,
    parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0; //,
    parameter [3:0] PF0_SRIOV_CAP_VER = 4'h0; //,
    parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0; //,
    parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0; //,
    parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h0; //,
    parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0; //,
    parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0; //,
    parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter PF0_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter PF0_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] PF0_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h0; //,
    parameter [3:0] PF0_VC_CAP_VER = 4'h0; //,
    parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; //,
    parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; //,
    parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h0; //,
    parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h0; //,
    parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR5_CONTROL = 3'h0; //,
    parameter [7:0] PF1_BIST_REGISTER = 8'h0; //,
    parameter [7:0] PF1_CAPABILITY_POINTER = 8'h0; //,
    parameter [23:0] PF1_CLASS_CODE = 24'h0; //,
    parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h0; //,
    parameter [15:0] PF1_DEVICE_ID = 16'h0; //,
    parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h0; //,
    parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "FALSE"; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h0; //,
    parameter [3:0] PF1_DPA_CAP_VER = 4'h0; //,
    parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h0; //,
    parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; //,
    parameter [7:0] PF1_INTERRUPT_LINE = 8'h0; //,
    parameter [2:0] PF1_INTERRUPT_PIN = 3'h0; //,
    parameter [2:0] PF1_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h0; //,
    parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] PF1_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] PF1_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h0; //,
    parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; //,
    parameter [3:0] PF1_PB_CAP_VER = 4'h0; //,
    parameter [7:0] PF1_PM_CAP_ID = 8'h0; //,
    parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] PF1_PM_CAP_VER_ID = 3'h0; //,
    parameter PF1_RBAR_CAP_ENABLE = "FALSE"; //,
    parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0; //,
    parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0; //,
    parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0; //,
    parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h0; //,
    parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h0; //,
    parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h0; //,
    parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h0; //,
    parameter [3:0] PF1_RBAR_CAP_VER = 4'h0; //,
    parameter [2:0] PF1_RBAR_NUM = 3'h0; //,
    parameter [7:0] PF1_REVISION_ID = 8'h0; //,
    parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; //,
    parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0; //,
    parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h0; //,
    parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0; //,
    parameter [3:0] PF1_SRIOV_CAP_VER = 4'h0; //,
    parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0; //,
    parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0; //,
    parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h0; //,
    parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0; //,
    parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0; //,
    parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter PF1_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter PF1_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] PF1_TPHR_CAP_VER = 4'h0; //,
    //parameter PIPE_CLK_SEL = "FALSE"; //,
    parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; //,
    parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; //,
    parameter PL_DISABLE_SCRAMBLING = "FALSE"; //,
    parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; //,
    parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; //,
    parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; //,
    parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h0; //,
    parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h0; //,
    parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; //,
    parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; //,
    parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h0; //,
    parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h0; //,
    parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h0; //,
    parameter [7:0] PL_N_FTS_COMCLK_GEN1 = 8'h0; //,
    parameter [7:0] PL_N_FTS_COMCLK_GEN2 = 8'h0; //,
    parameter [7:0] PL_N_FTS_COMCLK_GEN3 = 8'h0; //,
    parameter [7:0] PL_N_FTS_GEN1 = 8'h0; //,
    parameter [7:0] PL_N_FTS_GEN2 = 8'h0; //,
    parameter [7:0] PL_N_FTS_GEN3 = 8'h0; //,
    parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; //,
    parameter PL_UPSTREAM_FACING = "FALSE"; //,
    parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h0; //,
    parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h0; //,
    parameter PM_ENABLE_SLOT_POWER_CAPTURE = "FALSE"; //,
    parameter [31:0] PM_L1_REENTRY_DELAY = 32'h0; //,
    parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h0; //,
    parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0; //,
    //parameter REC_CLK_SEL = "FALSE"; //,
    parameter [0:0] SPARE_BIT0 = 1'h0; //,
    parameter [0:0] SPARE_BIT1 = 1'h0; //,
    parameter [0:0] SPARE_BIT2 = 1'h0; //,
    parameter [0:0] SPARE_BIT3 = 1'h0; //,
    parameter [0:0] SPARE_BIT4 = 1'h0; //,
    parameter [0:0] SPARE_BIT5 = 1'h0; //,
    parameter [0:0] SPARE_BIT6 = 1'h0; //,
    parameter [0:0] SPARE_BIT7 = 1'h0; //,
    parameter [0:0] SPARE_BIT8 = 1'h0; //,
    parameter [7:0] SPARE_BYTE0 = 8'h0; //,
    parameter [7:0] SPARE_BYTE1 = 8'h0; //,
    parameter [7:0] SPARE_BYTE2 = 8'h0; //,
    parameter [7:0] SPARE_BYTE3 = 8'h0; //,
    parameter [31:0] SPARE_WORD0 = 32'h0; //,
    parameter [31:0] SPARE_WORD1 = 32'h0; //,
    parameter [31:0] SPARE_WORD2 = 32'h0; //,
    parameter [31:0] SPARE_WORD3 = 32'h0; //,
    parameter SRIOV_CAP_ENABLE = "FALSE"; //,
    parameter TEST_MODE_PIN_CHAR = "FALSE"; //,
    parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'h0; //,
    parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0; //,
    parameter [11:0] TL_CREDITS_CD = 12'h0; //,
    parameter [7:0] TL_CREDITS_CH = 8'h0; //,
    parameter [11:0] TL_CREDITS_NPD = 12'h0; //,
    parameter [7:0] TL_CREDITS_NPH = 8'h0; //,
    parameter [11:0] TL_CREDITS_PD = 12'h0; //,
    parameter [7:0] TL_CREDITS_PH = 8'h0; //,
    parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "FALSE"; //,
    parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; //,
    parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; //,
    parameter TL_LEGACY_MODE_ENABLE = "FALSE"; //,
    parameter TL_PF_ENABLE_REG = "FALSE"; //,
    parameter TL_TAG_MGMT_ENABLE = "FALSE"; //,
    //parameter USER_CLK_SEL = "FALSE"; //,
    parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [7:0] VF0_CAPABILITY_POINTER = 8'h0; //,
    parameter [2:0] VF0_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF0_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF0_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF0_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF0_PM_CAP_VER_ID = 3'h0; //,
    parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF0_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF0_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF0_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF1_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF1_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF1_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF1_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF1_PM_CAP_VER_ID = 3'h0; //,
    parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF1_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF1_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF1_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF2_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF2_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF2_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF2_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF2_PM_CAP_VER_ID = 3'h0; //,
    parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF2_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF2_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF2_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF3_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF3_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF3_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF3_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF3_PM_CAP_VER_ID = 3'h0; //,
    parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF3_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF3_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF3_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF4_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF4_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF4_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF4_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF4_PM_CAP_VER_ID = 3'h0; //,
    parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF4_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF4_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF4_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF5_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF5_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF5_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF5_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF5_PM_CAP_VER_ID = 3'h0; //,
    parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF5_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF5_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF5_TPHR_CAP_VER = 4'h0; //,
endmodule

(* black_box, dont_touch="true" *)
module xsPCIE_E1(
    // 200k new
    output USER_CLK_O, // to 2 regions clk cmux
    input EDT_BYPASS,
    input [3:0] EDT_CHANNELS_IN,
    output [3:0] EDT_CHANNELS_OUT,
    input EDT_LOW_POWER_SHIFT_EN,
    input EDT_UPDATE,
    input OCC_BYPASS,
    // 200k update scan cib
    input SCAN_AC_MODE,
    input SCAN_CLK,
    input SCAN_EN,
    input SCAN_MODE,
    input SCAN_RST_N,
//    input SCANENABLE_N,
//    input [24:0] SCANIN,
//    input SCANMODE_N,
//    output [24:0] SCANOUT,
    input CFG_CONFIG_SPACE_ENABLE,
    output [2:0] CFG_CURRENT_SPEED,
    input [15:0] CFG_DEV_ID,
    output [1:0] CFG_DPA_SUBSTATE_CHANGE,
    input [7:0] CFG_DS_BUS_NUMBER,
    input [4:0] CFG_DS_DEVICE_NUMBER,
    input [2:0] CFG_DS_FUNCTION_NUMBER,
    input [7:0] CFG_DS_PORT_NUMBER,
    input [63:0] CFG_DSN,
    input CFG_ERR_COR_IN,
    output CFG_ERR_COR_OUT,
    output CFG_ERR_FATAL_OUT,
    output CFG_ERR_NONFATAL_OUT,
    input CFG_ERR_UNCOR_IN,
    output [7:0] CFG_EXT_FUNCTION_NUMBER,
    input [31:0] CFG_EXT_READ_DATA,
    input CFG_EXT_READ_DATA_VALID,
    output CFG_EXT_READ_RECEIVED,
    output [9:0] CFG_EXT_REGISTER_NUMBER,
    output [3:0] CFG_EXT_WRITE_BYTE_ENABLE,
    output [31:0] CFG_EXT_WRITE_DATA,
    output CFG_EXT_WRITE_RECEIVED,
    output [11:0] CFG_FC_CPLD,
    output [7:0] CFG_FC_CPLH,
    output [11:0] CFG_FC_NPD,
    output [7:0] CFG_FC_NPH,
    output [11:0] CFG_FC_PD,
    output [7:0] CFG_FC_PH,
    input [2:0] CFG_FC_SEL,
    input [1:0] CFG_FLR_DONE,
    output [1:0] CFG_FLR_IN_PROCESS,
    output [5:0] CFG_FUNCTION_POWER_STATE,
    output [7:0] CFG_FUNCTION_STATUS,
    input CFG_HOT_RESET_IN,
    output CFG_HOT_RESET_OUT,
    output CFG_INPUT_UPDATE_DONE,
    input CFG_INPUT_UPDATE_REQUEST,
    input [3:0] CFG_INTERRUPT_INT,
    input [2:0] CFG_INTERRUPT_MSI_ATTR,
    output [31:0] CFG_INTERRUPT_MSI_DATA,
    output [1:0] CFG_INTERRUPT_MSI_ENABLE,
    output CFG_INTERRUPT_MSI_FAIL,
    input [2:0] CFG_INTERRUPT_MSI_FUNCTION_NUMBER,
    input [31:0] CFG_INTERRUPT_MSI_INT,
    output CFG_INTERRUPT_MSI_MASK_UPDATE,
    output [5:0] CFG_INTERRUPT_MSI_MMENABLE,
    input [63:0] CFG_INTERRUPT_MSI_PENDING_STATUS,
    input [3:0] CFG_INTERRUPT_MSI_SELECT,
    output CFG_INTERRUPT_MSI_SENT,
    input CFG_INTERRUPT_MSI_TPH_PRESENT,
    input [8:0] CFG_INTERRUPT_MSI_TPH_ST_TAG,
    input [1:0] CFG_INTERRUPT_MSI_TPH_TYPE,
    output [5:0] CFG_INTERRUPT_MSI_VF_ENABLE,
    input [63:0] CFG_INTERRUPT_MSIX_ADDRESS,
    input [31:0] CFG_INTERRUPT_MSIX_DATA,
    output [1:0] CFG_INTERRUPT_MSIX_ENABLE,
    output CFG_INTERRUPT_MSIX_FAIL,
    input CFG_INTERRUPT_MSIX_INT,
    output [1:0] CFG_INTERRUPT_MSIX_MASK,
    output CFG_INTERRUPT_MSIX_SENT,
    output [5:0] CFG_INTERRUPT_MSIX_VF_ENABLE,
    output [5:0] CFG_INTERRUPT_MSIX_VF_MASK,
    input [1:0] CFG_INTERRUPT_PENDING,
    output CFG_INTERRUPT_SENT,
    output CFG_INTERRUPTA_OUTPUT,
    output CFG_INTERRUPTB_OUTPUT,
    output CFG_INTERRUPTC_OUTPUT,
    output CFG_INTERRUPTD_OUTPUT,
    output [1:0] CFG_LINK_POWER_STATE,
    input CFG_LINK_TRAINING_ENABLE,
    output CFG_LOCAL_ERROR,
    output CFG_LTR_ENABLE,
    output [5:0] CFG_LTSSM_STATE,
    output [2:0] CFG_MAX_PAYLOAD,
    output [2:0] CFG_MAX_READ_REQ,
    output CFG_MC_UPDATE_DONE,
    input CFG_MC_UPDATE_REQUEST,
    input [18:0] CFG_MGMT_ADDR,
    input [3:0] CFG_MGMT_BYTE_ENABLE,
    input CFG_MGMT_READ,
    output [31:0] CFG_MGMT_READ_DATA,
    output CFG_MGMT_READ_WRITE_DONE,
    input CFG_MGMT_TYPE1_CFG_REG_ACCESS,
    input CFG_MGMT_WRITE,
    input [31:0] CFG_MGMT_WRITE_DATA,
    output CFG_MSG_RECEIVED,
    output [7:0] CFG_MSG_RECEIVED_DATA,
    output [4:0] CFG_MSG_RECEIVED_TYPE,
    input CFG_MSG_TRANSMIT,
    input [31:0] CFG_MSG_TRANSMIT_DATA,
    output CFG_MSG_TRANSMIT_DONE,
    input [2:0] CFG_MSG_TRANSMIT_TYPE,
    output [3:0] CFG_NEGOTIATED_WIDTH,
    output [1:0] CFG_OBFF_ENABLE,
    input [2:0] CFG_PER_FUNC_STATUS_CONTROL,
    output [15:0] CFG_PER_FUNC_STATUS_DATA,
    input [2:0] CFG_PER_FUNCTION_NUMBER,
    input CFG_PER_FUNCTION_OUTPUT_REQUEST,
    output CFG_PER_FUNCTION_UPDATE_DONE,
    output CFG_PHY_LINK_DOWN,
    output [1:0] CFG_PHY_LINK_STATUS,
    output CFG_PL_STATUS_CHANGE,
    input CFG_POWER_STATE_CHANGE_ACK,
    output CFG_POWER_STATE_CHANGE_INTERRUPT,
    output [1:0] CFG_RCB_STATUS,
    input CFG_REQ_PM_TRANSITION_L23_READY,
    input [7:0] CFG_REV_ID,
    input [15:0] CFG_SUBSYS_ID,
    input [15:0] CFG_SUBSYS_VEND_ID,
    output [2:0] CFG_TPH_FUNCTION_NUM,
    output [1:0] CFG_TPH_REQUESTER_ENABLE,
    output [5:0] CFG_TPH_ST_MODE,
    output [4:0] CFG_TPH_STT_ADDRESS,
    input [31:0] CFG_TPH_STT_READ_DATA,
    input CFG_TPH_STT_READ_DATA_VALID,
    output CFG_TPH_STT_READ_ENABLE,
    output [3:0] CFG_TPH_STT_WRITE_BYTE_VALID,
    output [31:0] CFG_TPH_STT_WRITE_DATA,
    output CFG_TPH_STT_WRITE_ENABLE,
    input [15:0] CFG_VEND_ID,
    input [5:0] CFG_VF_FLR_DONE,
    output [5:0] CFG_VF_FLR_IN_PROCESS,
    output [17:0] CFG_VF_POWER_STATE,
    output [11:0] CFG_VF_STATUS,
    output [5:0] CFG_VF_TPH_REQUESTER_ENABLE,
    output [17:0] CFG_VF_TPH_ST_MODE,
    input CORE_CLK,
    input CORE_CLK_MI_COMPLETION_RAM_L,
    input CORE_CLK_MI_COMPLETION_RAM_U,
    input CORE_CLK_MI_REPLAY_RAM,
    input CORE_CLK_MI_REQUEST_RAM,
    output [15:0] DBG_DATA_OUT,
    input [10:0] DRP_ADDR,
    input DRP_CLK,
    input [15:0] DRP_DI,
    output [15:0] DRP_DO,
    input DRP_EN,
    output DRP_RDY,
    input DRP_WE,
    output [255:0] M_AXIS_CQ_TDATA,
    output [7:0] M_AXIS_CQ_TKEEP,
    output M_AXIS_CQ_TLAST,
    input [21:0] M_AXIS_CQ_TREADY,
    output [84:0] M_AXIS_CQ_TUSER,
    output M_AXIS_CQ_TVALID,
    output [255:0] M_AXIS_RC_TDATA,
    output [7:0] M_AXIS_RC_TKEEP,
    output M_AXIS_RC_TLAST,
    input [21:0] M_AXIS_RC_TREADY,
    output [74:0] M_AXIS_RC_TUSER,
    output M_AXIS_RC_TVALID,
    input MGMT_RESET_N,
    input MGMT_STICKY_RESET_N,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_A_L,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_A_U,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_B_L,
    output [9:0] MI_COMPLETION_RAM_READ_ADDRESS_B_U,
    input [143:0] MI_COMPLETION_RAM_READ_DATA,
    output [3:0] MI_COMPLETION_RAM_READ_ENABLE_L,
    output [3:0] MI_COMPLETION_RAM_READ_ENABLE_U,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_A_L,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_A_U,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_B_L,
    output [9:0] MI_COMPLETION_RAM_WRITE_ADDRESS_B_U,
    output [71:0] MI_COMPLETION_RAM_WRITE_DATA_L,
    output [71:0] MI_COMPLETION_RAM_WRITE_DATA_U,
    output [3:0] MI_COMPLETION_RAM_WRITE_ENABLE_L,
    output [3:0] MI_COMPLETION_RAM_WRITE_ENABLE_U,
    output [8:0] MI_REPLAY_RAM_ADDRESS,
    input [143:0] MI_REPLAY_RAM_READ_DATA,
    output [1:0] MI_REPLAY_RAM_READ_ENABLE,
    output [143:0] MI_REPLAY_RAM_WRITE_DATA,
    output [1:0] MI_REPLAY_RAM_WRITE_ENABLE,
    output [8:0] MI_REQUEST_RAM_READ_ADDRESS_A,
    output [8:0] MI_REQUEST_RAM_READ_ADDRESS_B,
    input [143:0] MI_REQUEST_RAM_READ_DATA,
    output [3:0] MI_REQUEST_RAM_READ_ENABLE,
    output [8:0] MI_REQUEST_RAM_WRITE_ADDRESS_A,
    output [8:0] MI_REQUEST_RAM_WRITE_ADDRESS_B,
    output [143:0] MI_REQUEST_RAM_WRITE_DATA,
    output [3:0] MI_REQUEST_RAM_WRITE_ENABLE,
    input PCIE_CQ_NP_REQ,
    output [5:0] PCIE_CQ_NP_REQ_COUNT,
    output [3:0] PCIE_RQ_SEQ_NUM,
    output PCIE_RQ_SEQ_NUM_VLD,
    output [5:0] PCIE_RQ_TAG,
    output [1:0] PCIE_RQ_TAG_AV,
    output PCIE_RQ_TAG_VLD,
    output [1:0] PCIE_TFC_NPD_AV,
    output [1:0] PCIE_TFC_NPH_AV,
    input PIPE_CLK,
    input [5:0] PIPE_EQ_FS,
    input [5:0] PIPE_EQ_LF,
    input PIPE_RESET_N,
    input [1:0] PIPE_RX0_CHAR_IS_K,
    input [31:0] PIPE_RX0_DATA,
    input PIPE_RX0_DATA_VALID,
    input PIPE_RX0_ELEC_IDLE,
    output [1:0] PIPE_RX0_EQ_CONTROL,
    input PIPE_RX0_EQ_DONE,
    input PIPE_RX0_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX0_EQ_LP_LF_FS,
    input PIPE_RX0_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX0_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX0_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX0_EQ_PRESET,
    input PIPE_RX0_PHY_STATUS,
    output PIPE_RX0_POLARITY,
    input PIPE_RX0_START_BLOCK,
    input [2:0] PIPE_RX0_STATUS,
    input [1:0] PIPE_RX0_SYNC_HEADER,
    input PIPE_RX0_VALID,
    input [1:0] PIPE_RX1_CHAR_IS_K,
    input [31:0] PIPE_RX1_DATA,
    input PIPE_RX1_DATA_VALID,
    input PIPE_RX1_ELEC_IDLE,
    output [1:0] PIPE_RX1_EQ_CONTROL,
    input PIPE_RX1_EQ_DONE,
    input PIPE_RX1_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX1_EQ_LP_LF_FS,
    input PIPE_RX1_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX1_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX1_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX1_EQ_PRESET,
    input PIPE_RX1_PHY_STATUS,
    output PIPE_RX1_POLARITY,
    input PIPE_RX1_START_BLOCK,
    input [2:0] PIPE_RX1_STATUS,
    input [1:0] PIPE_RX1_SYNC_HEADER,
    input PIPE_RX1_VALID,
    input [1:0] PIPE_RX2_CHAR_IS_K,
    input [31:0] PIPE_RX2_DATA,
    input PIPE_RX2_DATA_VALID,
    input PIPE_RX2_ELEC_IDLE,
    output [1:0] PIPE_RX2_EQ_CONTROL,
    input PIPE_RX2_EQ_DONE,
    input PIPE_RX2_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX2_EQ_LP_LF_FS,
    input PIPE_RX2_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX2_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX2_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX2_EQ_PRESET,
    input PIPE_RX2_PHY_STATUS,
    output PIPE_RX2_POLARITY,
    input PIPE_RX2_START_BLOCK,
    input [2:0] PIPE_RX2_STATUS,
    input [1:0] PIPE_RX2_SYNC_HEADER,
    input PIPE_RX2_VALID,
    input [1:0] PIPE_RX3_CHAR_IS_K,
    input [31:0] PIPE_RX3_DATA,
    input PIPE_RX3_DATA_VALID,
    input PIPE_RX3_ELEC_IDLE,
    output [1:0] PIPE_RX3_EQ_CONTROL,
    input PIPE_RX3_EQ_DONE,
    input PIPE_RX3_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX3_EQ_LP_LF_FS,
    input PIPE_RX3_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX3_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX3_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX3_EQ_PRESET,
    input PIPE_RX3_PHY_STATUS,
    output PIPE_RX3_POLARITY,
    input PIPE_RX3_START_BLOCK,
    input [2:0] PIPE_RX3_STATUS,
    input [1:0] PIPE_RX3_SYNC_HEADER,
    input PIPE_RX3_VALID,
    input [1:0] PIPE_RX4_CHAR_IS_K,
    input [31:0] PIPE_RX4_DATA,
    input PIPE_RX4_DATA_VALID,
    input PIPE_RX4_ELEC_IDLE,
    output [1:0] PIPE_RX4_EQ_CONTROL,
    input PIPE_RX4_EQ_DONE,
    input PIPE_RX4_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX4_EQ_LP_LF_FS,
    input PIPE_RX4_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX4_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX4_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX4_EQ_PRESET,
    input PIPE_RX4_PHY_STATUS,
    output PIPE_RX4_POLARITY,
    input PIPE_RX4_START_BLOCK,
    input [2:0] PIPE_RX4_STATUS,
    input [1:0] PIPE_RX4_SYNC_HEADER,
    input PIPE_RX4_VALID,
    input [1:0] PIPE_RX5_CHAR_IS_K,
    input [31:0] PIPE_RX5_DATA,
    input PIPE_RX5_DATA_VALID,
    input PIPE_RX5_ELEC_IDLE,
    output [1:0] PIPE_RX5_EQ_CONTROL,
    input PIPE_RX5_EQ_DONE,
    input PIPE_RX5_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX5_EQ_LP_LF_FS,
    input PIPE_RX5_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX5_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX5_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX5_EQ_PRESET,
    input PIPE_RX5_PHY_STATUS,
    output PIPE_RX5_POLARITY,
    input PIPE_RX5_START_BLOCK,
    input [2:0] PIPE_RX5_STATUS,
    input [1:0] PIPE_RX5_SYNC_HEADER,
    input PIPE_RX5_VALID,
    input [1:0] PIPE_RX6_CHAR_IS_K,
    input [31:0] PIPE_RX6_DATA,
    input PIPE_RX6_DATA_VALID,
    input PIPE_RX6_ELEC_IDLE,
    output [1:0] PIPE_RX6_EQ_CONTROL,
    input PIPE_RX6_EQ_DONE,
    input PIPE_RX6_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX6_EQ_LP_LF_FS,
    input PIPE_RX6_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX6_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX6_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX6_EQ_PRESET,
    input PIPE_RX6_PHY_STATUS,
    output PIPE_RX6_POLARITY,
    input PIPE_RX6_START_BLOCK,
    input [2:0] PIPE_RX6_STATUS,
    input [1:0] PIPE_RX6_SYNC_HEADER,
    input PIPE_RX6_VALID,
    input [1:0] PIPE_RX7_CHAR_IS_K,
    input [31:0] PIPE_RX7_DATA,
    input PIPE_RX7_DATA_VALID,
    input PIPE_RX7_ELEC_IDLE,
    output [1:0] PIPE_RX7_EQ_CONTROL,
    input PIPE_RX7_EQ_DONE,
    input PIPE_RX7_EQ_LP_ADAPT_DONE,
    output [5:0] PIPE_RX7_EQ_LP_LF_FS,
    input PIPE_RX7_EQ_LP_LF_FS_SEL,
    input [17:0] PIPE_RX7_EQ_LP_NEW_TX_COEFF_OR_PRESET,
    output [3:0] PIPE_RX7_EQ_LP_TX_PRESET,
    output [2:0] PIPE_RX7_EQ_PRESET,
    input PIPE_RX7_PHY_STATUS,
    output PIPE_RX7_POLARITY,
    input PIPE_RX7_START_BLOCK,
    input [2:0] PIPE_RX7_STATUS,
    input [1:0] PIPE_RX7_SYNC_HEADER,
    input PIPE_RX7_VALID,
    output [1:0] PIPE_TX0_CHAR_IS_K,
    output PIPE_TX0_COMPLIANCE,
    output [31:0] PIPE_TX0_DATA,
    output PIPE_TX0_DATA_VALID,
    output PIPE_TX0_ELEC_IDLE,
    input [17:0] PIPE_TX0_EQ_COEFF,
    output [1:0] PIPE_TX0_EQ_CONTROL,
    output [5:0] PIPE_TX0_EQ_DEEMPH,
    input PIPE_TX0_EQ_DONE,
    output [3:0] PIPE_TX0_EQ_PRESET,
    output [1:0] PIPE_TX0_POWERDOWN,
    output PIPE_TX0_START_BLOCK,
    output [1:0] PIPE_TX0_SYNC_HEADER,
    output [1:0] PIPE_TX1_CHAR_IS_K,
    output PIPE_TX1_COMPLIANCE,
    output [31:0] PIPE_TX1_DATA,
    output PIPE_TX1_DATA_VALID,
    output PIPE_TX1_ELEC_IDLE,
    input [17:0] PIPE_TX1_EQ_COEFF,
    output [1:0] PIPE_TX1_EQ_CONTROL,
    output [5:0] PIPE_TX1_EQ_DEEMPH,
    input PIPE_TX1_EQ_DONE,
    output [3:0] PIPE_TX1_EQ_PRESET,
    output [1:0] PIPE_TX1_POWERDOWN,
    output PIPE_TX1_START_BLOCK,
    output [1:0] PIPE_TX1_SYNC_HEADER,
    output [1:0] PIPE_TX2_CHAR_IS_K,
    output PIPE_TX2_COMPLIANCE,
    output [31:0] PIPE_TX2_DATA,
    output PIPE_TX2_DATA_VALID,
    output PIPE_TX2_ELEC_IDLE,
    input [17:0] PIPE_TX2_EQ_COEFF,
    output [1:0] PIPE_TX2_EQ_CONTROL,
    output [5:0] PIPE_TX2_EQ_DEEMPH,
    input PIPE_TX2_EQ_DONE,
    output [3:0] PIPE_TX2_EQ_PRESET,
    output [1:0] PIPE_TX2_POWERDOWN,
    output PIPE_TX2_START_BLOCK,
    output [1:0] PIPE_TX2_SYNC_HEADER,
    output [1:0] PIPE_TX3_CHAR_IS_K,
    output PIPE_TX3_COMPLIANCE,
    output [31:0] PIPE_TX3_DATA,
    output PIPE_TX3_DATA_VALID,
    output PIPE_TX3_ELEC_IDLE,
    input [17:0] PIPE_TX3_EQ_COEFF,
    output [1:0] PIPE_TX3_EQ_CONTROL,
    output [5:0] PIPE_TX3_EQ_DEEMPH,
    input PIPE_TX3_EQ_DONE,
    output [3:0] PIPE_TX3_EQ_PRESET,
    output [1:0] PIPE_TX3_POWERDOWN,
    output PIPE_TX3_START_BLOCK,
    output [1:0] PIPE_TX3_SYNC_HEADER,
    output [1:0] PIPE_TX4_CHAR_IS_K,
    output PIPE_TX4_COMPLIANCE,
    output [31:0] PIPE_TX4_DATA,
    output PIPE_TX4_DATA_VALID,
    output PIPE_TX4_ELEC_IDLE,
    input [17:0] PIPE_TX4_EQ_COEFF,
    output [1:0] PIPE_TX4_EQ_CONTROL,
    output [5:0] PIPE_TX4_EQ_DEEMPH,
    input PIPE_TX4_EQ_DONE,
    output [3:0] PIPE_TX4_EQ_PRESET,
    output [1:0] PIPE_TX4_POWERDOWN,
    output PIPE_TX4_START_BLOCK,
    output [1:0] PIPE_TX4_SYNC_HEADER,
    output [1:0] PIPE_TX5_CHAR_IS_K,
    output PIPE_TX5_COMPLIANCE,
    output [31:0] PIPE_TX5_DATA,
    output PIPE_TX5_DATA_VALID,
    output PIPE_TX5_ELEC_IDLE,
    input [17:0] PIPE_TX5_EQ_COEFF,
    output [1:0] PIPE_TX5_EQ_CONTROL,
    output [5:0] PIPE_TX5_EQ_DEEMPH,
    input PIPE_TX5_EQ_DONE,
    output [3:0] PIPE_TX5_EQ_PRESET,
    output [1:0] PIPE_TX5_POWERDOWN,
    output PIPE_TX5_START_BLOCK,
    output [1:0] PIPE_TX5_SYNC_HEADER,
    output [1:0] PIPE_TX6_CHAR_IS_K,
    output PIPE_TX6_COMPLIANCE,
    output [31:0] PIPE_TX6_DATA,
    output PIPE_TX6_DATA_VALID,
    output PIPE_TX6_ELEC_IDLE,
    input [17:0] PIPE_TX6_EQ_COEFF,
    output [1:0] PIPE_TX6_EQ_CONTROL,
    output [5:0] PIPE_TX6_EQ_DEEMPH,
    input PIPE_TX6_EQ_DONE,
    output [3:0] PIPE_TX6_EQ_PRESET,
    output [1:0] PIPE_TX6_POWERDOWN,
    output PIPE_TX6_START_BLOCK,
    output [1:0] PIPE_TX6_SYNC_HEADER,
    output [1:0] PIPE_TX7_CHAR_IS_K,
    output PIPE_TX7_COMPLIANCE,
    output [31:0] PIPE_TX7_DATA,
    output PIPE_TX7_DATA_VALID,
    output PIPE_TX7_ELEC_IDLE,
    input [17:0] PIPE_TX7_EQ_COEFF,
    output [1:0] PIPE_TX7_EQ_CONTROL,
    output [5:0] PIPE_TX7_EQ_DEEMPH,
    input PIPE_TX7_EQ_DONE,
    output [3:0] PIPE_TX7_EQ_PRESET,
    output [1:0] PIPE_TX7_POWERDOWN,
    output PIPE_TX7_START_BLOCK,
    output [1:0] PIPE_TX7_SYNC_HEADER,
    output PIPE_TX_DEEMPH,
    output [2:0] PIPE_TX_MARGIN,
    output [1:0] PIPE_TX_RATE,
    output PIPE_TX_RCVR_DET,
    output PIPE_TX_RESET,
    output PIPE_TX_SWING,
    input PL_DISABLE_SCRAMBLER,
    output PL_EQ_IN_PROGRESS,
    output [1:0] PL_EQ_PHASE,
    input PL_EQ_RESET_EIEOS_COUNT,
    input PL_GEN3_PCS_DISABLE,
    output [7:0] PL_GEN3_PCS_RXSLIDE,
    input [7:0] PL_GEN3_PCS_RXSYNC_DONE,
    input REC_CLK,
    input RESET_N,
    input [255:0] S_AXIS_CC_TDATA,
    input [7:0] S_AXIS_CC_TKEEP,
    input S_AXIS_CC_TLAST,
    output [3:0] S_AXIS_CC_TREADY,
    input [32:0] S_AXIS_CC_TUSER,
    input S_AXIS_CC_TVALID,
    input [255:0] S_AXIS_RQ_TDATA,
    input [7:0] S_AXIS_RQ_TKEEP,
    input S_AXIS_RQ_TLAST,
    output [3:0] S_AXIS_RQ_TREADY,
    input [59:0] S_AXIS_RQ_TUSER,
    input S_AXIS_RQ_TVALID,
    input USER_CLK)/*synthesis syn_black_box syn_noprune=1*/;
    parameter USERCLK_INT_CHOOSE = "FALSE"; //,
    parameter ARI_CAP_ENABLE = "FALSE"; //,
    parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_CC_PARITY_CHK = "FALSE"; //,
    parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; //,
    parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h0; //,
    parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; //,
    parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; //,
    parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; //,
    parameter AXISTEN_IF_RQ_PARITY_CHK = "FALSE"; //,
    parameter [1:0] AXISTEN_IF_WIDTH = 2'h0; //,
    //parameter CORE_CLK_MI_COMPLETION_RAM_L_SEL = "FALSE"; //,
    //parameter CORE_CLK_MI_COMPLETION_RAM_U_SEL = "FALSE"; //,
    //parameter CORE_CLK_MI_REPLAY_RAM_SEL = "FALSE"; //,
    //parameter CORE_CLK_MI_REQUEST_RAM_SEL = "FALSE"; //,
    //parameter CORE_CLK_SEL = "FALSE"; //,
    parameter CRM_CORE_CLK_FREQ_500 = "FALSE"; //,
    parameter [1:0] CRM_USER_CLK_FREQ = 2'h0; //,
    parameter [7:0] DNSTREAM_LINK_NUM = 8'h0; //,
    parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h0; //,
    parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "FALSE"; //,
    parameter [8:0] LL_ACK_TIMEOUT = 9'h0; //,
    parameter LL_ACK_TIMEOUT_EN = "FALSE"; //,
    parameter [1:0] LL_ACK_TIMEOUT_FUNC = 2'h0; //,
    parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0; //,
    parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; //,
    parameter [8:0] LL_REPLAY_TIMEOUT = 9'h0; //,
    parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; //,
    parameter [1:0] LL_REPLAY_TIMEOUT_FUNC = 2'h0; //,
    parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0; //,
    parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; //,
    parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; //,
    parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; //,
    parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; //,
    parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h0; //,
    parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h0; //,
    parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [3:0] PF0_ARI_CAP_VER = 4'h0; //,
    parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_BAR5_CONTROL = 3'h0; //,
    parameter [7:0] PF0_BIST_REGISTER = 8'h0; //,
    parameter [7:0] PF0_CAPABILITY_POINTER = 8'h0; //,
    parameter [23:0] PF0_CLASS_CODE = 24'h0; //,
    parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "FALSE"; //,
    parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "FALSE"; //,
    parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "FALSE"; //,
    parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "FALSE"; //,
    parameter PF0_DEV_CAP2_LTR_SUPPORT = "FALSE"; //,
    parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; //,
    parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; //,
    parameter [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 3'h0; //,
    parameter [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 3'h0; //,
    parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "FALSE"; //,
    parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; //,
    parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h0; //,
    parameter [15:0] PF0_DEVICE_ID = 16'h0; //,
    parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h0; //,
    parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "FALSE"; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h0; //,
    parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h0; //,
    parameter [3:0] PF0_DPA_CAP_VER = 4'h0; //,
    parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h0; //,
    parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; //,
    parameter [7:0] PF0_INTERRUPT_LINE = 8'h0; //,
    parameter [2:0] PF0_INTERRUPT_PIN = 3'h0; //,
    parameter [1:0] PF0_LINK_CAP_ASPM_SUPPORT = 2'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 3'h0; //,
    parameter [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 3'h0; //,
    parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE"; //,
    parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h0; //,
    parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h0; //,
    parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h0; //,
    parameter [3:0] PF0_LTR_CAP_VER = 4'h0; //,
    parameter [2:0] PF0_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h0; //,
    parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] PF0_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] PF0_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h0; //,
    parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; //,
    parameter [3:0] PF0_PB_CAP_VER = 4'h0; //,
    parameter [7:0] PF0_PM_CAP_ID = 8'h0; //,
    parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h0; //,
    parameter PF0_PM_CAP_PMESUPPORT_D0 = "FALSE"; //,
    parameter PF0_PM_CAP_PMESUPPORT_D1 = "FALSE"; //,
    parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "FALSE"; //,
    parameter PF0_PM_CAP_SUPP_D1_STATE = "FALSE"; //,
    parameter [2:0] PF0_PM_CAP_VER_ID = 3'h0; //,
    parameter PF0_PM_CSR_NOSOFTRESET = "FALSE"; //,
    parameter PF0_RBAR_CAP_ENABLE = "FALSE"; //,
    parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0; //,
    parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0; //,
    parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0; //,
    parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h0; //,
    parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h0; //,
    parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h0; //,
    parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h0; //,
    parameter [3:0] PF0_RBAR_CAP_VER = 4'h0; //,
    parameter [2:0] PF0_RBAR_NUM = 3'h0; //,
    parameter [7:0] PF0_REVISION_ID = 8'h0; //,
    parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; //,
    parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0; //,
    parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h0; //,
    parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0; //,
    parameter [3:0] PF0_SRIOV_CAP_VER = 4'h0; //,
    parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0; //,
    parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0; //,
    parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h0; //,
    parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0; //,
    parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0; //,
    parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter PF0_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter PF0_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] PF0_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h0; //,
    parameter [3:0] PF0_VC_CAP_VER = 4'h0; //,
    parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; //,
    parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; //,
    parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h0; //,
    parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h0; //,
    parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_BAR5_CONTROL = 3'h0; //,
    parameter [7:0] PF1_BIST_REGISTER = 8'h0; //,
    parameter [7:0] PF1_CAPABILITY_POINTER = 8'h0; //,
    parameter [23:0] PF1_CLASS_CODE = 24'h0; //,
    parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h0; //,
    parameter [15:0] PF1_DEVICE_ID = 16'h0; //,
    parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h0; //,
    parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "FALSE"; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h0; //,
    parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h0; //,
    parameter [3:0] PF1_DPA_CAP_VER = 4'h0; //,
    parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h0; //,
    parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h0; //,
    parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; //,
    parameter [7:0] PF1_INTERRUPT_LINE = 8'h0; //,
    parameter [2:0] PF1_INTERRUPT_PIN = 3'h0; //,
    parameter [2:0] PF1_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h0; //,
    parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] PF1_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] PF1_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h0; //,
    parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; //,
    parameter [3:0] PF1_PB_CAP_VER = 4'h0; //,
    parameter [7:0] PF1_PM_CAP_ID = 8'h0; //,
    parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] PF1_PM_CAP_VER_ID = 3'h0; //,
    parameter PF1_RBAR_CAP_ENABLE = "FALSE"; //,
    parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0; //,
    parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0; //,
    parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0; //,
    parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h0; //,
    parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h0; //,
    parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h0; //,
    parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h0; //,
    parameter [3:0] PF1_RBAR_CAP_VER = 4'h0; //,
    parameter [2:0] PF1_RBAR_NUM = 3'h0; //,
    parameter [7:0] PF1_REVISION_ID = 8'h0; //,
    parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h0; //,
    parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h0; //,
    parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; //,
    parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0; //,
    parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h0; //,
    parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0; //,
    parameter [3:0] PF1_SRIOV_CAP_VER = 4'h0; //,
    parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0; //,
    parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0; //,
    parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h0; //,
    parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0; //,
    parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0; //,
    parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter PF1_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter PF1_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] PF1_TPHR_CAP_VER = 4'h0; //,
    //parameter PIPE_CLK_SEL = "FALSE"; //,
    parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; //,
    parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; //,
    parameter PL_DISABLE_SCRAMBLING = "FALSE"; //,
    parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; //,
    parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; //,
    parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; //,
    parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h0; //,
    parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h0; //,
    parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; //,
    parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; //,
    parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h0; //,
    parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h0; //,
    parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h0; //,
    parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h0; //,
    parameter [7:0] PL_N_FTS_COMCLK_GEN1 = 8'h0; //,
    parameter [7:0] PL_N_FTS_COMCLK_GEN2 = 8'h0; //,
    parameter [7:0] PL_N_FTS_COMCLK_GEN3 = 8'h0; //,
    parameter [7:0] PL_N_FTS_GEN1 = 8'h0; //,
    parameter [7:0] PL_N_FTS_GEN2 = 8'h0; //,
    parameter [7:0] PL_N_FTS_GEN3 = 8'h0; //,
    parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; //,
    parameter PL_UPSTREAM_FACING = "FALSE"; //,
    parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h0; //,
    parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h0; //,
    parameter PM_ENABLE_SLOT_POWER_CAPTURE = "FALSE"; //,
    parameter [31:0] PM_L1_REENTRY_DELAY = 32'h0; //,
    parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h0; //,
    parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0; //,
    //parameter REC_CLK_SEL = "FALSE"; //,
    parameter [0:0] SPARE_BIT0 = 1'h0; //,
    parameter [0:0] SPARE_BIT1 = 1'h0; //,
    parameter [0:0] SPARE_BIT2 = 1'h0; //,
    parameter [0:0] SPARE_BIT3 = 1'h0; //,
    parameter [0:0] SPARE_BIT4 = 1'h0; //,
    parameter [0:0] SPARE_BIT5 = 1'h0; //,
    parameter [0:0] SPARE_BIT6 = 1'h0; //,
    parameter [0:0] SPARE_BIT7 = 1'h0; //,
    parameter [0:0] SPARE_BIT8 = 1'h0; //,
    parameter [7:0] SPARE_BYTE0 = 8'h0; //,
    parameter [7:0] SPARE_BYTE1 = 8'h0; //,
    parameter [7:0] SPARE_BYTE2 = 8'h0; //,
    parameter [7:0] SPARE_BYTE3 = 8'h0; //,
    parameter [31:0] SPARE_WORD0 = 32'h0; //,
    parameter [31:0] SPARE_WORD1 = 32'h0; //,
    parameter [31:0] SPARE_WORD2 = 32'h0; //,
    parameter [31:0] SPARE_WORD3 = 32'h0; //,
    parameter SRIOV_CAP_ENABLE = "FALSE"; //,
    parameter TEST_MODE_PIN_CHAR = "FALSE"; //,
    parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'h0; //,
    parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0; //,
    parameter [11:0] TL_CREDITS_CD = 12'h0; //,
    parameter [7:0] TL_CREDITS_CH = 8'h0; //,
    parameter [11:0] TL_CREDITS_NPD = 12'h0; //,
    parameter [7:0] TL_CREDITS_NPH = 8'h0; //,
    parameter [11:0] TL_CREDITS_PD = 12'h0; //,
    parameter [7:0] TL_CREDITS_PH = 8'h0; //,
    parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "FALSE"; //,
    parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; //,
    parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; //,
    parameter TL_LEGACY_MODE_ENABLE = "FALSE"; //,
    parameter TL_PF_ENABLE_REG = "FALSE"; //,
    parameter TL_TAG_MGMT_ENABLE = "FALSE"; //,
    //parameter USER_CLK_SEL = "FALSE"; //,
    parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [7:0] VF0_CAPABILITY_POINTER = 8'h0; //,
    parameter [2:0] VF0_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF0_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF0_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF0_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF0_PM_CAP_VER_ID = 3'h0; //,
    parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF0_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF0_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF0_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF1_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF1_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF1_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF1_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF1_PM_CAP_VER_ID = 3'h0; //,
    parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF1_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF1_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF1_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF2_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF2_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF2_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF2_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF2_PM_CAP_VER_ID = 3'h0; //,
    parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF2_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF2_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF2_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF3_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF3_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF3_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF3_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF3_PM_CAP_VER_ID = 3'h0; //,
    parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF3_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF3_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF3_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF4_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF4_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF4_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF4_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF4_PM_CAP_VER_ID = 3'h0; //,
    parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF4_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF4_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF4_TPHR_CAP_VER = 4'h0; //,
    parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF5_MSI_CAP_MULTIMSGCAP = 3'h0; //,
    parameter [2:0] VF5_MSIX_CAP_PBA_BIR = 3'h0; //,
    parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h0; //,
    parameter [2:0] VF5_MSIX_CAP_TABLE_BIR = 3'h0; //,
    parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h0; //,
    parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h0; //,
    parameter [7:0] VF5_PM_CAP_ID = 8'h0; //,
    parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h0; //,
    parameter [2:0] VF5_PM_CAP_VER_ID = 3'h0; //,
    parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE"; //,
    parameter VF5_TPHR_CAP_ENABLE = "FALSE"; //,
    parameter VF5_TPHR_CAP_INT_VEC_MODE = "FALSE"; //,
    parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h0; //,
    parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; //,
    parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; //,
    parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h0; //,
    parameter [3:0] VF5_TPHR_CAP_VER = 4'h0; //,
endmodule

(* black_box, dont_touch="true" *)
module xsSOC_INTERFACE(
    // to pclk
    output CLK0,
    output CLK1,
    output CLK2,
    output CLK3,
    // cib
    output [3:0] DMA_ACK,
    output [3:0] DMA_BUSY,
    input [3:0] DMA_REQ,
    input [31:0] HADDR_M0,
    input [31:0] HADDR_M1,
    output [31:0] HADDR_S0,
    input [2:0] HBURST_M0,
    input [2:0] HBURST_M1,
    output [2:0] HBURST_S0,
    input HCLK_M0_CLK,
    output HCLK_M0_RESETN,
    input HCLK_M1_CLK,
    output HCLK_M1_RESETN,
    input HCLK_S0_CLK,
    output HCLK_S0_RESETN,
    input [3:0] HPROT_M0,
    input [3:0] HPROT_M1,
    output [3:0] HPROT_S0,
    output [31:0] HRDATA_M0,
    output [31:0] HRDATA_M1,
    input [31:0] HRDATA_S0,
    input HREADY_M0,
    input HREADY_M1,
    input HREADY_S0,
    output HREADYOUT_M0,
    output HREADYOUT_M1,
    output HRESP_M0,
    output HRESP_M1,
    input HRESP_S0,
    input HSELX_M0,
    input HSELX_M1,
    input [2:0] HSIZE_M0,
    input [2:0] HSIZE_M1,
    output [2:0] HSIZE_S0,
    input [1:0] HTRANS_M0,
    input [1:0] HTRANS_M1,
    output [1:0] HTRANS_S0,
    input [31:0] HWDATA_M0,
    input [31:0] HWDATA_M1,
    output [31:0] HWDATA_S0,
    input HWRITE_M0,
    input HWRITE_M1,
    output HWRITE_S0,
    output [7:0] IRQ_IN,
    input [15:0] IRQ_OUT,
    output RESET0_N,
    output RESET1_N,
    output RESET2_N,
    output RESET3_N)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsLPLL_MFGOUT_MUX(input T0, T1, M, B0, B1)/*synthesis syn_black_box syn_noprune=1*/;
endmodule

(* black_box, dont_touch="true" *)
module xsHBUF(
	I,
	O
	)/*synthesis syn_black_box syn_noprune=1*/;
	input  I;
	output O;
endmodule

(* black_box, dont_touch="true" *)
module xsBRIDGE(
	I,
	O
	)/*synthesis syn_black_box syn_noprune=1*/;
	input  I;
	output O;
endmodule

(* black_box, dont_touch="true" *)
module xsRBUF(
	I,
	O
	)/*synthesis syn_black_box syn_noprune=1*/;
	input  I;
	output O;
endmodule
