
set mlib "/MACRO_SYN"

##############################################################################

obj.cell.set $mlib/MSYN_RAM_16_16X1S           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_16X2S           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_16X4S           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_16X8S          bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_32X1S           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_32X2S           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_32X4S          bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_32X8S          bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_64X1S           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_64X2S          bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_128X1S         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_256X1S         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_16X1D           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_32X1D           bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_64X1D          bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_128X1D         bram ;#dram

obj.cell.set $mlib/MSYN_RAM_16_16X1SBR         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_16X2SBR         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_16X4SBR         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_16X8SBR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_32X1SBR         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_32X2SBR         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_32X4SBR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_32X8SBR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_64X1SBR         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_64X2SBR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_128X1SBR       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_256X1SBR       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_16X1D0BR1BR     bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_16X1D0BR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_16X1D1BR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_32X1D0BR1BR     bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_32X1D0BR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_32X1D1BR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_64X1D0BR1BR    bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_64X1D0BR       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_64X1D1BR       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_128X1D0BR1BR   bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_128X1D0BR      bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_128X1D1BR      bram ;#dram
obj.cell.set $mlib/MSYN_RAM_16_16X1SBN         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_32X1SBN         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_64X1SBN         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_128X1SBN       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_256X1SBN       bram ;#dram

obj.cell.set $mlib/MSYN_RAM_256_M64_PDP        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_M64_PDPR       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_M32_PDP        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_M32_PDPR       bram ;#dram

obj.cell.set $mlib/MSYN_RAM_256_M64_SP         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_M64_SPR        bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_M32_SP         bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_M32_SPR        bram ;#dram

obj.cell.set $mlib/MSYN_RAM_16_16X1_BWWE       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_32X1_BWWE       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_64X1_BWWE       bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_128X1_BWWE     bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_256X1_BWWE     bram ;#dram
obj.cell.set $mlib/MSYN_RAM_32_16X1D_BWWE      bram ;#dram
obj.cell.set $mlib/MSYN_RAM_64_32X1D_BWWE      bram ;#dram
obj.cell.set $mlib/MSYN_RAM_128_64X1D_BWWE     bram ;#dram
obj.cell.set $mlib/MSYN_RAM_256_128X1D_BWWE    bram ;#dram

obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1WW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1WR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1WN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1RW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1RR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1RN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1NW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1NR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1S1NN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2WW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2WR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2WN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2RW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2RR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2RN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2NW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2NR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2S2NN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4WW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4WR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4WN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4RW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4RR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4RN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4NW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4NR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4S4NN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9WW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9WR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9WN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9RW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9RR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9RN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9NW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9NR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9S9NN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18WW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18WR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18WN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18RW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18RR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18RN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18NW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18NR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18NN  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1W  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1R  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS1N  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2W  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2R  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS2N  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4W  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4R  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS4N  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9W  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9R  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS9N  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18W  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18R  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18N  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36S36_PDPR  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36S36_PDPW  bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36S36_PDPN  bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1WW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1WR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1WN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1RW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1RR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1RN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1NW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1NR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1S1NN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2WW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2WR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2WN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2RW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2RR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2RN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2NW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2NR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2S2NN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4WW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4WR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4WN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4RW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4RR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4RN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4NW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4NR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4S4NN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9WW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9WR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9WN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9RW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9RR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9RN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9NW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9NR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9S9NN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18WW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18WR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18WN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18RW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18RR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18RN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18NW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18NR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18NN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36WW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36WR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36WN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36RW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36RR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36RN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36NW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36NR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36NN  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1W  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1R  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS1N  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2W  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2R  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS2N  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4W  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4R  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS4N  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9W  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9R  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS9N  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18W  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18R  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18N  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36W  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36R  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36N  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72S72_PDPR  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72S72_PDPW  bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72S72_PDPN  bram


obj.cell.set $mlib/MSYN_RAM_18432_B16KS16W_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16R_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16N_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS16W_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16R_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16N_BWWE bram

obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16WW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16WR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16WN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16RR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16RW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16RN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16NN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16NW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS16S16NR_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16WW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16WR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16WN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16RR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16RW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16RN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16NN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16NW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS16S16NR_BWWE bram

obj.cell.set $mlib/MSYN_RAM_18432_B16KS18W_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18R_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18N_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS18W_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18R_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18N_BWWE bram

obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18WW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18WR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18WN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18RR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18RW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18RN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18NN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18NW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS18S18NR_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18WW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18WR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18WN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18RR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18RW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18RN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18NN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18NW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS18S18NR_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS32W_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS32R_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS32N_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS36W_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36R_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36N_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS32S32WW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS32S32WR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS32S32WN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS32S32RR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS32S32RN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS32S32NN_BWWE bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36WW_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36WR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36WN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36RR_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36RN_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS36S36NN_BWWE bram

obj.cell.set $mlib/MSYN_RAM_18432_B16KS36S36_BWWE_PDPR bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36S36_BWWE_PDPW bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36S36_BWWE_PDPN bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS72S72_BWWE_PDPR bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72S72_BWWE_PDPW bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72S72_BWWE_PDPN bram

obj.cell.set $mlib/MSYN_RAM_18432_B16KS32W bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS32R bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS32N bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36W bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36R bram
obj.cell.set $mlib/MSYN_RAM_18432_B16KS36N bram

obj.cell.set $mlib/MSYN_RAM_36864_B32KS64W bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS64R bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS64N bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72W bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72R bram
obj.cell.set $mlib/MSYN_RAM_36864_B32KS72N bram

obj.cell.set $mlib/MSYN_RAM_36864_B32_ASYM_BWWE bram
obj.cell.set $mlib/MSYN_RAM_36864_B32_ASYM bram
obj.cell.set $mlib/MSYN_RAM_18432_B16_ASYM bram


obj.cell.set $mlib/MSYN_DSP_MULT_A18B18P36_MA    dsp
obj.cell.set $mlib/MSYN_DSP_MULT_A18B18P36_PA    dsp
obj.cell.set $mlib/MSYN_DSP_MULT_A9B9P18_MA      dsp
obj.cell.set $mlib/MSYN_DSP_MULT_A9B9P18_PA      dsp
obj.cell.set $mlib/MSYN_DSP_ALU_A36B36R54        dsp
obj.cell.set $mlib/MSYN_DSP_ALU_A18B18R24        dsp
obj.cell.set $mlib/MSYN_DSP_PRADD_A9B9P9         dsp
obj.cell.set $mlib/MSYN_DSP_PRADD_A18B18P18      dsp

