[V]dst: BCODT10 CLK
[V]rgn:     13
[V]dst: BCODT8 CLK
[V]rgn:     9
[V]dst: BCODT9 CLK
[V]rgn:     11
[V]dst: BDDRCTRL0 SCAN_CLK
[V]rgn:     11
[V]dst: BDDRCTRL0 SCLK
[V]rgn:     11
[V]dst: BDDRCTRL0 USR_CMD_CLK_0
[V]rgn:     9
[V]dst: BDDRCTRL0 USR_CMD_CLK_1
[V]rgn:     9
[V]dst: BDDRCTRL0 USR_DR_CLK_0
[V]rgn:     9
[V]dst: BDDRCTRL0 USR_DR_CLK_1
[V]rgn:     11
[V]dst: BDDRCTRL0 USR_DW_CLK_0
[V]rgn:     9
[V]dst: BDDRCTRL0 USR_DW_CLK_1
[V]rgn:     11
[V]dst: BDDRCTRL1 SCAN_CLK
[V]rgn:     11
[V]dst: BDDRCTRL1 SCLK
[V]rgn:     11
[V]dst: BDDRCTRL1 USR_CMD_CLK_0
[V]rgn:     13
[V]dst: BDDRCTRL1 USR_CMD_CLK_1
[V]rgn:     13
[V]dst: BDDRCTRL1 USR_DR_CLK_0
[V]rgn:     13
[V]dst: BDDRCTRL1 USR_DR_CLK_1
[V]rgn:     11
[V]dst: BDDRCTRL1 USR_DW_CLK_0
[V]rgn:     13
[V]dst: BDDRCTRL1 USR_DW_CLK_1
[V]rgn:     11
#[V]dst: BDDRDLL0_0 CLK
#[V]rgn:     9
#[V]dst: BDDRDLL0_1 CLK
#[V]rgn:     9
#[V]dst: BDDRDLL0_2 CLK
#[V]rgn:     9
#[V]dst: BDDRDLL0_3 CLK
#[V]rgn:     9
#[V]dst: BDDRDLL1_0 CLK
#[V]rgn:     11
#[V]dst: BDDRDLL1_1 CLK
#[V]rgn:     11
#[V]dst: BDDRDLL1_2 CLK
#[V]rgn:     11
#[V]dst: BDDRDLL1_3 CLK
#[V]rgn:     11
#[V]dst: BDDRDLL2_0 CLK
#[V]rgn:     13
#[V]dst: BDDRDLL2_1 CLK
#[V]rgn:     13
#[V]dst: BDDRDLL2_2 CLK
#[V]rgn:     13
#[V]dst: BDDRDLL2_3 CLK
#[V]rgn:     13
[V]dst: BDQS0_0 SCLK
[V]rgn:     9
[V]dst: BDQS0_1 SCLK
[V]rgn:     9
[V]dst: BDQS0_2 SCLK
[V]rgn:     9
[V]dst: BDQS0_3 SCLK
[V]rgn:     9
[V]dst: BDQS1_0 SCLK
[V]rgn:     11
[V]dst: BDQS1_1 SCLK
[V]rgn:     11
[V]dst: BDQS1_2 SCLK
[V]rgn:     11
[V]dst: BDQS1_3 SCLK
[V]rgn:     11
[V]dst: BDQS2_0 SCLK
[V]rgn:     13
[V]dst: BDQS2_1 SCLK
[V]rgn:     13
[V]dst: BDQS2_2 SCLK
[V]rgn:     13
[V]dst: BDQS2_3 SCLK
[V]rgn:     13
#[V]dst: BECLKSYNC0_0 ECLKI
#[V]rgn:     9
#[V]dst: BECLKSYNC0_1 ECLKI
#[V]rgn:     9
#[V]dst: BECLKSYNC0_2 ECLKI
#[V]rgn:     9
#[V]dst: BECLKSYNC0_3 ECLKI
#[V]rgn:     9
#[V]dst: BECLKSYNC1_0 ECLKI
#[V]rgn:     11
#[V]dst: BECLKSYNC1_1 ECLKI
#[V]rgn:     11
#[V]dst: BECLKSYNC1_2 ECLKI
#[V]rgn:     11
#[V]dst: BECLKSYNC1_3 ECLKI
#[V]rgn:     11
#[V]dst: BECLKSYNC2_0 ECLKI
#[V]rgn:     13
#[V]dst: BECLKSYNC2_1 ECLKI
#[V]rgn:     13
#[V]dst: BECLKSYNC2_2 ECLKI
#[V]rgn:     13
#[V]dst: BECLKSYNC2_3 ECLKI
#[V]rgn:     13
#[V]dst: BPLL0 CLKFB
#[V]rgn:     9
[V]dst: BPLL0 WBCLK
[V]rgn:     9
[V]dst: BPLL0 CLKI
[V]rgn:     9
#[V]dst: BPLLREFCS0 CLK0
#[V]rgn:     9
#[V]dst: BPLLREFCS0 CLK1
#[V]rgn:     9
[V]dst: CIBBOOT BOOTCLK
[V]rgn:     7
[V]dst: DNA_PORT CLK
[V]rgn:     7
[V]dst: EFB NO_UDM_PORT__R32C169_JUSERCLK_EFB
[V]rgn:     7
[V]dst: GSR CLK
[V]rgn:     7
[V]dst: ISCPU CLK
[V]rgn:     7
[V]dst: PCIE CORE_CLK
[V]rgn:     5
[V]rgn:     7
[V]dst: PCIE CORE_CLK_MI_COMPLETION_RAM_L
[V]rgn:     7
[V]rgn:     7
[V]dst: PCIE CORE_CLK_MI_COMPLETION_RAM_U
[V]rgn:     7
[V]rgn:     7
[V]dst: PCIE CORE_CLK_MI_REPLAY_RAM
[V]rgn:     5
[V]rgn:     5
[V]dst: PCIE CORE_CLK_MI_REQUEST_RAM
[V]rgn:     5
[V]rgn:     5
[V]dst: PCIE DRP_CLK
[V]rgn:     5
[V]dst: PCIE PIPE_CLK
[V]rgn:     7
[V]rgn:     7
[V]dst: PCIE REC_CLK
[V]rgn:     7
[V]rgn:     7
[V]dst: PCIE SCAN_CLK
[V]rgn:     5
[V]dst: PCIE USER_CLK
[V]rgn:     5
[V]rgn:     7
[V]dst: SADC CLKL
[V]rgn:     6
[V]dst: SED SEDEXCLK
[V]rgn:     7
[V]dst: SERDES2_CH0 ALT_SIGVALID_CLK
[V]rgn:     5
[V]dst: SERDES2_CH0 CKPINRSRVD0
[V]rgn:     5
[V]dst: SERDES2_CH0 CKPINRSRVD1
[V]rgn:     5
[V]dst: SERDES2_CH0 COREREFCLK
[V]rgn:     5
[V]dst: SERDES2_CH0 CPLLDMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH0 DCLK
[V]rgn:     5
[V]dst: SERDES2_CH0 DMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH0 PMASCANCLK0
[V]rgn:     5
[V]dst: SERDES2_CH0 PMASCANCLK1
[V]rgn:     5
[V]dst: SERDES2_CH0 PMASCANCLK2
[V]rgn:     5
[V]dst: SERDES2_CH0 PMASCANCLK3
[V]rgn:     5
[V]dst: SERDES2_CH0 PMASCANCLK4
[V]rgn:     5
[V]dst: SERDES2_CH0 RING_OSC_CLK_INT
[V]rgn:     5
[V]dst: SERDES2_CH0 RXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH0 RXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_CH0 SCANCLK
[V]rgn:     5
[V]dst: SERDES2_CH0 TCOCLKFSMFROUT
[V]rgn:     5
[V]dst: SERDES2_CH0 TSTCLK0
[V]rgn:     5
[V]dst: SERDES2_CH0 TSTCLK1
[V]rgn:     5
[V]dst: SERDES2_CH0 TXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH0 TXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_CH1 ALT_SIGVALID_CLK
[V]rgn:     5
[V]dst: SERDES2_CH1 CKPINRSRVD0
[V]rgn:     5
[V]dst: SERDES2_CH1 CKPINRSRVD1
[V]rgn:     5
[V]dst: SERDES2_CH1 COREREFCLK
[V]rgn:     5
[V]dst: SERDES2_CH1 CPLLDMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH1 DCLK
[V]rgn:     5
[V]dst: SERDES2_CH1 DMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH1 PMASCANCLK0
[V]rgn:     5
[V]dst: SERDES2_CH1 PMASCANCLK1
[V]rgn:     5
[V]dst: SERDES2_CH1 PMASCANCLK2
[V]rgn:     5
[V]dst: SERDES2_CH1 PMASCANCLK3
[V]rgn:     5
[V]dst: SERDES2_CH1 PMASCANCLK4
[V]rgn:     5
[V]dst: SERDES2_CH1 RING_OSC_CLK_INT
[V]rgn:     5
[V]dst: SERDES2_CH1 RXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH1 RXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_CH1 SCANCLK
[V]rgn:     5
[V]dst: SERDES2_CH1 TCOCLKFSMFROUT
[V]rgn:     5
[V]dst: SERDES2_CH1 TSTCLK0
[V]rgn:     5
[V]dst: SERDES2_CH1 TSTCLK1
[V]rgn:     5
[V]dst: SERDES2_CH1 TXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH1 TXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_CH2 ALT_SIGVALID_CLK
[V]rgn:     5
[V]dst: SERDES2_CH2 CKPINRSRVD0
[V]rgn:     5
[V]dst: SERDES2_CH2 CKPINRSRVD1
[V]rgn:     5
[V]dst: SERDES2_CH2 COREREFCLK
[V]rgn:     5
[V]dst: SERDES2_CH2 CPLLDMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH2 DCLK
[V]rgn:     5
[V]dst: SERDES2_CH2 DMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH2 PMASCANCLK0
[V]rgn:     5
[V]dst: SERDES2_CH2 PMASCANCLK1
[V]rgn:     5
[V]dst: SERDES2_CH2 PMASCANCLK2
[V]rgn:     5
[V]dst: SERDES2_CH2 PMASCANCLK3
[V]rgn:     5
[V]dst: SERDES2_CH2 PMASCANCLK4
[V]rgn:     5
[V]dst: SERDES2_CH2 RING_OSC_CLK_INT
[V]rgn:     5
[V]dst: SERDES2_CH2 RXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH2 RXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_CH2 SCANCLK
[V]rgn:     5
[V]dst: SERDES2_CH2 TCOCLKFSMFROUT
[V]rgn:     5
[V]dst: SERDES2_CH2 TSTCLK0
[V]rgn:     5
[V]dst: SERDES2_CH2 TSTCLK1
[V]rgn:     5
[V]dst: SERDES2_CH2 TXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH2 TXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_CH3 ALT_SIGVALID_CLK
[V]rgn:     5
[V]dst: SERDES2_CH3 CKPINRSRVD0
[V]rgn:     5
[V]dst: SERDES2_CH3 CKPINRSRVD1
[V]rgn:     5
[V]dst: SERDES2_CH3 COREREFCLK
[V]rgn:     5
[V]dst: SERDES2_CH3 CPLLDMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH3 DCLK
[V]rgn:     5
[V]dst: SERDES2_CH3 DMONCLK
[V]rgn:     5
[V]dst: SERDES2_CH3 PMASCANCLK0
[V]rgn:     5
[V]dst: SERDES2_CH3 PMASCANCLK1
[V]rgn:     5
[V]dst: SERDES2_CH3 PMASCANCLK2
[V]rgn:     5
[V]dst: SERDES2_CH3 PMASCANCLK3
[V]rgn:     5
[V]dst: SERDES2_CH3 PMASCANCLK4
[V]rgn:     5
[V]dst: SERDES2_CH3 RING_OSC_CLK_INT
[V]rgn:     5
[V]dst: SERDES2_CH3 RXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH3 RXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_CH3 SCANCLK
[V]rgn:     5
[V]dst: SERDES2_CH3 TCOCLKFSMFROUT
[V]rgn:     5
[V]dst: SERDES2_CH3 TSTCLK0
[V]rgn:     5
[V]dst: SERDES2_CH3 TSTCLK1
[V]rgn:     5
[V]dst: SERDES2_CH3 TXUSRCLK
[V]rgn:     5
[V]dst: SERDES2_CH3 TXUSRCLK2
[V]rgn:     5
[V]dst: SERDES2_COM COREREFCLK
[V]rgn:     5
[V]dst: SERDES2_COM DCLK_COM
[V]rgn:     5
[V]dst: SERDES2_COM QDCLKPINSPRD0
[V]rgn:     5
[V]dst: SERDES2_COM QDCLKPINSPRD1
[V]rgn:     5
[V]dst: SERDES2_COM QDPMASCANCLK0
[V]rgn:     5
[V]dst: SERDES2_COM QDPMASCANCLK1
[V]rgn:     5
[V]dst: SERDES2_COM QPLLDMONCLK
[V]rgn:     5
[V]dst: SERDES2_COM REFCKTESTCLK0
[V]rgn:     5
[V]dst: SERDES2_COM REFCKTESTCLK1
[V]rgn:     5
[V]dst: SERDES3_CH0 ALT_SIGVALID_CLK
[V]rgn:     7
[V]dst: SERDES3_CH0 CKPINRSRVD0
[V]rgn:     7
[V]dst: SERDES3_CH0 CKPINRSRVD1
[V]rgn:     7
[V]dst: SERDES3_CH0 COREREFCLK
[V]rgn:     7
[V]dst: SERDES3_CH0 CPLLDMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH0 DCLK
[V]rgn:     7
[V]dst: SERDES3_CH0 DMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH0 PMASCANCLK0
[V]rgn:     7
[V]dst: SERDES3_CH0 PMASCANCLK1
[V]rgn:     7
[V]dst: SERDES3_CH0 PMASCANCLK2
[V]rgn:     7
[V]dst: SERDES3_CH0 PMASCANCLK3
[V]rgn:     7
[V]dst: SERDES3_CH0 PMASCANCLK4
[V]rgn:     7
[V]dst: SERDES3_CH0 RING_OSC_CLK_INT
[V]rgn:     7
[V]dst: SERDES3_CH0 RXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH0 RXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_CH0 SCANCLK
[V]rgn:     7
[V]dst: SERDES3_CH0 TCOCLKFSMFROUT
[V]rgn:     7
[V]dst: SERDES3_CH0 TSTCLK0
[V]rgn:     7
[V]dst: SERDES3_CH0 TSTCLK1
[V]rgn:     7
[V]dst: SERDES3_CH0 TXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH0 TXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_CH1 ALT_SIGVALID_CLK
[V]rgn:     7
[V]dst: SERDES3_CH1 CKPINRSRVD0
[V]rgn:     7
[V]dst: SERDES3_CH1 CKPINRSRVD1
[V]rgn:     7
[V]dst: SERDES3_CH1 COREREFCLK
[V]rgn:     7
[V]dst: SERDES3_CH1 CPLLDMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH1 DCLK
[V]rgn:     7
[V]dst: SERDES3_CH1 DMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH1 PMASCANCLK0
[V]rgn:     7
[V]dst: SERDES3_CH1 PMASCANCLK1
[V]rgn:     7
[V]dst: SERDES3_CH1 PMASCANCLK2
[V]rgn:     7
[V]dst: SERDES3_CH1 PMASCANCLK3
[V]rgn:     7
[V]dst: SERDES3_CH1 PMASCANCLK4
[V]rgn:     7
[V]dst: SERDES3_CH1 RING_OSC_CLK_INT
[V]rgn:     7
[V]dst: SERDES3_CH1 RXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH1 RXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_CH1 SCANCLK
[V]rgn:     7
[V]dst: SERDES3_CH1 TCOCLKFSMFROUT
[V]rgn:     7
[V]dst: SERDES3_CH1 TSTCLK0
[V]rgn:     7
[V]dst: SERDES3_CH1 TSTCLK1
[V]rgn:     7
[V]dst: SERDES3_CH1 TXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH1 TXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_CH2 ALT_SIGVALID_CLK
[V]rgn:     7
[V]dst: SERDES3_CH2 CKPINRSRVD0
[V]rgn:     7
[V]dst: SERDES3_CH2 CKPINRSRVD1
[V]rgn:     7
[V]dst: SERDES3_CH2 COREREFCLK
[V]rgn:     7
[V]dst: SERDES3_CH2 CPLLDMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH2 DCLK
[V]rgn:     7
[V]dst: SERDES3_CH2 DMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH2 PMASCANCLK0
[V]rgn:     7
[V]dst: SERDES3_CH2 PMASCANCLK1
[V]rgn:     7
[V]dst: SERDES3_CH2 PMASCANCLK2
[V]rgn:     7
[V]dst: SERDES3_CH2 PMASCANCLK3
[V]rgn:     7
[V]dst: SERDES3_CH2 PMASCANCLK4
[V]rgn:     7
[V]dst: SERDES3_CH2 RING_OSC_CLK_INT
[V]rgn:     7
[V]dst: SERDES3_CH2 RXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH2 RXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_CH2 SCANCLK
[V]rgn:     7
[V]dst: SERDES3_CH2 TCOCLKFSMFROUT
[V]rgn:     7
[V]dst: SERDES3_CH2 TSTCLK0
[V]rgn:     7
[V]dst: SERDES3_CH2 TSTCLK1
[V]rgn:     7
[V]dst: SERDES3_CH2 TXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH2 TXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_CH3 ALT_SIGVALID_CLK
[V]rgn:     7
[V]dst: SERDES3_CH3 CKPINRSRVD0
[V]rgn:     7
[V]dst: SERDES3_CH3 CKPINRSRVD1
[V]rgn:     7
[V]dst: SERDES3_CH3 COREREFCLK
[V]rgn:     7
[V]dst: SERDES3_CH3 CPLLDMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH3 DCLK
[V]rgn:     7
[V]dst: SERDES3_CH3 DMONCLK
[V]rgn:     7
[V]dst: SERDES3_CH3 PMASCANCLK0
[V]rgn:     7
[V]dst: SERDES3_CH3 PMASCANCLK1
[V]rgn:     7
[V]dst: SERDES3_CH3 PMASCANCLK2
[V]rgn:     7
[V]dst: SERDES3_CH3 PMASCANCLK3
[V]rgn:     7
[V]dst: SERDES3_CH3 PMASCANCLK4
[V]rgn:     7
[V]dst: SERDES3_CH3 RING_OSC_CLK_INT
[V]rgn:     7
[V]dst: SERDES3_CH3 RXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH3 RXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_CH3 SCANCLK
[V]rgn:     7
[V]dst: SERDES3_CH3 TCOCLKFSMFROUT
[V]rgn:     7
[V]dst: SERDES3_CH3 TSTCLK0
[V]rgn:     7
[V]dst: SERDES3_CH3 TSTCLK1
[V]rgn:     7
[V]dst: SERDES3_CH3 TXUSRCLK
[V]rgn:     7
[V]dst: SERDES3_CH3 TXUSRCLK2
[V]rgn:     7
[V]dst: SERDES3_COM COREREFCLK
[V]rgn:     7
[V]dst: SERDES3_COM DCLK_COM
[V]rgn:     7
[V]dst: SERDES3_COM QDCLKPINSPRD0
[V]rgn:     7
[V]dst: SERDES3_COM QDCLKPINSPRD1
[V]rgn:     7
[V]dst: SERDES3_COM QDPMASCANCLK0
[V]rgn:     7
[V]dst: SERDES3_COM QDPMASCANCLK1
[V]rgn:     7
[V]dst: SERDES3_COM QPLLDMONCLK
[V]rgn:     7
[V]dst: SERDES3_COM REFCKTESTCLK0
[V]rgn:     7
[V]dst: SERDES3_COM REFCKTESTCLK1
[V]rgn:     7
[V]dst: TDDRCTRL0 SCAN_CLK
[V]rgn:     4
[V]dst: TDDRCTRL0 SCLK
[V]rgn:     4
[V]dst: TDDRCTRL0 USR_CMD_CLK_0
[V]rgn:     4
[V]dst: TDDRCTRL0 USR_CMD_CLK_1
[V]rgn:     4
[V]dst: TDDRCTRL0 USR_DR_CLK_0
[V]rgn:     4
[V]dst: TDDRCTRL0 USR_DR_CLK_1
[V]rgn:     4
[V]dst: TDDRCTRL0 USR_DW_CLK_0
[V]rgn:     4
[V]dst: TDDRCTRL0 USR_DW_CLK_1
[V]rgn:     6
#[V]dst: TDDRDLL2_0 CLK
#[V]rgn:     4
#[V]dst: TDDRDLL2_1 CLK
#[V]rgn:     4
#[V]dst: TDDRDLL2_2 CLK
#[V]rgn:     4
#[V]dst: TDDRDLL2_3 CLK
#[V]rgn:     4
#[V]dst: TDDRDLL3_0 CLK
#[V]rgn:     6
#[V]dst: TDDRDLL3_1 CLK
#[V]rgn:     6
#[V]dst: TDDRDLL3_2 CLK
#[V]rgn:     6
#[V]dst: TDDRDLL3_3 CLK
#[V]rgn:     6
#[V]dst: TDDRDLL4_0 CLK
#[V]rgn:     8
#[V]dst: TDDRDLL4_1 CLK
#[V]rgn:     8
#[V]dst: TDDRDLL4_2 CLK
#[V]rgn:     8
#[V]dst: TDDRDLL4_3 CLK
#[V]rgn:     8
#[V]dst: TDDRDLL5_0 CLK
#[V]rgn:     10
#[V]dst: TDDRDLL5_1 CLK
#[V]rgn:     10
#[V]dst: TDDRDLL5_2 CLK
#[V]rgn:     10
#[V]dst: TDDRDLL5_3 CLK
#[V]rgn:     10
#[V]dst: TDDRDLL6_0 CLK
#[V]rgn:     12
#[V]dst: TDDRDLL6_1 CLK
#[V]rgn:     12
#[V]dst: TDDRDLL6_2 CLK
#[V]rgn:     12
#[V]dst: TDDRDLL6_3 CLK
#[V]rgn:     12
[V]dst: TDQS2_0 SCLK
[V]rgn:     4
[V]dst: TDQS2_1 SCLK
[V]rgn:     4
[V]dst: TDQS2_2 SCLK
[V]rgn:     4
[V]dst: TDQS2_3 SCLK
[V]rgn:     4
[V]dst: TDQS3_0 SCLK
[V]rgn:     6
[V]dst: TDQS3_1 SCLK
[V]rgn:     6
[V]dst: TDQS3_2 SCLK
[V]rgn:     6
[V]dst: TDQS3_3 SCLK
[V]rgn:     6
[V]dst: TDQS4_0 SCLK
[V]rgn:     8
[V]dst: TDQS4_1 SCLK
[V]rgn:     8
[V]dst: TDQS4_2 SCLK
[V]rgn:     8
[V]dst: TDQS4_3 SCLK
[V]rgn:     8
[V]dst: TDQS5_0 SCLK
[V]rgn:     10
[V]dst: TDQS5_1 SCLK
[V]rgn:     10
[V]dst: TDQS5_2 SCLK
[V]rgn:     10
[V]dst: TDQS5_3 SCLK
[V]rgn:     10
[V]dst: TDQS6_0 SCLK
[V]rgn:     12
[V]dst: TDQS6_1 SCLK
[V]rgn:     12
[V]dst: TDQS6_2 SCLK
[V]rgn:     12
[V]dst: TDQS6_3 SCLK
[V]rgn:     12
#[V]dst: TECLKSYNC2_0 ECLKI
#[V]rgn:     4
#[V]dst: TECLKSYNC2_1 ECLKI
#[V]rgn:     4
#[V]dst: TECLKSYNC2_2 ECLKI
#[V]rgn:     4
#[V]dst: TECLKSYNC2_3 ECLKI
#[V]rgn:     4
#[V]dst: TECLKSYNC3_0 ECLKI
#[V]rgn:     6
#[V]dst: TECLKSYNC3_1 ECLKI
#[V]rgn:     6
#[V]dst: TECLKSYNC3_2 ECLKI
#[V]rgn:     6
#[V]dst: TECLKSYNC3_3 ECLKI
#[V]rgn:     6
#[V]dst: TECLKSYNC4_0 ECLKI
#[V]rgn:     8
#[V]dst: TECLKSYNC4_1 ECLKI
#[V]rgn:     8
#[V]dst: TECLKSYNC4_2 ECLKI
#[V]rgn:     8
#[V]dst: TECLKSYNC4_3 ECLKI
#[V]rgn:     8
#[V]dst: TECLKSYNC5_0 ECLKI
#[V]rgn:     10
#[V]dst: TECLKSYNC5_1 ECLKI
#[V]rgn:     10
#[V]dst: TECLKSYNC5_2 ECLKI
#[V]rgn:     10
#[V]dst: TECLKSYNC5_3 ECLKI
#[V]rgn:     10
#[V]dst: TECLKSYNC6_0 ECLKI
#[V]rgn:     12
#[V]dst: TECLKSYNC6_1 ECLKI
#[V]rgn:     12
#[V]dst: TECLKSYNC6_2 ECLKI
#[V]rgn:     12
#[V]dst: TECLKSYNC6_3 ECLKI
#[V]rgn:     12
[V]dst: TPLL2 CLKI
[V]rgn:     6
[V]dst: TPLL3 CLKI
[V]rgn:     8
[V]dst: TPLL4 CLKI
[V]rgn:     8
[V]dst: TPLL5 CLKI
[V]rgn:     10
[V]dst: TPLL6 CLKI
[V]rgn:     10
[V]dst: TPLL7 CLKI
[V]rgn:     12
[V]dst: TPLL8 CLKI
[V]rgn:     12
#[V]dst: TPLL2 CLKFB
#[V]rgn:     6
[V]dst: TPLL2 WBCLK
[V]rgn:     6
#[V]dst: TPLL3 CLKFB
#[V]rgn:     8
[V]dst: TPLL3 WBCLK
[V]rgn:     8
#[V]dst: TPLL4 CLKFB
#[V]rgn:     8
[V]dst: TPLL4 WBCLK
[V]rgn:     8
#[V]dst: TPLL5 CLKFB
#[V]rgn:     10
[V]dst: TPLL5 WBCLK
[V]rgn:     10
#[V]dst: TPLL6 CLKFB
#[V]rgn:     10
[V]dst: TPLL6 WBCLK
[V]rgn:     10
#[V]dst: TPLL7 CLKFB
#[V]rgn:     12
[V]dst: TPLL7 WBCLK
[V]rgn:     12
#[V]dst: TPLL8 CLKFB
#[V]rgn:     12
[V]dst: TPLL8 WBCLK
[V]rgn:     12
#[V]dst: TPLLREFCS2 CLK0
#[V]rgn:     6
#[V]dst: TPLLREFCS2 CLK1
#[V]rgn:     6
#[V]dst: TPLLREFCS3 CLK0
#[V]rgn:     8
#[V]dst: TPLLREFCS3 CLK1
#[V]rgn:     8
#[V]dst: TPLLREFCS4 CLK0
#[V]rgn:     8
#[V]dst: TPLLREFCS4 CLK1
#[V]rgn:     8
#[V]dst: TPLLREFCS5 CLK0
#[V]rgn:     10
#[V]dst: TPLLREFCS5 CLK1
#[V]rgn:     10
#[V]dst: TPLLREFCS6 CLK0
#[V]rgn:     10
#[V]dst: TPLLREFCS6 CLK1
#[V]rgn:     10
#[V]dst: TPLLREFCS7 CLK0
#[V]rgn:     12
#[V]dst: TPLLREFCS7 CLK1
#[V]rgn:     12
#[V]dst: TPLLREFCS8 CLK0
#[V]rgn:     12
#[V]dst: TPLLREFCS8 CLK1
#[V]rgn:     12
