<?xml version="1.0" ?>
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	<! i:info e:error w:warning f:fatal h:hint n:note>
	<!ELEMENT messages ((i|e|w|f)+)>
	<!ELEMENT i (#PCDATA)>
	<!ATTLIST i id CDATA #REQUIRED>
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	<!ATTLIST e id CDATA #REQUIRED>
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	<!ATTLIST w id CDATA #REQUIRED>
	<!ELEMENT f (#PCDATA)>
	<!ATTLIST f id CDATA #REQUIRED>
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<messages>
	<p id="ANY-1">%s</p>
	<!-- Info messages -->
	<i id="STWL-1">Set work library to be %s</i>
	<i id="STTD-1">Set top design to be /%s/%s</i>
	<i id="HQTM-1">%s</i>
	<i id="HQLP-1">Launching program %s</i>
	<i id="HQIN-1">HqFpga is ready to work on host %s (%s)</i>
	<i id="MAP-1">Start technology mapping </i>
	<i id="MAP-2">Done technology mapping </i>
	<i id="MAP-3">Map report has been written to file %s</i>
	<i id="PR-1">Start placement and routing </i>
	<i id="PR-2">Done placement and routing </i>
	<i id="PL-1">Start placement</i>
	<i id="PL-2">Done placement</i>
	<i id="PL-3">Netlist report has been written to file %s</i>
	<i id="HQTM-2">Program terminating at %s</i>
	<i id="HQRT-1">Total runtime is %s seconds</i>
	<i id="HQMU-1">Peak memory consumption is %s </i>
	<i id="UCTM-0">Runtime of executing U-command "%s" is %.2fs </i>
	<i id="SAVE-0">Saving design to file %s</i>
	<i id="SAVE-1">Design saved successfully</i>
	<i id="LOAD-0">Loading design from file %s</i>
	<i id="LOAD-1">Design loaded successfully</i>
	<e id="LOAD-2">Invalid file format for loading design data</e>
	<i id="LANG-1">Language set successfully</i>
	<i id="LOG-0">Output logging is switched to directory %s </i>
	<i id="EXT-0">(NOTE: using third-party tool %s)</i>
	<i id="LO-00"><![CDATA[    Total number of literals before LO: %s]]> </i>
	<i id="LO-0"><![CDATA[    Number of literals before LO: %s]]> </i>
	<i id="LO-1"><![CDATA[    LO loop %s : number of literals from %s to %s]]> </i>
	<i id="LO-2"><![CDATA[    Number of literals after LO: %s]]> </i>
	<i id="LO-3"><![CDATA[  Logic optimization on view : %s]]> </i>
	<i id="LO-4"><![CDATA[  Slack before TDO: %s]]> </i>
	<i id="LO-5"><![CDATA[  Slack after  TDO: %s]]> </i>
	<i id="LO-6"><![CDATA[  Re-do literal optimization]]> </i>
	<i id="LO-7A">Start register CE and data co-optimization</i>
	<i id="LO-7B">Done register CE and data co-optimization</i>
	<i id="LO-8A">Start logic decomposition</i>
	<i id="LO-8B">Done logic decomposition</i>
	<i id="LO-9A">====&gt; Start basic logic reduction</i>
	<i id="LO-9B">----&gt; Reduced %d instances, continue round %d of basic logic reduction</i>
	<i id="LO-9C">&lt;==== Done basic logic reduction, totally reduced %d instances</i>

	<i id="IOH-0">IO pullmode is set as : %s</i>
	<!-- runtime messages -->
	<i id="RTLO-0">Logic optimization total runtime : %s seconds</i>
	<i id="RTLO-1">Timing driven optimization total runtime : %s seconds</i>
	<i id="RTLO-2">Area and timing driven logic optimization total runtime : %s seconds</i>
	<i id="RTUM-0">Unmapping total runtime : %s seconds</i>
	<i id="RTMP-0">Technology mapping total runtime : %s seconds</i>
	<i id="RTPK-0">Packing total runtime : %s seconds</i>
	<i id="RTPL-0">Placement total runtime : %s seconds</i>
	<i id="RTRT-0">Routing total runtime : %s seconds</i>
	<i id="RTDA-0">Design analysis total runtime : %s seconds</i>
	<i id="RTDS-0">RTL synthesis total runtime : %s seconds</i>
	<i id="RTLM-0">Timing driven optimization and mapping total runtime : %s seconds</i>
	<i id="RTBG-0">Bitstream generation total runtime : %s seconds</i>
	<i id="NOFUNC-001">Required function is not available in this build</i>

	<!-- step messages -->
	<i id="STLO-0">Start logic optimization</i>
	<i id="STLO-1">Done logic optimization</i>
	<i id="STLO-3">Start timing driven optimization</i>
	<i id="STLO-4">Done timing driven optimization</i>
	<i id="STLO-5"><![CDATA[  No timing constraints applied, skip TDO]]></i>
	<i id="STBGEN-500"><![CDATA[
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!
! This build is for EVALUATION purpose, Xilinx ISE tool will be
! invoked to do bitstream generation
!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	]]></i>
	<i id="STBGEN-501">Done bitstream generation using Xilinx ISE tool</i>
	<p id="STBGEN-701"><![CDATA[==== Generated bitstream files  ====
binary format bitstream file   : %s
reversed binary bitstream file : %s
]]></p>
	<p id="STBGEN-705">Unable to view binary format bitstream file %s, please open it with other tools</p>
	<p id="STBGEN-710">Unable to view reversed binary format bitstream file %s, please open it with other tools</p>

	<!-- GUI Info messages 'begin' -->
	<i id="GUI-1">Start a gui_Server in port %s</i>
	<i id="GUI-2">Accept %s from %s port %s</i>
	<i id="GUI-3">close $sock</i>
	<i id="GUI-4">Disconnect with gui interface of hqui</i>
	<i id="GUI-5">Using 'gui.run' to rerun the interface</i>
	<!-- GUI Info messages 'end'-->

	<!-- Error messages -->
	<e id="MSG-0">Message %s is not defined</e>
	<i id="MSG-1">... Message %s is set to appear no more than %d times, skipping successive same message</i>
	<e id="LANG-0">Language "%s" is not supported </e>
	<e id="CMD-0">Invalid command name "%s"</e>
	<e id="VAR-1">Error assigning variable %s </e>

	<!-- 	Error messages related with argument handling  -->
	<e id="ARGF000">Invalid argument format: %s</e>
	<e id="ARGF002">No argument type found in argument format string [%s]</e>
	<e id="ARGF003">Invalid argument type &lt;%s&gt; in argument format string [%s]</e>
	<e id="ARGF004">Invalid type detail format in argument format string [%s].</e>
	<e id="ARGF005">Type detail is empty in argument format string [%s]</e>
	<e id="ARGF006">Default value is empty in argument format string [%s]</e>
	<e id="ARGF007">A required argument with multiple occurrences must be the last required argument</e>
	<e id="ARGF008">Recursive argument should not have default value, in argument format string [%s]</e>
	<e id="ARGF009">Argument [%s]'s value "%s" is not of type [%s]</e>
	<e id="ARGF010">Value "%s" is not valid for argument [%s] whose value must be one of [%s]</e>
	<e id="ARGF011">[%s] does not match format of sub-argument of %s</e>
	<e id="ARGF012">Argument [%s] is not defined</e>
	<e id="ARGF013">No value is specified for argument [%s]</e>
	<e id="ARGF014">Argument [%s] can not have multiple occurrences</e>
	<e id="ARGF015">Syntax error of argument [%s], &apos;(&apos; or &apos;=&apos; expected</e>
	<e id="ARGF016">Syntax error of argument [%s], &apos;=&apos; expected</e>
	<e id="ARGF017">Unexpected argument value %s</e>
	<e id="ARGF018">Redefinition of argument [%s]</e>
	<e id="ARGF019">Meet unexpected character &apos;%c&apos; in argument format string [%s]</e>
	<e id="ARGF020">Invalid enum value format "%s" in argument format string [%s]</e>
	<e id="ARGF021">Number of &apos;%c&apos;s and &apos;%c&apos;s do not match</e>
	<e id="ARGF022">No value is specified for required argument [%s]</e>
	<e id="ARGF023">Arguments [%s] and [%s] are mutual exclusive </e>
	<e id="ARGF024">Only after argument [%s] is specified can argument [%s] be specified</e>
	<e id="ARGF025">An optional positional argument with multiple occurrences must be last optional positional argument</e>
	<e id="ARGF026">An optional positional argument should not appear before requirement argument(s)</e>
	<e id="ARGF027">A required argument with multiple has been defined, no optional positional argument may appear </e>
	<e id="ARGF028">Argument [%s] must be specified based on the context of command</e>
	<e id="ARGF029">Argument [%s]'s value "%s" is invalid</e>
	<e id="ARGF030">Argument [%s] must NOT be specified based on the context of command</e>
	<e id="ARGF031">Either argument [%s] or argument [%s] should be specified </e>
	<e id="ARGF032">When argument [%s] is specified, argument [%s] should also be specified </e>
	<e id="ARGF033">The value of argument [%s] must be no less than %d</e>
	<e id="ARGF034">"%s" is not in a valid list format</e>
	<e id="ARGF035">The value of argument [%s] should not be empty</e>
	<e id="ARGF036">Argument [%s] conflicts with argument [%s]</e>
	<e id="ARGF037">"%s" is not applicable to &lt;%s&gt; object</e>
	<e id="ARGF038">"%s" is only applicable to &lt;%s&gt; object</e>
	<e id="ARGF039">Command(or argument) "%s" is not supported by current device</e>

	<p id="ARGP-0">[U-command]\n    %s</p>
	<p id="ARGP-1">[Syntax]</p>
	<p id="ARGP-2">[Arguments]</p>
	<p id="ARGP-3">enumerated integer double string recursive switch object_reference</p>
	<p id="ARGP-4"> <![CDATA[o %s
    type: %s
    default value: %s ]]></p>

	<e id="UCMD000">There's no U-command named %s</e>
	<e id="UCMD005">Met unhandled exception when processing command :</e>

	<!-- 	Error messages related with file handling  -->
	<e id="FILE000">Failed to locate output directory to [%s]</e>
	<e id="FILE001">Unable to read file %s</e>
	<e id="FILE002">Unable to write file %s</e>
	<e id="FILE003">Unable to find/open file %s</e>
	<e id="FILE004">File %s doesn't exist</e>
	<e id="FILE005">Failed to write anything into output directory [%s]</e>
	<e id="FILE500">Error encrypting file %s</e>
	<e id="FILE501">Error decrypting file %s</e>
	<e id="FILE502">Error generating license file %s</e>
	<e id="FILE503">Error decrypting license file %s</e>
	<e id="FILE600">Unable to locate bitstream generator</e>
	<e id="FILE601">Unable to locate FPGA programmer/downloader</e>
	<e id="FILE605">Unable to locate HqInsight Instrumentor</e>
	<e id="FILE610">Unable to locate HqInsight Debugger</e>
	<e id="FILE615">Unable to locate IP Creator</e>
	<e id="FILE616">Unable to locate Netlist Viewer</e>
	<e id="FILE617">Unable to locate Design Explorer</e>

	<!-- 	Error messages related with object handling  -->
	<e id="FOBJ001">There's no library named %s </e>
	<e id="FOBJ002">Wrong object hierarchical name : "%s"</e>
	<e id="FOBJ003">Top view is NULL </e>
	<e id="FOBJ004">%s-type of object "%s" does not own instance objects</e>
	<e id="FOBJ005">In nview "%s", there's no instance named "%s"</e>
	<e id="FOBJ006">Unable to find net in a non-nview object "%s"</e>
	<e id="FOBJ007">In nview "%s", there's no net named "%s"</e>
	<e id="FOBJ008">Unable to find port in a non-cell object "%s"</e>
	<e id="FOBJ009">On cell "%s", there's no port named "%s"</e>
	<e id="FOBJ010">Unable to find primary in a non-nview object "%s"</e>
	<e id="FOBJ011">On view "%s", there's no primary pin named "%s"</e>
	<e id="FOBJ012">Unable to find pin in a non-instance object "%s"</e>
	<e id="FOBJ013">On instance "%s", there's no pin named "%s"</e>
	<e id="FOBJ014">Unable to find pin or port in object "%s" whose type is %s</e>
	<e id="FOBJ015">In library "%s", there's no cell named "%s"</e>
	<e id="FOBJ016">Cell "%s" does not have a view named "%s"</e>
	<e id="FOBJ017">In the subnetlist of instance "%s", there's no instance named "%s"</e>
	<e id="FOBJ018">%s-type of object "%s" does own lower level instances</e>
	<e id="FOBJ019">The referenced object "%s" is not a %s object </e>
	<e id="FOBJ020">Type of object "%s" should be library or view </e>
	<e id="FOBJ021">Pin/port index %d is out of range (0-%d)</e>
	<e id="FOBJ022">In implicant string "%s", literal value "%s" is invalid</e>
	<e id="FOBJ023">In nview "%s", there's no instance or net named "%s" </e>
	<e id="FOBJ024">Attempting to get empty object</e>
	<e id="FOBJ900">Unable to find object(s) matching name pattern "%s"</e>
	<e id="FOBJ901">Invalid name pattern "%s"</e>
	<e id="FOBJ902">%s type of object "%s" is invalid to be used here</e>
	<e id="FOBJ903">Unable to find ports matching pattern "%s"</e>
	<e id="FOBJ904">Unable to find instances matching pattern "%s"</e>
	<e id="FOBJ905">Unable to find nets matching pattern "%s"</e>
	<e id="FOBJ906">Unable to find pins matching pattern "%s"</e>
	<e id="FOBJ907">Unable to find ports or pins matching pattern "%s"</e>
	<e id="FOBJ908">Unable to find ports/pins/instances/nets matching pattern "%s"</e>
	<e id="FOBJ909">Unable to find pins/instances/nets matching pattern "%s"</e>
   	<e id="FOBJ910">Meet unexpected tribuf instance at map stage</e>

	<!-- 	Error messages related design  -->
	<e id="DSGN000">No netlist to apply the specified operation</e>
	<e id="DSGN005">Problem encountered somewhere in the above process, please search ERROR-like messages and check</e>
    <e id="FLOW002">Hierarchy structure info is destroyed, unflatten failed </e>
    <e id="EXTC001">Instance %s(%s) is not applicable to target device </e>
    <e id="DEVX300">Please setup target device first</e>
    <e id="DEVX301">Cell %s is invalid for target device</e>

	<!-- 	Error messages related with xdata handling  -->
	<e id="XDATA000">Object "%s", unable to retrieve parameter/property named "%s"</e>
	<e id="XDATA005">Instance %s(%s), unable to retrieve parameter/property named "%s"</e>
	<e id="XDATA-301">Instance %s(%s), parameter "%s" : type is [%s], while [%s] is expected</e>
	<e id="XDATA-305">Instance %s(%s), parameter "%s" : value "%s" is invalid</e>
	<p id="XDATA-305A"><![CDATA[  +--> Valid values: {%s}]]> </p>
	<e id="XDATA-310">Instance %s(%s), parameter "%s" : value %s exceeds bit-size limit (%d vs %d)</e>
	<e id="XDATA-315">Instance %s(%s), parameter "%s" : value %s exceeds range [%s %s]</e>
	<e id="XDATA-320">Instance %s(%s), parameter "%s" : value %s is out of %d-bit range </e>
	<e id="XDATA-325">Instance %s(%s), parameter "%s" : value %s is not a valid %d-bit number </e>

	<i id="COBJ-1">Created library %s</i>

	<!-- Retired error messages
		<e id="ARGF001">Only one (the last) required argument can have multiple occurrences</e>
	 -->
	<e id="UDM001">Unable to recognize cell /%s/%s</e>
	<e id="UDM005">Cell %s: port %s is undefined</e>

	<e id="UDM010">Instance "%s" in container Nview "%s", but deleted in other Nview "%s"</e>

	<w id="UDM900">In library %s, cell %s, changed port %s's direction to %s </w>
	<w id="UDM901">Reading an older version (%s) of design database, latest version is %s</w>

	<!-- 	Physical constraint handling  -->
	<i id="UPCR-0">Reading UPC file %s ...</i>
	<i id="UPCR-1">End of reading UPC</i>
	<i id="UPCR-0A">Checking physical constraint ...</i>
	<i id="UPCR-1A">Done</i>
	<w id="UPCR-2">Clear previous User Physical Constraint</w>
	<e id="UPC900"><![CDATA[Invalid IO attribute string : "%s"
   Attribute string must be in list format ]]></e>
	<e id="UPC901"><![CDATA[Invalid IO attribute string : "%s"
   Each item should be in <name>=<value> format ]]></e>

    <!-- 	Timing analysis/constraint handling  -->
	<i id="SDCR-0">Reading SDC file %s ...</i>
	<i id="SDCR-1">End of reading SDC</i>
	<i id="SDCR-0A">Checking timing constraints ...</i>
	<i id="SDCR-1A">Done</i>

	<e id="SDC900">At command [%s]</e>
	<e id="SDC901">Error reading SDC</e>
	<e id="SDC000">SDC commands should be read in from a SDC file by "sdc.read" command, or should be used in between "sdc.start" and "sdc.end" commands </e>
	<e id="SDC001">Object "%s" is not of type Nview </e>
	<e id="SDC002">Currently there's no netlist to apply SDC</e>
	<e id="SDC003">Invalid mode list string "%s" </e>
	<e id="SDC004">Mode "%s" is not defined </e>
	<e id="SDC005">Net "%s" is undriven and can not be set as clock source </e>
	<e id="SDC006">Invalid format of %s list {%s}</e>
	<e id="SDC007">Clock waveform {%s} should contain even number of edges </e>
	<e id="SDC008">The %s list {%s} should only contain values with type %s</e>
	<e id="SDC009">The edges in clock waveform {%s} are not monotonically increasing</e>
	<e id="SDC010">The number of edges must be an odd number and not less than 3</e>
	<e id="SDC011">The edges {%s} are not monotonically increasing</e>
	<e id="SDC012">The number of edge_shifts must be equal to that of edges</e>
	<e id="SDC013">Only one master clock source pin can be specified</e>
	<e id="SDC014">Unable to find master clock with name "%s"</e>
	<e id="SDC015">Unable to find clock(s) with name pattern "%s"</e>
	<e id="SDC016">No clocks have been created, unable to apply constraint</e>
	<e id="SDC017">Only one argument of "%s" can be used</e>
	<e id="SDC018">Unable to find clocks, ports, pins or instances matching pattern "%s"</e>
	<e id="SDC018A">Unable to find clocks, ports or pins matching pattern "%s"</e>
	<e id="SDC019">Wrongly use output port(s) in "-from" side of path constraint</e>
	<e id="SDC020">Wrongly use input port(s) in "-to" side of path constraint</e>
	<e id="SDC021">Unable to find pins, ports, instances or nets matching pattern "%s"</e>
	<e id="SDC022">Unable to find ports, pins, or nets matching pattern "%s"</e>
	<e id="SDC023">The number of edges should not exceed %d</e>
	<e id="SDC024">Clock waveform {%s} should not contain two or more edges with time large than clock period</e>
	<e id="SDC025">Clock waveform {%s} contain a negative edge time</e>
	<e id="SDC026">Wrongly set input delay to output port(s)</e>
	<e id="SDC027">Wrongly set output delay to input port(s)</e>
	<e id="SDC028">Argument [object_list] should not refer to clock object(s) when [clock] argument is specified</e>
	<e id="SDC029">Clock source latencies can only be set on clocks or clock source pins</e>
	<e id="SDC030">Clock waveform {%s} contains an invalid edge time: %s </e>
	<e id="SDC031A">Clock waveform {%s} contains abnormal high pulse (width >= clock period)</e>
	<e id="SDC031B">Clock waveform {%s} contains abnormal low pulse (width >= clock period)</e>
	<e id="SDC032A">Met unexpected character(s) preceding object command "[%s]"</e>
	<e id="SDC032B">Met unexpected character(s) succeeding object command "[%s]"</e>
	<e id="SDC500">Command is not supported in this build</e>
	<e id="SDC501">Argument %s is not supported in this build</e>
	<i id="SDC701">Ignored %d tc.synclcoks.set constraint(s) due to existances of set_clock_groups constraint(s)</i>
	<i id="SDC705">Set synchronous relationship for clocks below -- </i>
	<p id="SDC705A"><![CDATA[  %s
]]></p>
	<e id="TC005">Invalid clock list string "%s" appeas in constraint above</e>
	<w id="TC505">Clock list should contain at lease two clocks, constraint above is ignored</w>
	<w id="TC510">Clock "%s" is specified multiple times in constraint above, only one is kept effective</w>
	<p id="TC800"><![CDATA[  %s
]]></p>

	<w id="TCLK001">Found more than one master clocks for generated clock "%s", select "%s" as master clock</w>
	<w id="TCLK002">Unable to figure out master clock for generated clock "%s" (disabled)</w>

	<e id="TA001">Netlist is empty, unable to do timing analysis or report</e>
	<e id="TA002">Undefined timing mode : "%s"</e>
	<e id="TA003">Reserved timing mode "%s" should not be used here</e>
	<e id="TA004">Timing mode "%s" is not active for reporting timing</e>
	<e id="TA005">"%s" is not a valid field when reporting timing path</e>
	<e id="TA006">Field should not be empty when reporting timing path</e>
	<e id="TA007">Unable to find clock named "%s"</e>
	<e id="TA008">Invalid clock name format "%s"</e>
	<e id="TA010">Found combinational loop along clock path</e>
	<e id="TA015">Unable to break comb-loop </e>

	<w id="TA601">Inside physical instance %s(%s), fail to correlate timing on pin %s(%s).%s </w>
	<w id="TA605">Ignored abnormal clock skew (%s) when calculating FMAX for clock %s </w>
	<p id="TA605A">-- This indicates a high risk of hold violation</p>
	<w id="TA901">Design contains combinational loop(s), which has(have) been broken:</w>
	<p id="TA902">======= Combinational loop %d ========</p>

	<i id="TC001">Timing constraint already exists, skip timing constraint auto-generation</i>
	<i id="TC002">Force overwriting existing timing constraint </i>
	<i id="TC101">Deriving constraint: %s </i>
	<w id="TC501">Failed to derive output clock information for instance "%s(%s)" </w>

	<e id="TM000">Invalid -adjust string "%s"</e>
	<e id="TM001">Unable to get adjust value from "%s"</e>
	<e id="TM002">Invalid delay format "%s"</e>
	<e id="TM003">Adjust delay "%s" does not match base delay "%s" in terms of format</e>

	<w id="TCLK501">Found clock(s) without user-specified constraint, please double check..</w>
	<w id="TCLK501A">Found unconstrained clock(s) in analysis above, please double check</w>
	<w id="TCLK901">Previously defined clock "%s" will be overwritten</w>
	<w id="SDC300">On port "%s", previous %s setting is overwritten by the constraint below</w>
	<w id="SDC301">On pin "%s", previous %s setting is overwritten by the constraint below</w>
	<w id="SDC302">Unable to find paths for calculating source latency of generated clock "%s", zero clock source latency is used</w>
	<w id="SDC303">Ignored input delay set on clock port "%s" by the constraint below</w>
	<w id="SDC304">Argument "level_sensitive" is currently not supported, ignored from constraint below</w>
	<w id="SDC310"><![CDATA[In constraint below, clock "%s" appears in more than one clock groups, only the first occurrence is effective:
  %s
]]> </w>

	<!-- 	HqInsight/IP Creator/Downloader/Netlist Viewer/Design Explorer Messages  -->
	<e id="HQINS001">HqInsight IP instrumentation hasn't completed</e>
	<i id="HQINS-1">Launching HqInsight Instrumentor ...</i>
	<i id="HQINS-2">Launching HqInsight Debugger ...</i>
	<i id="HQINS-VIO-1">Launching VIO Debugger ...</i>
	<i id="DNLD-1">Launching bitstream downloader ...</i>
	<i id="IPC-1">Launching IP Creator ...</i>
	<i id="NLV-1">Launching Netlist Viewer ...</i>
	<i id="DSXP-1">Launching Design Explorer ...</i>

	<!-- 	Header Messages  -->
	<p id="CPYT000">
	<![CDATA[
==========oOOOo===========================================oOOOo==========
=  HqFpga(TM) V%s Build %s
=  Unified FPGA platform solutions
=  Uptops Design Technologies, Inc. (www.uptops-dt.com)    _@)
 _________________________________________________________/ (
<_________________________________________________________  {}@8@@8@(*)
                                                          \_(
=  Copyright (c) 2008-2014 UDT, Inc.                        @)
=  All rights reserved.
=========================================================================
]]>
	</p>

	<p id="CMDH000">
	<![CDATA[[Hint]
Type "help <U-Command>" to get help text on that specific command,
Type "help all" to get a list of all U-commands.
]]>
	</p>

	<p id="HELP000">
	<![CDATA[
[Syntax]
   HQFPGA   [-cmd <script_file>]
            [-outdir <output_directory>]
            [-log <log_file_name>]
            [-lang <language>]
            [-help]

[Arguments]
o cmd
    When specified, HQFPGA will run in batch mode by executing the commands
    in the named script file. (By default HQFPGA runs in interactive mode).
o outdir
    By default HQFPGA outputs files (log file, netlist file, ...etc) in the
    directory where HQFPGA is launched. This argument can be used to specify
    a different directory where to output files.
o log
    By default HQFPGA logs messages in the file "hqfpga.log" in the directory
    of <outdir>. This argument can be used to specify a different log file
    name.
o lang
    Language selection, must be one of the following values:
        "eng"  -- English
        "chs"  -- Simplified Chinese
        "jpn"  -- Japanese
    HQFPGA uses English as default language.
o help
    Print out help messages.

[Example]
        hqfpga -log my.log -lang chs -outdir d:/mydir
    Run HQFPGA with language simplified Chinese, output all files to directory
    d:/mydir, logfile is named "my.log"

]]>
    </p>


	<p id="MRPT000">
	<![CDATA[
##########oOOOo###########oOOOo##############
#  HqFpga(TM) Release V%s Build %s
#  [Resource Utilization Report]
#############################################
Date   : %s
Device : %s

** Device Utilization Summary  ** ]]>	</p>

	<p id="RSRPT000">
	<![CDATA[
##########oOOOo###########oOOOo##############
#  HqFpga(TM) Release V%s Build %s
#  [Region Resource Utilization Report]
#############################################
Date   : %s
Device : %s

]]>	</p>
	<p id="RSRPT001">
	<![CDATA[
******************************************************
** Region %d Utilization Summary
******************************************************
** R%dC%d--R%dC%d
]]>	</p>

	<p id="MRPT001">+---------------------------+-------------+-------------+-------------+</p>
	<p id="MRPT002">|  %-26s| %-12s| %-12s| %-12s|</p>
	<p id="MRPT900">{Resource Type} {Used} {Available} {Ratio(%%)}</p>
	<p id="MRPT903">IOB SLICE LUT Flip-Flop Block-RAM Multiplier DSP {Global Clock}</p>

	<p id="URPT000">
	<![CDATA[
##########oOOOo###########oOOOo##############
#  HqFpga(TM) Release V%s Build %s
#  [Resource Perspective Report]
#############################################
Date         : %s
Device       : %s
Design       : %s
Design State : %s

** Resource Perspective Report **
]]>	</p>
	<p id="URPT001">Table of Contents</p>
	<p id="URPT002">Synthesized Packed</p>
	<p id="URPT003">{BL}  {Slice LUTs}
					{SLD} {Slice Logic Distribution}
					{MEM} {Memory}
					{DSP} {DSP}
					{IO}  {IO}
					{CLK} {Clocking}
					{SP}  {Function Block}
					{PRM} {Primitives}
					{BB}  {Black Boxes}
					{NL}  {Instantiated Netlists}</p>
	<p id="URPT005"><![CDATA[{LUT} 	{LUTs}
					{LUTL} 	{  LUT as Logic}
					{LUTM} 	{  LUT as Memory}
					{LUTS} 	{  LUT as Shift Register}
					{LUTC} 	{  LUT in Carry Chain}
					{FFLAT} {Registers}
					{FF} 	{  Register as Flip Flop}
					{LAT} 	{  Register as Latch}]]>
					</p>
	<p id="URPT006"><![CDATA[
					{SLICE} 	{Slice}
					{SLLOGIC} 	{  LOGIC}
					{SLRIPPLE} 	{  RIPPLE}
					{SLCCU} 	{  CCU2}
					{SLRAMD} 	{  RAMD}
					{SLICEL} 	{  SLICEL}
					{SLICEM} 	{  SLICEM}
					{LUT} 		{Slice LUTs}
					{LUTL} 		{  LUT as Logic}
					{LUTL5} 	{    using O5 output only}
					{LUTL5P5} 	{      O5 as pass-through}
					{LUTL6} 	{    using O6 output only}
					{LUTL6P6} 	{      O6 as pass-through}
					{LUTL56} 	{    using O5 and O6}
					{LUTL56P5} 	{      O5 as pass-through}
					{LUTL56P6} 	{      O6 as pass-through}
					{LUTL56P56} {      both as pass-through}
					{LUTM} 		{  LUT as Memory}
					{LUTMD} 	{    LUT as Distributed RAM}
					{LUTMD5} 	{      using O5 output only}
					{LUTMD6} 	{      using O6 output only}
					{LUTMD56} 	{      using O5 and O6}
					{LUTMS} 	{    LUT as Shift Register}
					{LUTMS5} 	{      using O5 output only}
					{LUTMS6} 	{      using O6 output only}
					{LUTMS56} 	{      using O5 and O6}
					{FFLAT} 	{Slice Register}
					{REGFF} 	{  Slice Register as Flip Flop}
					{REGLAT} 	{  Slice Register as Latch}
					{REGLATP} 	{    Latch as pass-through}
					{F7}		{F7 Muxes}
					{F8}		{F8 Muxes}
					{CARRY}		{Slice Carry Chain}
					]]>
					</p>
	<p id="URPT007"><![CDATA[
					{BRAM} 		{Block RAM}
					{RAMB9K} 	{Block RAM (9K-based)}
					{RAMB18K} 	{Block RAM (18K-based)}
					{BRAM9} 	{  RAMB9K}
					{BRAM18} 	{  RAMB18K}
					{BRAM36} 	{  RAMB36K}
					{SPRAM1KX32} {Single-Port RAM 1Kx32}
					]]></p>
	<p id="URPT008"><![CDATA[
					{PRADD} 	{Pre-Adder}
					{PRADD9} 	{  PRADD9 (half DSP-PRADD)}
					{PRADD18} 	{  PRADD18}
					{MULT} 		{Multiplier}
					{MULT9} 	{  MULT9 (half DSP-MULT)}
					{MULT18} 	{  MULT18}
					{ALU} 		{Arithmetic Logic Unit}
					{ALU24} 	{  ALU24 (half DSP-ALU)}
					{ALU54} 	{  ALU54}
					]]></p>
	<p id="URPT009"><![CDATA[
					{IOB} 		{I/O Block}
					{PIO} 		{Programmable I/O}
					{IOREG} 	{I/O Register}
					{IOLOGIC} 	{I/O Logic Controller}
					{IREG} 		{  Input Register}
					{OREG} 		{  Output Register}
					{TREG} 		{  Tri-state Register}
					]]></p>
	<p id="URPT010">{PLL} 	{Phase-Locked Loop}
					{DQS} 		{Data Strobe}
					{DQSDLL} 	{QDS DLL}
					{DDRDLL} 	{DDR DLL}</p>
	<p id="URPT011">{CEM} 	{Embedded Function Block}
					{DDRCTRL} 		{DDR Controller}
					{SERDES_COM} 	{SerDes COM}
					{SERDES_CH} 	{SerDes Channel}</p>

	<p id="NRPT000">
	<![CDATA[
######################oOOOo###########oOOOo##########################
#  HqFpga(TM) Release V%s Build %s
#  [Netlist Report]
#####################################################################
Date   : %s]]>   </p>
    <p id="NRPT900">{Cell Name} {Count}</p>
	<p id="NRPT600">DUMMY IOB LUT {FF/Latch} {Global-Clock} {Block-RAM} {Multiplier} {DSP} {CLKDLL} {DCM}</p>
	<p id="NRPT600-M5">DUMMY IOC LUT LUT4C Register EMB MAC PLL MCU SRAM</p>
	<i id="NRPT300">No specific device is set, unable to report resource utilization ratio</i>
	<i id="NRPT302">No specific device is set, unable to report location information </i>
	<i id="NRPT305">Netlist is not mapped to target device, unable to report resource utilization ratio</i>
	<i id="NRPT306">Placement must complete before the region resource utilization ratio can be reported</i>
	<i id="NRPT307">Skip region report since current device has no clock regions</i>
	<e id="NRPT310">Check failed !</e>
	<!-- V5 resource-->
	<!--         DIE-DIE-PKG  IOB LUT   FFLAT      GBUF           BRAM       DSP DCM PLL-->
	<p id="NRPT-XC5V-1">DUMMY IOB LUT {FF/LATCH} {Global-Buffer} {BRAM/FIFO} DSP DCM PLL</p>
	<!--                  PKG IOB SLICE   GBUF          BRAM        DSP DCM PLL -->
	<p id="NRPT-XC5V-2">DUMMY IOB SLICE {Global-Buffer} {BRAM/FIFO} DSP DCM PLL</p>

	<!-- Sealion resources-->
	<!--                    IOB  LUT   FFLAT     IOREG         BRAM        MULT9 MULT18 ALU24 ALU54 PLL DQS DQSDLL CEM-->
	<p id="NRPT700-1">DUMMY IO  LUT  {Register} {IO-Register} {BLOCK-RAM}
					  {DSP-MULTIPLIER} { +- MULT9 (half DSP-MULT)} { +- MULT18} {DSP-ALU} { +- ALU24 (half DSP-ALU)} { +- ALU54}
					  PLL DQS DQSDLL CEM SPRAM1KX32</p>
	<p id="NRPT700-1C">DUMMY IO  LUT  {Register} {IOREG} {EBR}
					  MULT MULT.9b MULT.18b ALU ALU.24b ALU.54b
					  PLL DQS DQSDLL CEM SPRAM1KX32</p>
	<!--                    PIO SLICE IOLOGIC BRAM        MULT9 MULT18 ALU24 ALU54     PLL DQS DQSDLL CEM-->
	<p id="NRPT700-2">DUMMY PIO SLICE IOLOGIC { +- IREG} { +- OREG} { +- TREG} {BLOCK-RAM}
					  {DSP-MULTIPLIER} { +- MULT9 (half DSP-MULT)} { +- MULT18} {DSP-ALU} { +- ALU24 (half DSP-ALU)} { +- ALU54}
					  PLL DQS DQSDLL CEM SPRAM1KX32</p>
	<p id="NRPT700-2C">DUMMY PIO SLICE IOL {IOL.IREG} {IOL.OREG} {IOL.TREG} EBR
					  MULT MULT.9b MULT.18b ALU ALU.24b ALU.54b
					  PLL DQS DQSDLL CEM SPRAM1KX32</p>

    <!-- Seal resources-->
	<!--                    IOB  LUT   FFLAT     IOREG         BRAM        MULT9 MULT18 ALU24 ALU54 PLL DQS DDRDLL CEM-->
	<p id="NRPT700-3">DUMMY IO  LUT  {Register} {IO-Register}
					  {BLOCK-RAM(18K-Based)} {BLOCK-RAM(9K-Based)} { +- RAMB18K} { +- RAMB9K}  { +- RAMB36K}
					  {DSP-PRADD} { +- PRADD9 (half DSP-PRADD)} { +- PRADD18}
					  {DSP-MULTIPLIER} { +- MULT9 (half DSP-MULT)} { +- MULT18} {DSP-ALU} { +- ALU24 (half DSP-ALU)} { +- ALU54}
					  PLL DQS DDRDLL CEM DDRCTRL SERDES_COM SERDES_CH</p>
	<!-- for column header display in hierarchical resource repo -->
	<p id="NRPT700-3C">DUMMY IO  LUT  {Register} {IOREG}
					EBR EBR EBR.18K EBR.9K EBR.36K
					PRADD PRADD.9b PRADD.18b MULT MULT.9b MULT.18b ALU ALU.24b ALU.54b
 				    PLL DQS DDRDLL CEM DDRCTRL SERDES_COM SERDES_CH</p>

	<!--                    PIO SLICE IOLOGIC BRAM           BRAM9        BRAM36        MULT9 MULT18 ALU24 ALU54 PLL DQS DDRDLL CEM-->
	<p id="NRPT700-4">DUMMY IO SLICE IOLOGIC { +- IREG} { +- OREG} { +- TREG}
					  {BLOCK-RAM(18K-Based)} {BLOCK-RAM(9K-Based)} { +- RAMB18K} { +- RAMB9K}  { +- RAMB36K}
					  {DSP-PRADD} { +- PRADD9 (half DSP-PRADD)} { +- PRADD18}
					  {DSP-MULTIPLIER} { +- MULT9 (half DSP-MULT)} { +- MULT18} {DSP-ALU} { +- ALU24 (half DSP-ALU)} { +- ALU54}
					  PLL DQS DDRDLL CEM DDRCTRL SERDES_COM SERDES_CH LUT FFLAT</p>
	<p id="NRPT700-4C">DUMMY PIO SLICE IOL {IOL.IREG} {IOL.OREG} {IOL.TREG}
  					  EBR EBR EBR.18K EBR.9K EBR.36K
					  PRADD PRADD.9b PRADD.18b MULT MULT.9b MULT.18b ALU ALU.24b ALU.54b
					  PLL DQS DDRDLL CEM DDRCTRL SERDES_COM SERDES_CH LUT FFLAT</p>

    <p id="NRPT500">Hier Id</p>
    <p id="NRPT505">Hier Name</p>
	<h id="NRPT400">Design is flattened or not fully synthesized/implemented, skip hierarchical resource report</h>

	<p id="RRPT000">
	<![CDATA[
######################oOOOo###########oOOOo##########################
#  HqFpga(TM) Release V%s Build %s
#  [Resource Location Report]
#####################################################################
Date   : %s
Device : %s
]]>
</p>

	<p id="RRPT001">** IO Pin Assignment  **</p>
	<p id="RRPT002">** Instance Locations  **</p>
	<p id="RRPT003">** Bank Voltage Available  **</p>
	<p id="RRPT900">{Port Name} {Direction} {Pin Location} {IO Standard} {Bank}</p>
	<p id="RRPT900A">{Port Name} {Direction} {Pin Location} {IO Standard} {PULLMODE} {VCCIO} {Bank}</p>
	<p id="RRPT900B">{Port Name} {Direction} {Pin Location} {IO Standard} {Bank} {VCCIO} {DRIVE} {SLEWRATE} {PULLMODE} {In} {Out} {Tri}</p>
	<p id="RRPT901">{Instance Name} {Instance Type} {Location}</p>
	<p id="RRPT902">{Bank} {VCCIO}</p>
	<p id="RRPT903">{IO Pin Assignment} {Port Name} {Direction} {Pin Location} {IO Standard}</p>
	<p id="RRPT904">{Instance Locations} {Instance Name} {Instance Type} {Location}</p>
	<p id="RRPT905">+-------------------------------------+-----------------+-----------------+</p>
    <p id="RRPT906">|  %-36s| %-16s| %-16s|</p>

	<p id="DRPT000">Packing</p>
	<p id="DRPT001">Placement</p>
	<p id="DRPT002">Routing</p>
	<p id="DRPT003">TMR</p>
	<p id="DRPT004">Technology Mapping</p>
	<p id="DRPT005">Area And Timing Driven Logic Optimization</p>
	<p id="DRPT006">RTL Synthesis</p>
	<p id="DRPT007">Timing Driven Optimization And Mapping</p>
	<p id="DRPT008">Design Analysis</p>
	<p id="DRPT009">Bitstream Generation</p>

	<i id="SVRS-0">Saved</i>
	<i id="SVRS-1">Saving packing result.. </i>
	<i id="SVRS-2">Saving placement result.. </i>
	<i id="SVRS-3">Saving routing result.. </i>

	<!-- timing report messages -->
	<i id="TRPT300">No paths found</i>
	<w id="TAW000">There's no clock found in the design, please create clock for the design and restart the timing analysis</w>
	<w id="TAW001">There are non-path-end points found as by "-to" argument, clock specified by "-to_clk" will be ignored on those points</w>
	<p id="TRPT000">* Path %d</p>
	<p id="TRPT001">
	<![CDATA[
Slack : %s
From  : %s [launch  clock : %s, %s %d]
To    : %s [capture clock : %s, %s %d]
Type  : %s ]]>	</p>
	<p id="TRPT001M">
	<![CDATA[
Slack : %s
From  : %s
To    : %s
Type  : %s ]]>	</p>
	<p id="TRPT001F">
	<![CDATA[
From  : %s [launch  clock : %s, %s %d]
To    : %s [capture clock : %s, %s %d] ]]>	</p>
	<p id="TRPT002">[Data Launch Path]</p>
	<p id="TRPT003">NODE NET CELL DELAY AT RT SLACK TRANS LOC FO# TYPE</p><!--column title for display-->
	<p id="TRPT003-I">NODE NET CELL DELAY AT RT SLACK TRANS LOC FANOUT TYPE</p><!--internally-used fields-->
	<p id="TRPT003-D">NODE CELL DELAY AT TYPE LOC NET FANOUT</p><!--default report fields-->
	<p id="TRPT003-F">NODE CELL DELAY TYPE LOC NET FANOUT</p><!-- FMAX report fields-->
	<p id="TRPT004">[Data Capture Path]</p>
	<p id="TRPT005">[Slack Calculation]</p>
	<p id="TRPT006">[Delay Calculation]</p>
	<p id="TRPT013"><![CDATA[      = %s (VIOLATION!)]]></p>
	<p id="TRPT014"><![CDATA[      = %s]]></p>
	<p id="TRPT015-1"><![CDATA[Clock Path Delay     = %-10s (Tclkp)]]></p>
	<p id="TRPT015-2"><![CDATA[    clock-to-q Delay = %s]]></p>
	<p id="TRPT015-3"><![CDATA[    input Delay      = %s]]></p>
	<p id="TRPT015-4"><![CDATA[Data Path Delay      = %-10s (Tdatp)]]></p>
	<p id="TRPT015-5"><![CDATA[    total cell delay = %s]]></p>
	<p id="TRPT015-6"><![CDATA[    total wire delay = %s]]></p>
	<p id="TRPT015-7"><![CDATA[    logic Level      = %d]]></p>
	<p id="TRPT016"><![CDATA[TC    : %s ]]></p>
	<!-- max delay -->
    <p id="TRPT017">
        <![CDATA[Slack = Tmdly      - Tdatp      - %s
      = %-10s - %-10s - %-10s ]]></p>
    <p id="TRPT017A">
        <![CDATA[Slack = Tmdly      - Tdatp      - %-10s - Tcku
      = %-10s - %-10s - %-10s - %-10s ]]></p>
    <!-- min delay -->
    <p id="TRPT018">
        <![CDATA[Slack = Tdatp      - %-10s - Tmdly
      = %-10s - %-10s - %-10s ]]></p>
    <p id="TRPT018A">
        <![CDATA[Slack = Tdatp      - %-10s - Tmdly      - Tcku
      = %-10s - %-10s - %-10s - %-10s ]]></p>
    <!-- setup -->
    <p id="TRPT019">
        <![CDATA[Slack = Tcat       + Tckpm      - Tlat       - Tclkp      - Tdatp      - %s
      = %-10s + %-10s - %-10s - %-10s - %-10s - %-10s ]]></p>
    <p id="TRPT019A">
        <![CDATA[Slack = Tcat       + Tckpm      - Tlat       - Tclkp      - Tdatp      - Tcku       - %s
      = %-10s - %-10s - %-10s - %-10s - %-10s - %-10s - %-10s ]]></p>
    <!-- hold -->
    <p id="TRPT020">
        <![CDATA[Slack = Tlat       + Tckpm      + Tclkp      + Tdatp      - Tcat       - %s
      = %-10s + %-10s + %-10s + %-10s - %-10s - %-10s ]]></p>
    <p id="TRPT020A">
        <![CDATA[Slack = Tlat       + Tckpm      + Tclkp      + Tdatp      - Tcat       - Tcku       - %s
      = %-10s + %-10s + %-10s + %-10s - %-10s - %-10s - %-10s ]]></p>
    <!-- fmax -->
    <p id="TRPT021">
        <![CDATA[Total Delay = Tdatap     + Tsu        - Tckpm      - Tcksw
            = %-10s + %-10s - %-10s - %-10s ]]></p>
    <p id="TRPT021A">
        <![CDATA[Total Delay = Tdatap     + Tsu        - Tckpm      - Tcksw      + Tcku
            = %-10s + %-10s - %-10s - %-10s + %-10s]]></p>
    <p id="TRPT022"><![CDATA[            = %s]]></p>
	<!-- others -->
    <p id="TRPT200"><![CDATA[Tmdly -- Max/Min delay value ]]></p>
    <p id="TRPT201"><![CDATA[Tclkp -- Clock path delay ]]></p>
	<p id="TRPT202"><![CDATA[Tdatp -- Data Path delay ]]></p>
	<p id="TRPT203"><![CDATA[Tsu   -- Library setup time ]]></p>
	<p id="TRPT204"><![CDATA[Thd   -- Library hold time ]]></p>
	<p id="TRPT205"><![CDATA[Tcat  -- Data capture clock arrival time ]]></p>
	<p id="TRPT206"><![CDATA[Tlat  -- Data launch clock initial arrival time ]]></p>
	<p id="TRPT207"><![CDATA[Tod   -- Output delay ]]></p>
	<p id="TRPT208"><![CDATA[Tcku  -- Clock uncertainty, from constraint below: ]]></p>
	<p id="TRPT209"><![CDATA[Tcksw -- Clock skew]]></p>
	<p id="TRPT210"><![CDATA[Clock Path Delay     = %-10s]]></p>
	<p id="TRPT211"><![CDATA[      Clock Skew     = %s (with CPR = %s)]]></p>
   <p id="TRPT211A"><![CDATA[      Clock Skew     = %s (Tcksw)]]></p> <!-- for fmax report -->
	<p id="TRPT212"><![CDATA[Data Path Delay      = %-10s]]></p>
    <p id="TRPT220"><![CDATA[Tckpm -- Clock Pessimism ]]></p>
	<p id="TRPT900">rising edge</p>
	<p id="TRPT901">falling edge</p>
	<p id="TRPT903">Setup</p>
	<p id="TRPT903A">Recovery</p>
	<p id="TRPT904">Hold</p>
	<p id="TRPT904A">Removal</p>
    <p id="TRPT905">
		<![CDATA[
############################################################################
# Timing Analysis Report %s
############################################################################
#  Analysis type                                               : %s
#  Analyze/report paths between unconstrained IO and registers : %s
#  Analyze/report cross clock domain paths                     : %s
#  Analyze/report min pulse width checks                       : %s
#  Dynamic Loop Breaking during analysis                       : %s
#  Report timing nodes inside physical hierarchy               : %s
#  Report timing nodes on user hierarchical modules            : %s
#  Maximum number of paths to report                           : %s
#  Maximum number of paths to report on one checkpoint         : %s
#  Maximum number of paths to report from one path start point : %s ]]> </p>
    <p id="TRPT905A">
		<![CDATA[
#
#########################   [User Specified Path]   ########################
#  From    : %s
#  To      : %s
#  Through : %s
#  Exclude : %s ]]>	</p>
	<p id="TRPT905B">clock: %s</p>
	<p id="TRPT905C">Unlimited</p>
	<p id="TRPT905D">
		<![CDATA[
############################################################################
]]>	</p>
	<p id="TRPT906">MAXDELAY</p>
	<p id="TRPT907">MINDELAY</p>
	<p id="TRPT908">User specified path</p>
    <p id="TRPT909">
		<![CDATA[
# **************************************************************************
# Clock          : %s
# Minimum period : %s
# **************************************************************************
]]>	</p>
    <p id="TRPT909A">
		<![CDATA[
# **************************************************************************
# Clock          : %s
# Minimum period : %s (*)
# **************************************************************************
# (*NOTE) Since the most critical path's start and end point have
# different rising/falling clock edge, the minimum period time is
# scaled %s times from the path delay.
]]>	</p>
    <p id="TRPT910">
		<![CDATA[
############################################################################
# FMAX Summary
############################################################################
Slowest clock     : %s
Minimum period    : %s
Maximum frequency : %s MHz
############################################################################
]]>	</p>
    <p id="TRPT911">
		<![CDATA[
############################################################################
#
# FMAX Report
#
############################################################################
#
# NOTE: FMAX is only computed for register-to-register paths within SAME
# clock domain. Multi-cycle paths, cross-clock-domain paths, including paths
# between master and generated clocks, are ignored. For paths between a clock
# and its inversion, FMAX is computed by scaling the path delay based on
# clock duty cycle. For example, for a path with start point driven by a
# rising clock edge and  with end  point driven by the the same  clock's
# falling edge, if the clock duty cycle is 50%%, the path delay is multi-
# plied by 2 (divided by 50%%) so as to compute FMAX.
#
]]>	</p>

	<!-- Min pulse width related messages -->
	<p id="TRPT300S">
	<![CDATA[
Slack : %s
Pin   : %s [Related clock : %s]
Type  : %s ]]> </p>
	<p id="TRPT300F">
	<![CDATA[
Pin   : %s [Related clock : %s]
Type  : %s ]]> </p>
	<p id="TRPT305">[Pulse rising edge propagation path]</p>
	<p id="TRPT310">[Pulse falling edge propagation path]</p>
	<p id="TRPT315"><![CDATA[Actual pulse width          : %s ]]></p>
	<p id="TRPT320"><![CDATA[Required pulse width        : %s ]]></p>
	<p id="TRPT325"><![CDATA[Slack = (actual - required) = %s ]]></p>
	<p id="TRPT325V"><![CDATA[Slack = (actual - required) = %s (VIOLATION!)]]></p>
	<i id="TRPT330">Generating WNS report ..</i>
	<p id="TRPT331">[Overall Summary]</p>
	<p id="TRPT331-A"><![CDATA[Setup WNS = %.0f]]></p>
	<p id="TRPT331-B"><![CDATA[Hold  WNS = %.0f]]></p>
	<i id="TRPT330-C"><![CDATA[  No result. Reason : design netlist is empty]]></i>
	<i id="TRPT330-D"><![CDATA[  No result. Reason : no timing constraint is specified]]></i>
	<p id="WNS-00">Info(wns-ok): %s, Met timing target.</p>
	<w id="WNS-W1">%s, Met timing target while margin is narrow</w>
	<w id="WNS-W2">%s, FAILED meeting timing target !</w>
	<w id="WNS-W3">%s, ** SEVERELY FAILED ** meeting timing target !</w>
	<i id="TRPT333">Done WNS report</i>
	<i id="TRPT335"><![CDATA[  (Check file "%s" for further detail)]]></i>

	<!-- timing info. report messages -->
	<p id="TMRT000">* CELL: %s</p>
	<p id="TMRT001">SYMBOL FROM TO VALUE TYPE LOGIC_SENSE CFG COND MODES</p>
	<p id="TMRT002">* VIEW: %s</p>
	<p id="TMRT003">* INSTANCE: %s[VIEW=%s]</p>
	<p id="TMRT004">* NET: %s</p>
	<p id="TMRT005">* LIBRARY: %s</p>
	<p id="TMRT600">synthesis timing report</p>
	<p id="TMRT601">packing timing report</p>
	<p id="TMRT602">placement timing report</p>
	<p id="TMRT603">routing timing report</p>

	<e id="TM701">No corresponding "save_timing_derate" called for "restore_timing_derate"</e>

	<e id="LIC000">License is not available for device "%s"</e>
	<e id="LIC001">License has expired</e>
	<p id="LIC900">
		<![CDATA[
#================================================
# License information of current release
#================================================
# Granted to : %s
# Type       : %s ]]>	</p>
	<p id="LIC901">
		<![CDATA[#------------------------------------------------
# [KEY     ] %s
# [Expire  ] %s
# [Devices ] ]]> </p>
	<p id="LIC902">#================================================</p>

<!-- Power Analysis -->
<p id="PA001">
<![CDATA[--------------------------------
Types            Power(W)
--------------------------------
Leakage          %g
Design Static    %g
Dynamic          %g
--------------------------------
Total            %g
]]>	</p>

<p id="PA002">
<![CDATA[
Dynamic Power Details:
--------------------------------
On Chip        Power(W)
--------------------------------
]]>	</p>

<p id="PA003">
<![CDATA[%-15s%g
]]></p>

<w id="PA101">Clock %s is not constrained </w>

<!-- Power Analyzer -->
<w id="PWR001">Design is not fully implemented, unable to run power analysis</w>
<w id="PWR002">Device family %s is not supported by power analysis</w>
<w id="PWR003">Failed to open file %s</w>
<w id="PWR004">Failed to load file %s</w>
<w id="PWR005">No timing constraint is applied, unable to calculate/report dynamic power consumption</w>

<!-- Signal Probe -->
<i id="SPRB001">Probing signal %s to %s ...</i>
<i id="SPRB002">Signal probe %s </i>
<e id="SPRB100">Net name or loc is not found!</e>
<e id="SPRB101">Not find net %s</e>
<e id="SPRB102">For %s, find %d (>1) UDM nets!</e>
<e id="SPRB103">Invalid location "%s"</e>
<e id="SPRB105">Pin location "%s" is used in design, please choose an unused pin location</e>
<e id="SPRB110">Unable to find free resources to implement inverter</e>

<!-- IO Handling -->
<i id="IOH001">Set %d unused IO(s) to high impedance state</i>
<e id="IOH002">Dual-purpose IO name %s is invalid, valid names are : %s</e>
<e id="IOH003">For dual-purpose IO %s : pullmode %s is invalid, valid values are : %s</e>
<w id="IOH004">Unused IO(s) will not be set to high impedance state when pullmode is set to DOWN</w>
<w id="IOH005">Unused IO(s) will be set to high impedance state, but pullmode is set to %s</w>
<w id="IOH006">The command option '-unused_io' is outdated, please use '-unsio_pullmode' in the future</w>
<e id="IOH007">For port %s assigned to dual-purpose IO %s : pullmode %s is invalid, valid values are : %s</e>
<w id="IOH008">For port %s assigned to dual-purpose IO %s : pullmode %s is different from the default value %s</w>
<w id="IOH009">Unused normal IO has no pullmode setting, the default value(%s) will be used</w>
<w id="IOH010">Unused dual-purpose IO %s has no pullmode setting, the default value(%s) will be used</w>
<i id="IOH011">Checking IO attributes</i>
<p id="IOH012">** Unused IOs  **</p>
<p id="IOH013">{Type} {Name} {PULLMODE}</p>
<e id="IOH014">The command option '%s' is not supported by %s family</e>
<e id="IOH015">The command option '%s' is invalid, because %s has already been used</e>
<e id="IOH016">The command option '%s' is not supported by current device</e>

<!-- pin to csv -->
<e id="PTC001">This function is not supported by current device</e>
<i id="PTC002">Exporting CSV file %s</i>
<i id="PTC003">Done</i>
<e id="PTC004">Unable to find or open file %s</e>
<i id="PTC005">Converting CSV file %s to UPC file %s</i>
<e id="PTC006">The identifier "%s" could not be found, please check whether it has been deleted or changed</e>

<!-- DRC related messages -->
<e id="DRC-SA1001">SED function is enable on instance %s(%s), dual-port 36Kb RAM(s) below may not function properly, please use 16Kb RAM instead</e>
<h id="DRC-SA8001">Inference of 36Kb RAM is disabled due to SED function being enabled on instance %s(%s) </h>

<!-- clock region -->
<i id="CRSK0001">Annotated inter-clock region skew</i>
<i id="CRSK0005">Applying CDELAY for deskewing inter-region clock delay</i>

</messages>
