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<messages>
	<!-- commen netlist related messages -->
	<i id="UMAP-1">Converted %d LUT instances to technology-independent logic based on lutmask property "%s" </i>
	<i id="NLRD-1">Preparing device related information for reading netlist...</i>

	<e id="NLRD000">%s(%d) : %s </e>
	<e id="NLFM001">Unable recognize the netlist file format, please use -format to specify file format</e>
	<e id="NLFM901">argument -top only applies to netlist file in Verilog format, ignored</e>

	<w id="NLWR000">There's no top design cell or view specified, nothing to output</w>

	<!-- object handling messages -->
	<e id="UOBJ000">Object pointer %s is NULL or invalid</e>
	<e id="UOBJ001">Object type "%s" is invalid against its owner object type "%s" </e>
	<e id="UOBJ002">Owner should be an NVIEW object in the context of this command </e>
	<e id="UOBJ003">Owner object of type "%s" is invalid in the context of this command </e>

	<!-- guide related message -->
	<e id="GD000">Object is invalid </e>
	<e id="GD001">Top module is not assigned yet </e>
	<w id="GD002">At least one operation should be assigned </w>
	<w id="GD003">non-leaf instance should be uniquified before user applies guides</w>
	<e id="GD010">Only instance or net can be set as "dont_touch" </e>
	<e id="GD011">Only whole design or non-leaf instance can be set as "keep_hier" </e>
	<e id="GD012">Only whole design, non-leaf instance or FF instance can be set as "dont_retime" </e>
	<e id="GD013">Only whole design or instance can be set as "dont_dup" </e>
	<e id="GD014">Only whole design, non-leaf instance or FF instance can be set as "dont_dup_ff" </e>
	<e id="GD015">Only whole design, non-leaf instance or FF instance can be set as "dont_merge_ff" </e>
	<e id="GD016">target port/pin must be input/inout primary port, or output/inout pin of leaf instance </e>
	<e id="GD017">Only whole design, non-leaf instance, pin or net can be set with "fanout_limit" </e>
	<e id="GD018">Fanout limit number should be greater than one </e>

	<!-- flow related message -->
	<i id="FLOW100">nl.clean starts ...</i>
	<i id="FLOW101">nl.clean ends</i>
	<i id="FLOW102">Totally %d instances are removed by nl.clean</i>
	<i id="FLOW110">nl.sweep starts ...</i>
	<i id="FLOW111">nl.sweep ends</i>
	<i id="FLOW112">Totally %d instances are removed by nl.sweep</i>

	<!-- XDL reader messages -->
	<i id="XDLR-0">Reading XDL file %s ...</i>
	<i id="XDLR-1">XDL file read in successfully</i>
	<i id="XDLW-0">XDL file written successfully</i>
	<i id="XDLW-1">Output XDL file %s ...</i>
	<i id="XDLG-0">Router pre-processing of GND/VCC nets ...</i>
	<i id="XDLG-1">Generated %d GND nets (driving %d pins), generated %d VCC nets (driving %d pins)</i>
	<i id="XDLG-2">Done with GND/VCC net processing</i>

	<e id="XDLR001">%s(%d): Unexpected format of Cfg string : \n %s</e>
	<e id="XDLR002">%s(%d): Unexpected format of Cfg string line : \n %s</e>
	<e id="XDLR003">%s(%d): Unexpected BUS_INFO in Cfg string line : \n %s</e>
	<e id="XDLR004">%s(%d): Unexpected port direction [%s] in Cfg string line : \n %s</e>
	<e id="XDLR005">%s(%d): Unexpected port bus format [%s] in Cfg string line : \n %s</e>
	<e id="XDLR006">%s(%d): instance %s has been defined previously</e>
	<e id="XDLR007">%s(%d): unexpected site_def [%s]</e>
	<e id="XDLR008">%s(%d): inst %s is not defined previously</e>
	<e id="XDLR009">%s(%d): on inst %s : there's no pin named %s</e>
	<e id="XDLR010">%s(%d): unable to find port %s</e>
	<w id="XDLR011">%s(%d): "cfg" string is empty</w>
	<e id="XDLW300">Outputing of XDL file failed</e>
	<e id="XDLW301">Netlist check error: no IOBs are found in the netlist</e>
	<e id="XDLG000">There's no free logic resource to implement %s </e>

	<!-- XPN related messages -->
	<i id="NCLR-0">Reading XPN file %s ...</i>
	<i id="NCLR-1">XPN file read in successfully</i>
	<i id="XPNR-5">==&gt; Setup device with dev-info in XPN file </i>
	<i id="NCLW-0">XPN file written successfully</i>
	<i id="NCLW-1">Output XPN file %s ...</i>
	<e id="NCLR006">%s(%d): instance %s has been defined previously</e>
	<e id="NCLR007">%s(%d): unexpected cellmodel-name [%s]</e>
	<e id="NCLR008">%s(%d): signal %s refers to an undefined comp %s</e>
	<e id="NCLR009">%s(%d): signal %s refers to an undefined pin %s@%s</e>
	<e id="XPNR010">Unable to figure complete device information from XPN file: architecture=%s, device=%s, package=%s, performance=%s</e>
	<w id="NCLR100">%s(%d): signal %s refers to a previously-defined pin %s@%s</w>
	<w id="NCLR105">%s(%d): signal %s has no driver</w>
	<w id="NCLR110">%s(%d): signal %s has been defined</w>
	<e id="NCLW100">Outputing of XPN file failed</e>

	<!-- BookShelf related messages -->
	<i id="BSR-0">Reading BS file %s ...</i>
	<i id="BSR-1">BS file %s read in successfully</i>
	<e id="BSR001">Unsupported vendor %s for BookShelf reader, only XILINX are supported!</e>
	<e id="BSR002">Library set up failed!</e>
	<e id="BSR003">Read file %s failed!</e>
	<e id="BSR004">Can't find cell %s in library %s !</e>

	<!-- Edif reader messages -->
	<i id="EDIR-0">Reading EDIF file %s ...</i>
	<i id="EDIR-2">    Appending file %s to read</i>
	<i id="EDIR-1">EDIF file read in successfully</i>
	<i id="BIND-1">Binding netlist to predefined library ... </i>
	<w id="BIND301">Ignored initial value %s of instance %s (not supported in this device) </w>

	<e id="EDFR001">No top cell found after reading EDIF file %s</e>
	<e id="EDFR002">Unable to find cell %s</e>
	<e id="EDFR003">Unable to find library %s</e>
	<e id="EDFR004">View %s has been defined for cell %s</e>
	<e id="EDFR005">Multi-dimensional array is not supported in this version</e>
	<e id="EDFR006">Unable to find port %s</e>
	<e id="EDFR007">Unexpected syntax</e>
	<e id="EDFR008">Unable to find instance %s</e>
	<e id="EDFR009">Instance %s has been defined already in view %s</e>
	<e id="EDFR010">Unable to find view %s in cell %s</e>
	<e id="EDFR300">Reading of EDIF file failed</e>

	<w id="EDFR901">Current design is not empty, please specify argument "-overwrite" to force overwriting the current design </w>
	<w id="EDFR902">Please use argument "-family" to specify the target device family when reading netlist, or use "dv.setup" command to setup target device first</w>
	<w id="EDFR903">Overwrote cell %s that already exists in library %s</w>

	<!-- Edif writer messages -->
	<i id="EDIW-0">Writing EDIF file %s ...</i>
	<i id="EDIW-1">EDIF file writing successfully</i>
	<e id="EDFW900">Please use argument "-family" to specify the target device family before writing netlist, or use "dv.setup" command to setup target device first</e>
	<e id="EDFW001">No top cell found </e>
	<e id="EDFW002">Before writing EDIF file, please uniquify the design first </e>
	<e id="EDFW003">Cannot open file %s ...</e>
	<e id="EDFW100">Writing of EDIF file failed</e>

	<!-- SDF writer messages -->
	<i id="SDFW-0">Output SDF file %s ...</i>
	<i id="SDFW-1">SDF written successfully</i>

	<!-- Verilog writer messages -->
	<i id="VLGW-0">Output Verilog file %s ...</i>
	<i id="VLGW-1">Verilog written successfully</i>
	<e id="VLGW300">Outputing of Verilog file failed</e>

	<!-- Verilog reader messages -->
	<i id="NVLM-0">    Reading module %s ...</i>
	<i id="NVLM-1">Top level modules: %s </i>

	<e id="NVLR001">%s(%d): module %s has been defined previously</e>
	<e id="NVLR002">%s(%d): instance %s has been defined previously</e>
	<e id="NVLR003">%s(%d): on module %s, there's no port named %s</e>
	<e id="NVLR004">%s(%d): port %s has been declared previously</e>
	<e id="NVLR005">%s(%d): port %s is not declared</e>
	<e id="NVLR006">%s(%d): wire %s has been defined previously</e>
	<e id="NVLR007">%s(%d): wire %s has different range definition from the port with same name</e>
	<e id="NVLR008">%s(%d): identifier %s is not defined</e>
	<e id="NVLR009">%s(%d): slice range [%d:%d] is invalid based on the definition of %s</e>
	<e id="NVLR010">%s(%d): index [%d] is invalid based on the definition of %s</e>
	<e id="NVLR011">%s(%d): the LHS width does not match that of RHS in the assignment</e>
	<e id="NVLR012">%s(%d): assignment to constant is invalid</e>
	<e id="NVLR013">%s(%d): module %s is not defined </e>
	<e id="NVLR014">%s(%d): port count does not match the connections count </e>
	<e id="NVLR015">%s(%d): can not find instance %s</e>
	<e id="NVLR016">%s(%d): invalid LHS expression in the tristate assignment</e>
	<e id="NVLR017">%s(%d): invalid RHS expression in the tristate assignment</e>
	<e id="NVLR018">%s(%d): invalid condition expression in the tristate assignment</e>
	<e id="NVLR019">%s(%d): module %s, port %s is not defined</e>
	<e id="NVLR300">Reading of netlist verilog file failed</e>

	<w id="NVLR901">%s(%d): instance %s : its %d-bit pin %s is not fully connected</w>
	<w id="NVLR902">%s(%d): gate instance %s has no output, ignored</w>
	<w id="NVLR903">%s(%d): can not find definition for module %s, treat it as blackbox </w>
	<w id="NVLR904">Unable to find definition for module %s, treat it as blackbox </w>
	<w id="NVLR600">Can not find module named %s</w>
	<w id="NVLR601">Library %s is empty, nothing to output </w>
	<w id="NVLR603">Overwrote module %s that already exists in library %s</w>

	<i id="NVLR-0">Reading netlist-verilog file %s ...</i>
	<i id="NVLR-1">Verilog file read in successfully</i>

	<!-- Spectre writer messages -->
	<i id="SPCW-0">Output Spectre file %s ...</i>
	<i id="SPCW-1">Spectre written successfully</i>
	<e id="SPCW300">Outputing of Spectre file failed</e>

	<!-- Legalization messages -->
	<i id="LGLZ000">Start legalization</i>
	<i id="LGLZ001">Done Legalization</i>
	<e id="LGLZ002">Legalization failed due to pin %s of instance %s was occupied</e>
	<i id="LGLZ003">Processing illegal carry chain: immigrate signal from pin %s to pin %s</i>
	<i id="LGLZ004">Processing VCC/GND nets: %d LUTs are implemented as VCC/GND drivers</i>
	<i id="LGLZ-101">Remove redundant Net %s</i>
	<i id="LGLZ-102">Remove redundant Instance %s</i>
	<i id="LGLZ-103">Detect LOOP net %s</i>
	<w id="LGLZ-104">Instance %s has not been placed</w>
	<i id="LGLZ-105">Total %d hierarchy constant Net</i>
	<i id="LGLZ-106">Create Dummy GND Instance %s</i>
	<i id="LGLZ-107">Create Dummy VCC Instance %s</i>
	<i id="LGLZ-108">Processing illegal shifter chain: immigrate signal from pin %s to pin %s</i>
	<i id="LGLZM5-101">  Added %d pass-through LUT4C(s)</i>

	<e id="LGLZ-110">IDELAYCTRL %s is placed at %s by user, but no IODELAY instantiated in same region</e>
	<e id="LGLZ-111">IDELAYCTRL need instantiated at %s</e>
	<e id="LGLZ-IO-001">Met unexpected connections for IOCELL %s(%s)</e>
	<e id="LGLZ-IO-005">Met unexpected connections between IOCELL %s(%s) and %s(%s)</e>

	<!-- Router messages -->
	<i id="RT0000">Device file is loaded successfully</i>
	<i id="RT0001">Done routing</i>
	<i id="RT0002">Create %d IOBs</i>
	<i id="RT0003">Total %d instances in current netlist</i>
	<i id="RT0004">%d primary nets are ignored</i>
	<i id="RT0005">Total %d nets (%d sinks) need to be routed</i>
	<i id="RT0006">Loading device and checking netlist ...</i>
	<i id="RT0007">Start routing</i>
	<i id="RT0008">Pin name from %s to %s</i>
	<i id="RT0009">Total %d net(s) failed among %d routed nets</i>
	<i id="RT0010">Router runtime is %d seconds</i>
	<i id="RT0011">Routing mode : %s</i>
	<i id="RT0012">Effort : %s</i>
	<i id="RT0013"><![CDATA[Round  0 : pre-routing ...]]></i>
	<i id="RT0014">Round %2d : unrouted nets %-5d, overused pins %-5d</i>
	<w id="RT0015">Failed nets : %d</w>
	<i id="RT0016">Net %s is set as %s by %s</i>

	<i id="RT3000">Global routing ... </i>
	<i id="RT3001">Global routing completed </i>
	<i id="RT3002">Detailed routing ... </i>
	<i id="RT3003">Detailed routing completed </i>
	<i id="RT3004">Loading routing resource library ... </i>

	<i id="RT4000">Congestion estimating ... </i>
	<i id="RT4001">Congestion estimating completed </i>
	<i id="RT4002">Initial Estimated Router Congestion: </i>
	<i id="RT4003">Estimation value: %.2f</i>
	<i id="RT4004"><![CDATA[%5.2f%% tiles are congested extremely
      %5.2f%% tiles are very congested
      %5.2f%% tiles are congested]]></i>
	<i id="RT4005"><![CDATA[Most congested areas:
        |  Tiles  | Congestion Value | Congestion level |
        +---------+------------------+------------------+]]></i>
	<p id="RT4006"><![CDATA[        |(%3d,%3d)|      %5.2f       |%s|]]></p>
	<i id="RT4007"><![CDATA[Maximum congestion area: (%3d,%3d)-->(%3d,%3d), average congestion value: %.2f]]></i>
	<i id="RT4008">The matrix of congestion estimation has been dumped</i>
	<i id="RT4009">Pins utilization in maximum congestion area:</i>
	<i id="RT4010">net%2d: %s (%d)</i>

	<e id="RT1001">Error when loading file %s</e>
	<e id="RT1002">Routing failed</e>
	<e id="RT1003">XDL file %s already exists</e>
	<e id="RT1004">Die name is NULL</e>
	<e id="RT1005">Can not find switch type between Pin %s and Pin %s</e>
	<e id="RT1006">Failed to set router device info</e>
	<e id="RT1007">Routing failed for sink pin %s of instance %s in net %s</e>
	<e id="RT1008">Unknown device type meets</e>
	<e id="RT1009">Netlist error meets</e>
	<e id="RT1010">Unknown exception: %s</e>
	<e id="RT1011">Can not find a path to pin (%s, %s) in net %s</e>
	<e id="RT1012">Net %s has been set clk index previously</e>
	<e id="RT1013">No path from src (%s%s) to dst (%s%s) in net %s</e>

	<w id="RT2000">can not find a path to pin %s in net %s</w>
	<w id="RT2001">use clock tree for pin %s of instance %s in net %s</w>
	<w id="RT2002">ignore dedicate path and use clock tree for pin %s of instance %s in net %s</w>
	<w id="RT2003">no real pclk pin in net %s</w>

	<!-- Packing messages -->
	<i id="PK0000">Start packing </i>
	<i id="PK0001">Done Packing </i>
	<i id="PK0002">Start preprocessing</i>
	<i id="PK0003">Done preprocessing</i>
	<i id="PK0100">Packing mode : Timing </i>
	<i id="PK0101">Packing mode : Area </i>
	<i id="PK0102">Area ratio limited : %d%% </i>
	<i id="PK0103">Area threshold of absorbing DFF to IOB : %d%% </i>
	<i id="PK0105">Logic Element (LE) Utilization : %d/%d %d%%</i>
	<i id="PK0110">Push %s to %s</i>
	<w id="PK0111">Failed to push REG %s to IOREG</w>
	<w id="PK0112">Reg %s with %s port and init value %d, cannot be promoted to IOREG</w>
	<i id="PK0115">Absorbed data output register to Block-RAM %s on port %s</i>
	<i id="PK0116">Duplicate reg %s for FIFO async rst %s</i>
	<w id="PK0117">Resource usage is too high and may cause trouble to achieve timing target</w>
	<e id="PK0118">Pad %s(%s) has no valid IOTYPE, please check LOC and BANK_VCCIO constraint</e>
	<w id="PK0120">Reg %s is driven by Port %s | %s, but not packed into IOLOGIC, %s</w>
	<w id="PK0121">Reg %s is driving Port %s | %s, but not packed into IOLOGIC, for %s</w>
	<w id="PK0122">Port %s has %s in IOLOGIC, but no paired %s</w>
	<i id="PK0123">Duplicate PLL RST REG %s</i>
	<i id="PK0124">Pre-pack PLL RST REG %s</i>

	<i id="PK0200">%-13s %10d</i>
	<i id="PK0201"><![CDATA[    %-13s %6d]]></i>
	<i id="PK0202">%-18s %10d</i>

	<i id="PK0300">Start gpack </i>
	<i id="PK0301">Done gpack </i>

	<e id="PK0911">Design netlist %s</e>
	<e id="PK1000">Pack Failed ... </e>
	<e id="PK1001">Invalid ratio: %d, valid value should be in range 1-100</e>
	<e id="PK1002">Cell %s can not be packed!!! </e>
	<e id="PK1003">LUT %s has no MASK!!! </e>
	<e id="PK1004">Unsupported OSCH NOM_FREQ parameter value %s in device %s</e>
	<e id="PK1005">Unsupported IO_TYPE %s on pad %s</e>
	<e id="PK1006">Unsupported OSCH NOM_DIV parameter value %s in device %s</e>
	<e id="PK1007">Device %s doesn't supported Cell %s</e>
	<e id="PK1008">Device %s doesn't supported Cell %s, please use %s</e>
	<w id="PK2000">More then 2 %s are assigned to location %s, extra ones are ignored.</w>
	<w id="PK2001">Legalize DI port of EBR %s.</w>
	<w id="PK2002">Make sure PLL %s have feedback from %s</w>
	<e id="PK2100">Dual-capacity ERB with different %s and %s has risky logic: %s</e>
	<e id="PK2101">Dual-capacity ERB %s%d port should not be used: %s</e>
	<e id="PK2102">Syntax of param %s=%s is wrong, should be 0b%s: %s</e>
	<e id="PK2103">Dual-capacity ERB param %s bit %d should not be used: %s</e>
	<e id="PK3000">#SLICE overflow, %d > %d, cannot fit</e>
	<i id="PK3001">Process packing ...</i>

	<i id="IRT0101">Start building routing graph</i>
	<i id="IRT0102">Finish building routing graph</i>
	<i id="IRT0200">User assign net %s to %s clock idx %d</i>
	<i id="IRT0200-PL">Placer assign net %s to %s clock idx %d</i>
	<i id="IRT0201">Auto assign net %s to %s clock idx %d</i>
	<i id="IRT0202">Pre-route design to collect info</i>
	<i id="IRT0203">Pre-routing %d th net of %d</i>
	<i id="IRT0204">Estimate upbound of worst-slack is %.3f</i>
	<i id="IRT0205">Routing round [%d] ----------------</i>
	<i id="IRT0206">  Routing %d th sink of %d (%d unrouted)</i>
	<i id="IRT0207">  Unrouted sinks : %d</i>
	<w id="IRT0208">Cannot find path even with used node, for sink %s</w>
	<i id="IRT0209">  Unrouted + conflict sinks : %d</i>
	<i id="IRT0210">Routing succeed</i>
	<e id="IRT0211">Routing failed</e>
	<e id="IRT0212">unroutable sink : src %s dst %s</e>
	<e id="IRT0213">unroutable net : src %s</e>
	<w id="IRT0214">%s %s has no valid site</w>
	<w id="IRT0215">Net %s driven by %s, need PCLK idx %s, but occupied.</w>

	<!-- Placement messages -->
	<i id="PL0000">Start placement</i>
	<i id="PL0001">Done placement</i>
	<i id="PL0002">Device %s loaded successfully</i>
	<e id="PL1000">No device specified, please setup device first</e>
	<e id="PL1001">Constraint conflict, quit placer ... </e>
	<e id="PL1002">Unknown device name %s</e>
	<e id="PL1003">Instance number exceeds device capacity, quit</e>
	<w id="PL2001">Find a COUT drives a non CIN pin %s</w>

	<!-- Logic Optimization messages -->
	<i id="LO0000">lo.simplify starts...</i>
	<i id="LO0001">lo.simplify ends</i>
	<i id="LO0002">lo.boolresub starts...</i>
	<i id="LO0003">lo.boolresub ends</i>
	<i id="LO0005">lo.resub starts...</i>
	<i id="LO0006">lo.resub ends</i>
	<i id="LO0007">Totally %d instances are substituted by lo.resub</i>
	<i id="LO0010">lo.eliminate starts...</i>
	<i id="LO0011">lo.eliminate ends</i>
	<i id="LO0012">Totally %d instances are eliminated by lo.eliminate</i>
	<i id="LO0015">lo.cubext starts...</i>
	<i id="LO0016">lo.cubext ends</i>
	<i id="LO0017">Totally %d instances are extracted by lo.cex</i>
	<i id="LO0020">lo.kernelext starts...</i>
	<i id="LO0021">lo.kernelext ends</i>
	<i id="LO0022">Totally %d instances are extracted by lo.kex</i>
	<i id="LO0025">Design has %d literal in all</i>
	<i id="LO0026">Convert %s %s to constant %s %s due to %s</i>
	<w id="LO0027">FF/Latch "%s" has both set and reset controls, convert to without</w>
	<w id="LO0028">FF/Latch "%s" has asynchronous load control, convert to without</w>
	<w id="LO0029">Keep "%s" failed, reason: Device does not support FF/Latch with both set and reset</w>
	<w id="LO0030">Keep "%s" failed, reason: The device does not support FF/Latch with asynchronous load</w>
	<i id="LO0031">merge %s "%s" into "%s"</i>
	<i id="LO0032">%d FFs are merged and #FF is reduced from %d to %d</i>
	<i id="LO0033">%s "%s", first %d/%d length is swept to %s ...</i>	
	<i id="LO0034">Merge %d nets</i>
    <i id="LO0035">%s -> %s</i>
	<i id="LO0036">%d SR-Luts are merged and #SR-Lut reduced %d</i>
	<i id="LO0037">merge %s "%s" and "%s"</i>
	<e id="SRL-E-0">%s</e>
	<e id="SEQ-E-0">%s</e>
	<e id="SRL-E-1">%s %s</e>
	<e id="SEQ-E-1">%s %s</e>

	<e id="LO1000">Unsupported input option value: %s for command lo.simplify</e>
	<e id="LO1001">Unsupported input option value: %s for command lo.boolresub</e>

	<i id="LO2001">Convert %d generated clock net: %s</i>
	<i id="LO2002">Convert %d gated clock net: %s</i>
	<i id="LO2003">Optimized %d chains with %d elements</i>
	<i id="LO2004">Optimized %d same input LUTs</i>
	<i id="LO2005">Optimized %d constant input MUXF</i>
	<i id="LO2006">Optimized %d same snet chains with %d elements</i>

	<!-- Technology Mapping messages -->
	<i id="Map0000">Start technology mapping</i>
	<i id="Map0001">Done technology Mapping</i>
	<i id="Map0002"><![CDATA[  Preprocess netlist...]]> </i>
	<i id="Map0003"><![CDATA[  Prepare syn library...]]> </i>
	<i id="Map0004"><![CDATA[  Initialize pins and cost...]]> </i>
	<i id="Map0005"><![CDATA[  Compute Cones...]]> </i>
	<i id="Map0006"><![CDATA[  Covering...]]> </i>
	<i id="Map0007"><![CDATA[  Generate LUT netlist...]]> </i>
	<i id="Map0008"><![CDATA[  Post process netlist...]]> </i>
	<i id="Map0009"><![CDATA[  Final checking...]]> </i>
	<i id="Map0010"><![CDATA[  Bind to %d 4-input LUTs]]> </i>

	<w id="Map0011">MUXF5 %s (Port %s) is driven by %s (%s)</w>

	<!-- Resynthesize messages -->
	<i id="RESYN-000">Start resynthesize</i>
	<i id="RESYN-001">Done resynthesis</i>

	<!-- Io Insertion messages -->
	<i id="INSIO-0000">Inserted %d IO cells</i>

	<w id="INSIO-0010">%s, %d internal tri-bufs driving net %s are implemented with AND-OR logic</w>
	<i id="INSIO-0011">%d boundary tri-bufs implemented with AND-OR logic</i>
	<i id="INSIO-0012">%d tri-bufs with OE: %s drive same primary output: %s </i>
	<h id="INSIO-100">%s instance %s : pin %s is dummy and legalized </h>
	<h id="INSIO-105">%s instance %s : pin %s is wired to dedicated external port</h>
	<e id="INSIO-200">Port %s drives more than one IOCELL: %s, %s, etc</e>

	<!-- Open Up messages -->
	<i id="OPEN0000">Start building physical netlist...</i>
	<i id="OPEN000A">Updating physical netlist...</i>
	<i id="OPEN0001">Done building physical netlist</i>
	<i id="OPEN001A">Updating physical netlist done</i>
	<i id="OPEN0002"><![CDATA[  Built physical netlist for%5d %ss ]]> </i>
	<i id="OPEN0003">Start reverse extracting netlist</i>
	<i id="OPEN0004">Done reverse extracting netlist</i>

	<!-- TMR messages -->
	<i id="TMR000">Start TMR</i>
	<i id="TMR001">Done TMR</i>
	<i id="TMR003">Demote clock iocell %s to normal iocell </i>
	<e id="TMR100">CLKDLL/DCM number is more than one, unable to do TMR</e>
	<e id="TMR101">The netlist contains physical block(s), unable to do TMR</e>

    <!-- LPP messages -->
	<i id="LPP_CA_1">%s assign Net to PCLK %d: %s</i>
	<i id="LPP_LGLZ_1">Lglz PLB</i>
	<i id="LPP_BPL_LOC_1">The inst %s [%s] is assigned to loc %s</i>

	<!-- Bitstream generation messages -->
	<i id="BGEN-1">Start generating bitstream file %s</i>
	<i id="BGEN-2">Done bitstream generation </i>
	<i id="BGEN-3"><![CDATA[  Running DRC ..]]></i>
	<i id="BGEN-4"><![CDATA[  Writing bitstream file ..]]></i>
	<i id="BGEN-5"><![CDATA[  Checking netlist ..]]></i>
	<i id="BGEN-6">Writing ASCII format bitstream file %s ..</i>
	<e id="BGEN001">Design integrity check error</e>
	<e id="BGEN002">Failed to generate bitstream</e>

	<!-- Synchronous reset/set control optimization messages -->
	<i id="SRS000">Start synchronous control optimization</i>
	<i id="SRS001">Done synchronous control optimization</i>
	<i id="SRS300">Removed %d gates for synchronous control</i>
	<i id="SRS301">[NOTE]Adjusted %d FFs with control priority differ from target device</i>
	<e id="SRS100">Device hasn't been setup, unable to run synchronous control optimization</e>

	<!-- Netlist checking/fixing messages -->
	<i id="NCHK001-1">Found %d dangling nets</i>
	<i id="NCHK001-2">Found and fixed %d dangling nets</i>
	<i id="NCHK002-1">Found %d undriven pins</i>
	<i id="NCHK002-2">Found and fixed %d undriven pins</i>
	<i id="NCHK003">Found %d multi-driven nets</i>
	<i id="NCHK004">Found %d instances that are not from the synthesis library</i>
	<w id="NCHK300-1">The following nets are dangling ...</w>
	<w id="NCHK300-2">The following nets are dangling, tied to GND ...</w>
	<w id="NCHK305-1">Instance %s : pin %s is undriven</w>
	<w id="NCHK305-2">Instance %s : pin %s is undriven, ties it to GND</w>
	<w id="NCHK305-3">Output port %s is undriven</w>
	<w id="NCHK305-4">Output port %s is undriven, ties it to GND</w>
	<w id="NCHK310">The following nets are multi-driven...</w>
	<e id="NCHK310A">The following nets are multi-driven...</e>
	<w id="NCHK315">Instance %s has asynchronous control pin driven by combinational logic and may be affected by glitch</w>
	<w id="NCHK315A"><![CDATA[  Force converted ascynchronous control to synchronouse control]]></w>
	<e id="NCHK320">The following are instances that are not from the synthesis library...</e>
	<w id="NCHK400">FF/Latch %s has both set and reset controls</w>
	<w id="NCHK401">FF/Latch %s has asynchronous load control</w>
	<w id="NCHK402-1">There's no connection for the following input port(s)...</w>
	<w id="NCHK402-2">There's no connection for the following inout port(s)...</w>
	<w id="NCHK402-3">There's no connection for the following output port(s)...</w>
	<w id="NCHK402-4">The following port(s) is driven by constant 0...</w>
	<w id="NCHK402-5">The following port(s) is driven by constant 1...</w>
	<e id="NCHK403">On IO buffer %s, PAD pin %s is unconnected, should connects to a port</e>
	<w id="NCHK404">Current netlist is empty</w>
	<e id="NCHK405">IO buffer %s(%s), PAD pin %s's connection (net %s) is invalid, it should connect one and only external port</e>
	<e id="NCHK410">%sRegister %s with %s has an initial value of %s. Unsupported by %s !</e>
	<w id="NCHK411">%sRegister %s with %s has an initial value of %s. Ignore initial value</w>
	<w id="NCHK501">Processed duplicated IO cell connection : %s(%s) -> %s(%s)</w>
	<w id="NCHK505">Processed irregular IO connections between %s(%s) and %s(%s)</w>
	<w id="NCHK510">There's no IOCELL for port %s</w>
	<e id="NCHK515">Instance %s, %s's pin %s is prohibited from conventional use, please check and modify design</e>
	<e id="NCHK516">Netlist NOT integrity: net %s connected to pin %s is not in its nview</e>

	<w id="NCHK-CLK001">Net %s has mixed clock and data connection(s)</w>
	<p id="NCHK-CLK001-EXP"><![CDATA[[HINT]Situation above usually indicates a generated clock, e.g. for
dividing frequency with counter logic. If it's indeed the case and is
necessary (e.g. unable to be replaced by PLL/DCM), please remember to
specify clock constraint EXPLICITLY for the generated clock net.
Otherwise, please fix such mixed-clock-data connections.
]]></p>
	<w id="NCHK-CLK003">Net %s has mixed connection of clock and control pins</w>
	<p id="NCHK-CLK003-EXP"><![CDATA[[NOTE]Situation above indicates that most likely there is irregular coding
style or typo in source description, please DOUBLE CHECK.
]]></p>
	<w id="NCHK-CLK005">Net %s is a gated clock, which may wrongly triggers due to combinational glitch</w>
	<p id="NCHK-CLK005-EXP"><![CDATA[[NOTE]Gated clock is NOT recommended in FPGA design, please make use
of dedicated CE(clock enable) pin of sequential cells driven by the
clock directly, rather than gating it.
]]></p>
	<p id="NCHK-CLK900">-- non-clock pins --</p>
	<p id="NCHK-CLK905">-- clock pins --</p>

	<i id="NCHK-DRH001">NOTE-- data recovery instance %s has user specified location %s, skip auto handling</i>
	<i id="NCHK-DRH005">Identified data-recovery port %s and automatically set locations of related instances </i>
	<w id="NCHK-DRH901">There's no pin assignment to port %s, corresponding data recovery function may NOT working!</w>
	<i id="NCHK-DRH010">[CHK-DATA-SKEW]Net %s, data skew (%.0f) is within limit (%.0f)</i>
	<w id="NCHK-DRH905">[CHK-DATA-SKEW]Net %s, data skew (%.0f) exceeds limit (%.0f)</w>
	<i id="NCHK-DLY001">[CHK-DELAY-005]Net %s, delay (%.0f) is within limit (%.0f)</i>
	<w id="NCHK-DLY401">[CHK-DELAY-305]Net %s, delay (%.0f) exceeds limit (%.0f)</w>

	<p id="VLGH000">
	<![CDATA[
//=========oOOOo===========================================oOOOo==========
//  Verilog file generated by HqFpga(TM) v%s Build %s
//  Time : %s
//  Uptops Design Technologies, Inc. (www.uptops-dt.com)
//========================================================================
	]]>
	</p>

	<p id="XDLH000">
	<![CDATA[
# =========oOOOo===========================================oOOOo==========
# XDL file generated by HqFpga(TM) v%s Build %s
# Time: %s
# Uptops Design Technologies, Inc. (www.uptops-dt.com)
# ========================================================================
	]]>
	</p>

	<p id="NCLH000">
	<![CDATA[
// =========oOOOo===========================================oOOOo==========
// XiST Physical Netlist generated by HqFpga(TM) v%s Build %s
// Designname: %s
// Creation time stamp : %s
// Uptops Design Technologies, Inc. (www.uptops-dt.com)
// ========================================================================
	]]>
	</p>

</messages>
