<?xml version="1.0" encoding="UTF-8"?>
<root>
	<!-- Example -->
		<!-- CacheMsg.getMsg("edit_ID2") -->
	<!-- For 'button' -->
	<buttonClass>
		<item id="button_ID01">Design Entry</item>
		<item id="button_ID02">To invoke Xilinx ISE</item>
		<item id="button_ID03">Implementation</item>
		<item id="button_ID04">DRC/Bitgen</item>
		<item id="button_ID05">browser...</item>
		<item id="button_ID06">Add</item>
		<item id="button_ID07">Del</item>
		<item id="button_ID08">OK</item>
		<item id="button_ID09">Cancel</item>
		<item id="button_ID10">low</item>
		<item id="button_ID11">standard</item>
		<item id="button_ID12">high</item>
		<item id="button_ID13">Create</item>
		<item id="button_ID14">Import</item>
		<item id="button_ID15">Timing driven</item>
		<item id="button_ID16">Area mode</item>
		<item id="button_ID17">Read EDIF file</item>
		<item id="button_ID18">RTL synthesis</item>
		<item id="button_ID20">XDL </item>
		<item id="button_ID21">Verilog netlist</item>
		<item id="button_ID23">Routability driven</item>
		<item id="button_ID24">RTL(VHDL/Verilog)</item>
		<item id="button_ID25">Netlist(EDIF)</item>
		<item id="button_ID26">Report</item>
		<item id="button_ID27">refresh</item>
		<item id="button_ID28">expand</item>
		<item id="button_ID29">collapse</item>
		<item id="button_ID30">output SDF</item>
		<item id="button_ID31">output physical hierarchy</item>
		<item id="button_ID32">output location</item>
		<item id="button_ID33">output logic equation</item>
		<item id="button_ID34">Mode</item>
		<item id="button_ID35">extra</item>
		<item id="button_ID36">Finish</item>
		<item id="button_ID37">Back</item>
		<item id="button_ID38">Next</item>
		<item id="button_ID39">remapping</item>
		<item id="button_ID40">Mapping &amp; Packing</item>
		<item id="button_ID41">iob_dff threshold %</item>
		<item id="button_ID42">Save</item>
		<item id="button_ID43">Setting</item>
		<item id="button_ID44">Default</item>
		<item id="button_ID45">Routing effort</item>
		<item id="button_ID46">Timing effort</item>
		<item id="button_ID47">Set Font</item>
		<item id="button_ID48">Placement Viewer</item>
		<item id="button_ID49">Package Viewer</item>
		<item id="button_ID50">YES</item>
		<item id="button_ID51">NO</item>
		<item id="button_ID52">Report and Analysis</item>
		<item id="button_ID53">Synthesis/Mapping</item>
		<item id="button_ID54">Tech-mapping effort</item>
		<item id="button_ID55">Tech-mapping mode</item>
		<item id="button_ID56">Maximum number of inputs for LUT</item>
		<item id="button_ID57">Show Details</item>
		<item id="button_ID58">table view</item>
		<item id="button_ID59">graphic view</item>
		<item id="button_ID60">Clear</item>
		<item id="button_ID61">Set Optimization Options</item>
		<item id="button_ID62">Pack effort</item>
		<item id="button_ID63">Place effort</item>
		<item id="button_ID64">Exit</item>
		<item id="button_ID65">Placement seed (non zero integer)</item>
		<item id="button_ID66">Other placement options</item>
		<item id="button_ID100">On-chip debugging</item>
		<item id="button_ID100A">On-chip debugging</item>
		<item id="button_ID105">Implement-&gt;Download</item>
		<item id="button_ID110">Realtime Debug</item>
		<item id="button_ID115">IP Creator</item>
		<item id="button_ID116">Netlist Viewer</item>
		<item id="button_ID117">Design Explorer</item>
		<item id="button_ID201">IO pull mode</item>
		<item id="button_ID205">Set unused IO to high impedance state</item>
		<item id="button_ID301">Set Hidden Options</item>
	</buttonClass>
	<!-- For 'label' -->
	<labelClass>
		<item id="label_ID01">Project name:</item>
		<item id="label_ID02">Top module:</item>
		<item id="label_ID03">Working directory:</item>
		<item id="label_ID04">Device:</item>
		<item id="label_ID05">Source RTL:</item>
		<item id="label_ID06">Packing</item>
		<item id="label_ID07">Placement</item>
		<item id="label_ID08">Routing setting:</item>
		<item id="label_ID11">Output directory:</item>
		<item id="label_ID12">Constraint text:</item>
		<item id="label_ID13">Constraint guide:</item>
		<item id="label_ID14">Effort</item>
		<item id="label_ID15">Base device:</item>
		<item id="label_ID16">Output file</item>
		<item id="label_ID17">Placement output</item>
		<item id="label_ID18">Resource util%:</item>
		<item id="label_ID19">Entry type:</item>
		<item id="label_ID20">Routing output</item>
		<item id="label_ID21">Netlist file</item>
		<item id="label_ID22">Root ISE install dir:</item>
		<item id="label_ID23">Synplify binary dir:</item>
		<item id="label_ID24">Precision binary dir:</item>
		<item id="label_ID25">Project name and output directory</item>
		<item id="label_ID26">Select target device</item>
		<item id="label_ID26-0">Family</item>
		<item id="label_ID26-A">Die</item>
		<item id="label_ID26-B">Package</item>
		<item id="label_ID26-C">Speedgrade</item>
		<item id="label_ID26-D">Condition</item>
		<item id="label_ID27">Design entry type</item>
		<item id="label_ID28">RTL entry:</item>
		<item id="label_ID29">Global setting</item>
		<item id="label_ID30">Flow setting</item>
		<item id="label_ID31">Constraints</item>
		<item id="label_ID32">constraint editor</item>
		<item id="label_ID33">ProjectNavigater</item>
		<item id="label_ID34">RAM inferencing/mapping</item>
		<item id="label_ID35">ROM inferencing/mapping</item>
		<item id="label_ID36">FSM Optimization</item>
		<item id="label_ID37">Expression Optimization</item>
		<item id="label_ID38">MUX Optimization</item>
		<item id="label_ID39">Target FMAX (MHz)</item>
		<item id="label_ID40">Cell</item>
		<item id="label_ID41">Used</item>
		<item id="label_ID42">Total</item>
		<item id="label_ID43">Ratio</item>
		<item id="label_ID50">DSP inferencing/mapping</item>
		<item id="label_ID51">Resource Sharing</item>
		<item id="label_ID52">Redundant Register Removal</item>
		<item id="label_ID53">Verilog include paths</item>
		<item id="label_ID54">ShiftRegister inferencing/mapping</item>
		<item id="label_ID55">SystemVerilog mode</item>
		<item id="label_ID56">Gated/Generated clock conversion</item>
		<item id="label_ID57">Disable IO buffer insertion</item>
		<item id="label_ID60">Binary format</item>
		<item id="label_ID61">Compressed format</item>
		<item id="label_ID62">Disable CRC</item>
		<item id="label_ID63">Reversed binary format</item>
		<item id="label_ID64">Output detailed message</item>
		<item id="label_ID65">Additional configurations</item>
		<item id="label_ID68">Frame CRC</item>
		<item id="label_ID69">Additional bitgen options</item>
		<item id="label_ID70">Retain IO state during reconfiguration</item>
		<item id="label_ID71">Retain configuration for SSPI interface</item>
		<item id="label_ID72">Retain configuration for I2C interface</item>
		<item id="label_ID73">DCLK frequency</item>
		<item id="tip_ID65">Sample: master_spi_port=disabled|ext_crystal=on</item>
		<item id="tip_ID66">Sample: -compress_line_len 64</item>
		<item id="label_ID66">Execution is cancelled by user</item>
		<item id="label_ID67">total progress</item>
	</labelClass>
	<!-- For 'dialog' -->
	<dialogClass>
		<item id="dialog_ID01">Setting working dir</item>
		<item id="dialog_ID02">Please select working directory</item>
		<item id="dialog_ID03">Info</item>
		<item id="dialog_ID04">Warning</item>
		<item id="dialog_ID05">Error</item>
		<item id="dialog_ID06">Please specify project name.</item>
		<item id="dialog_ID07">Please set top module</item>
		<item id="dialog_ID08">Please specify source files</item>
		<item id="dialog_ID09">folder exists, will be overwritten!</item>
		<item id="dialog_ID10">XST is not found in your specified directory</item>
		<item id="dialog_ID11">Set XST directory</item>
		<item id="dialog_ID12">Choose XST dir</item>
		<item id="dialog_ID18">Main program is not connected</item>
		<item id="dialog_ID19">Done</item>
		<item id="dialog_ID20">RTL synthesis failed</item>
		<item id="dialog_ID21">Running RTL synthesis, please wait...</item>
		<item id="dialog_ID22">Running RTL synthesis...</item>
		<item id="dialog_ID24">No ISE. Please make sure XST is installed properly</item>
		<item id="dialog_ID25">Info: RTL synthesis done, start loading target device...</item>
		<item id="dialog_ID26">Unable to find  top module</item>
		<item id="dialog_ID27">Question</item>
		<item id="dialog_ID28">Reading EDIF file ...</item>
		<item id="dialog_ID29">Reading EDIF file failed</item>
		<item id="dialog_ID30">Bitstream generation...</item>
		<item id="dialog_ID31">setting working and output directory.</item>
		<item id="dialog_ID32">output directory can not be null!</item>
		<item id="dialog_ID33">does not support special character such as '#$%^</item>
		<item id="dialog_ID34">Add netlist to your project.</item>
		<item id="dialog_ID35">Netlist files' target family</item>
		<item id="dialog_ID36">Please specify netlist file!</item>
		<item id="dialog_ID37">Add source files to your project.</item>
		<item id="dialog_ID38">add one source file at least!</item>
		<item id="dialog_ID39">LUT input number should be within [2-6] (default is 4).</item>
		<item id="dialog_ID40">ratio option can only accept [1, 100],\nusing default 100.</item>
		<item id="dialog_ID41">iob_dff option can only accept [0, 100],\nusing default 25.</item>
		<item id="dialog_ID42">Timing analysis</item>
		<item id="dialog_ID43">analysing path </item>
		<item id="dialog_ID44"> (out of </item>
		<item id="dialog_ID45"> )</item>
		<item id="dialog_ID46">can't save the change on read-only file!</item>
		<item id="dialog_ID47">Content has been changed, save it ?</item>
		<item id="dialog_ID48">Opening Constraint Editor...</item>
		<item id="dialog_ID49">Running</item>
		<item id="dialog_ID50">Select Pin Location</item>
		<item id="dialog_ID51">Would you like you clear all Constraints?</item>
		<item id="dialog_ID52">Progress Information</item>
		<item id="dialog_ID53">Schematic Page %s of %s</item>
		<item id="dialog_ID54">This function is not provided in this build, please check with UDT for official release.</item>
		<item id="dialog_ID90">This function is not yet available for selected device! </item>
		<item id="dialog_ID91">This build is for evaluation purpose, Xilinx ISE tool will be invoked to do bitstream generation and download</item>
		<item id="dialog_ID95">Are you sure to re-run whole flow ?</item>
		<item id="dialog_ID201">Search Files </item>
		<item id="dialog_ID202">File Type : </item>
		<item id="dialog_ID203">Directory : </item>
		<item id="dialog_ID204">Search sub-directories </item>
		<item id="dialog_ID205">Start Search</item>
		<item id="dialog_ID206">Setting </item>
		<item id="dialog_ID207">Search Result </item>
		<item id="dialog_ID208">Found %d matched-file(s) </item>
		<item id="dialog_ID209">Select files ...</item>
		<item id="dialog_ID210">Search in directory ...</item>
		<item id="dialog_ID300">Content changed, do you want to discard all changes? </item>
		<item id="dialog_ID305">Please Select target device</item>
	</dialogClass>
	<!-- For 'editor' -->
	<editorClass>
		<item id="editor_ID01">No project</item>
		<item id="editor_ID02">HqFpga logfile</item>
		<item id="editor_ID03">Placement report</item>
		<item id="editor_ID04">Logic equation netlist (Verilog)</item>
		<item id="editor_ID05">Placed netlist (Verilog)</item>
		<item id="editor_ID06">Resource utilization Report</item>
		<item id="editor_ID08">RTL Synthesis logfile</item>
		<item id="editor_ID09">Mapped Netlist (EDIF)</item>
		<item id="editor_ID10">Close Server Socket\n</item>
		<item id="editor_ID11">Info: Opening project</item>
		<item id="editor_ID11A">Info: Done.</item>
		<item id="editor_ID12">Routed netlist (XDL)</item>
		<item id="editor_ID13">Top Module Setting</item>
		<item id="editor_ID14">Module Name</item>
		<item id="editor_ID15">Packed netlist (XDL)</item>
		<item id="editor_ID16">Placed netlist (XDL)</item>
		<item id="editor_ID17">DRC report</item>
		<item id="editor_ID18">Bitstream</item>
		<item id="editor_ID19">Packed netlist (Verilog)</item>
		<item id="editor_ID20">Synthesized netlist</item>
		<item id="editor_ID21">Routed netlist (Verilog)</item>
		<item id="editor_ID22">Packed SDF </item>
		<item id="editor_ID23">Placed SDF </item>
		<item id="editor_ID24">Routed SDF </item>
		<item id="editor_ID25">新宋仿</item>
		<item id="editor_ID26">DejaVu Sans Mono</item>
		<item id="editor_ID30">Routed Resource Report</item>
		<item id="editor_ID31">Download/Program</item>
		<item id="editor_ID32">VIO debugger</item>
		<item id="editor_ID33">Embedded VLA debugger</item>
		<item id="editor_ID34">Routing Heatmap</item>
		<item id="editor_ID40">synthesis timing report</item>
		<item id="editor_ID41">packing timing report</item>
		<item id="editor_ID42">placement timing report</item>
		<item id="editor_ID43">routing timing report</item>
	</editorClass>
	<!-- For 'info' -->
	<infoClass>
		<item id="info_ID01">New Project</item>
		<item id="info_ID02">Project property</item>
		<item id="info_ID03">Source file</item>
		<item id="info_ID04">Directory</item>
		<item id="info_ID05">Options</item>
		<item id="info_ID06">Setting 3rd party RTL synthesis tools</item>
		<item id="info_ID09">Console</item>
		<item id="info_ID11">Creating new project ...</item>
		<item id="info_ID12">Done.</item>
		<item id="info_ID13">Such as:</item>
		<item id="info_ID15">Export files</item>
		<item id="info_ID16">Add constraint</item>
		<item id="info_ID17">[Related commands] ta.set ta.report</item>
		<item id="info_ID18">Info: ****** Process interrupted per user request! ******</item>
		<item id="info_ID19">Info: Rolling back design status... </item>
		<item id="info_ID20">Info: Design status rolled back</item>
		<item id="info_ID21">Create New Project Done.</item>
		<item id="info_ID21">========== New Project ===========</item>
		<item id="info_ID22">======== Project Change  =========</item>
		<item id="info_ID23">========== Open Project ==========</item>
		<item id="info_ID24">==================================</item>
		<item id="info_ID30">Project File</item>
		<item id="info_ID31">Project Directory</item>
		<item id="info_ID32">Open other projects : </item>
	</infoClass>
	<!-- For 'ta' -->
	<taClass>
		<item id="ta_ID01">Timing report options</item>
		<item id="ta_ID02">report paths between unconstrained IO and registers</item>
		<item id="ta_ID03">report cross-clock domain paths</item>
		<item id="ta_ID04">report timing nodes inside physical hierarchy</item>
		<item id="ta_ID05">Dynamic loop breaking during analysis/optimization</item>
		<item id="ta_ID06">Report timing nodes on user hierarchical modules</item>
		<item id="ta_ID07">Maximum number of paths to report</item>
		<item id="ta_ID08">Maximum number of paths to report on one checkpoint</item>
		<item id="ta_ID08A">Maximum number of paths to report from one path start point</item>
		<item id="ta_ID09">Timing report options</item>
		<item id="ta_ID10">Optimize unconstrained IO to clock paths</item>
		<item id="ta_ID11">Optimize clock to unconstrained IO paths</item>
		<item id="ta_ID12">Handle cross-clock domain paths</item>
		<item id="ta_ID13">Keep hierarchy</item>
		<item id="ta_ID14">Handle paths between unconstrained IO and registers</item>
		<item id="ta_ID15">Timing analysis/optimization</item>
		<item id="ta_ID16">timing analysis/optimization type</item>
		<item id="ta_ID17">Run timing analysis, should add timing constraint first! Does add timing constraint now?</item>
		<item id="ta_ID18">Add constraint, should load design first! Does load design now?</item>
		<item id="ta_ID19">Handle asynchronous set/reset-to-output path</item>
		<item id="ta_ID20">Register power-up value</item>
		<item id="ta_ID25">Report min pulse width</item>
		<item id="ta_ID30">Naming style for auto-generated clocks</item>
		<item id="ta_ID31">Other setting(s)</item>
	</taClass>
	<soEditorClass>
		<item id="soEditor_ID01">Save</item>
		<item id="soEditor_ID02">Undo</item>
		<item id="soEditor_ID03">Redo</item>
		<item id="soEditor_ID04">Find/Replace</item>
		<item id="soEditor_ID05">Find:</item>
		<item id="soEditor_ID06">Replace with:</item>
		<item id="soEditor_ID07">Direction</item>
		<item id="soEditor_ID08">Forward</item>
		<item id="soEditor_ID09">Backward</item>
		<item id="soEditor_ID10">Options</item>
		<item id="soEditor_ID11">Case sensitive</item>
		<item id="soEditor_ID12">Whole word</item>
		<item id="soEditor_ID13">Regular expressions</item>
		<item id="soEditor_ID14">Find</item>
		<item id="soEditor_ID15">Replace</item>
		<item id="soEditor_ID16">Close</item>
	</soEditorClass>
	<bitGenClass>
		<item id="bitGen_ID01">
#=========oOOOo===========oOOOo==========
# Bitstream Generation
#========================================</item>
		<item id="bitGen_ID02">Info:   Performing DRC...</item>
		<item id="bitGen_ID03">Info:   Generating bitstream files...</item>
		<item id="bitGen_ID04">Info: Bitstream generation done.</item>
		<item id="bitGen_ID05">Info: Running bitstream generation... </item>
		<item id="bitGen_ID06">ERROR: bitGen ERROR, Please check log file for more info.</item>
	</bitGenClass>
	<!-- For 'application' -->
	<appClass>
		<item id="app_ID01">HqFpga</item>
				<item id="header">
<![CDATA[
==========oOOOo===========================================oOOOo==========
=  HqFpga(TM) V%s Build %s
=  Unified FPGA platform solutions
=  Uptops Design Technologies, Inc. (www.uptops-dt.com)    _@)
 _________________________________________________________/ (
<_________________________________________________________  {}@8@@8@(*)
                                                          \_(
=  Copyright (c) 2007-2010 UDT, Inc.                        @)
=  All rights reserved.
=========================================================================
]]></item>
	</appClass>
</root>
