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<messages>
	<!--  messages related with PLACEMENT general information  -->
    <i id="PHY-001">PLACEMENT final WNS = %d</i>

	<!--  messages related with constraints processing  -->
	<w id="PHY-CST-001">Instance %s's location constraint is ignored: location is invalid or conflicting with others</w>
	<e id="PHY-CST-001E">IO %s, pin assignment to %s is invalid</e>
	<e id="PHY-CST-001F">%s : %s</e>
	<w id="PHY-CST-002">Instance %s's location constraint is ignored: instance and location are not compatible</w>
	<w id="PHY-CST-003">Instance %s's location constraint is ignored: location constraint can only be applied to the header of an adder chain</w>
	<i id="PHY-CST-004">Instance %s is fixed at (%d, %d)</i>
	<w id="PHY-CST-005">Port %s's package pin assignment is ignored: port is unconnected</w>
	<w id="PHY-CST-006">Port %s's package pin assignment is ignored: port location %s is invalid</w>
	<i id="PHY-CST-007">Port %s is fixed at %s</i>
	<w id="PHY-CST-008">Instance %s's regional constraint is ignored: region %s can't be found in region definition</w>
	<w id="PHY-CST-009">Instance %s's regional constraint is ignored: regional constraint only applies to SLICE and BRAM instances</w>
	<w id="PHY-CST-010">Port %s's package pin assignment is ignored: port %s is fixed at the same position %s</w>
	<w id="PHY-CST-011">Instance %s's location constraint is ignored: instance %s is fixed at the same position %s</w>
	<e id="PHY-CST-011A">IO %s and %s are assigned to the same pin %s </e>
	<e id="PHY-CST-011B">Instance %s and %s are assigned to the same location %s </e>
	<w id="PHY-CST-012">Instance %s's regional constraint is ignored: regional constraint can only be applied to inclusive region</w>
	<w id="PHY-CST-013">Port %s's package pin assignment is ignored: normal IO is fixed at GCLK position %s</w>
	<w id="PHY-CST-014">Port %s's package pin assignment is ignored: global IO is fixed at normal position %s</w>
	<i id="PHY-CST-015">Instance %s is fixed at %s</i>
	<i id="PHY-CST-016">Instance %s is fixed at %s</i>
	<i id="PHY-CST-017">Set bank %s vccio : %s</i>
	<e id="PHY-CST-018">Bank %s vccio %s constraint is conflict with others</e>
	<e id="PHY-CST-019">Unsupported bank %s vccio type : %s</e>
	<e id="PHY-CST-100">Net type %s is invalid for current device, valid types are: {%s}</e>
	<w id="PHY-CST-101">Unable to honor regional constraint for instance %s, ignored</w>
	<p id="PHY-CST-101A"><![CDATA[Logical Resource :%s

]]> </p>
	<e id="PHY-CST-102">Instance %s cannot fit in, please specify the location by \"phycst.loc.set\" </e>
	<w id="PHY-CST-020">Instance %s's rloc constraint is ignored: it is conflict with the device structure requirement</w>
	<e id="PHY-CST-021">Conflict exists for rloc sets on instances %s because of fixed instance</e>
	<w id="PHY-CST-022">Rloc set %s is ignored: it is conflict with the device structure requirement</w>
	<e id="PHY-CST-023">Multiple instances have same relative location for rloc sets on instances %s</e>
	<e id="PHY-CST-024">Conflict exists in the following chain structures. %s</e>
	<e id="PHY-CST-025">Please specify the LOC for IODELAY %s, since the IDELAYCTRL's LOC has been assigned by user.</e>
	<e id="PHY-CST-030">Unable to place instance %s(%s), please check related IO constraint</e>
	<w id="PHY-CST-031">Unable to place instance %s(%s), the constraint may comes from other element in Group %s</w>
	<e id="PHY-CST-035">Instance %s's location (%s) conflicts with instance %s's location (%s), please check related location constraint</e>
	<e id="PHY-CST-040">Unable to place instance %s(%s) due to wrongly assigning associated port %s to pin %s</e>
	<w id="PHY-CST-045A">Port %s's pin assignment is changed from %s to %s</w>
	<e id="PHY-CST-045B">Port %s has multiple pin assignments: %s, %s</e>

	<e id="PHY-CST-050">Unable to find LOC for Instance %s</e>
	<e id="PHY-CST-051">Instance %s got invalid LOC</e>
	<e id="PHY-CST-052">PIO %s got incompatible IO_TYPE at LOC %s</e>
	<e id="PHY-CST-053">PIO %s : IO_TYPE/VCCIO is not compatible with Bank</e>
	<e id="PHY-CST-054">Instance %s cannot be placed on Blocked LOC</e>
	<e id="PHY-CST-055">Instance %s has multiple loc assignments: %s, %s</e>

	<e id="PHY-CST-060">Port %s is set as VREF_LOAD1, please specify the VREF PAD for BANK %d in advance</e>
	<e id="PHY-CST-061">PAD %s is set as VREF_LOAD1, it needs specified LOC</e>
	<e id="PHY-CST-062">Found conflicted PIO ATTR, PIO %s \"%s\" VS \"%s\"</e>
	<e id="PHY-CST-063">DDR2 IO is off, it does not support -vref argument</e>
	<e id="PHY-CST-064">DDR2 IO is off, it does not support -ratio argument</e>
	<e id="PHY-CST-065">EXTERNAL VREF does not support \"%s\"</e>
	<i id="PHY-CST-066">DDR2 IO is disabled</i>
	<e id="PHY-CST-067">unable to extract VCCIO for %s</e>
	<e id="PHY-CST-068">DDR2 IO is off, it does not support -external argument</e>
	<e id="PHY-CST-069">DDR2 IO is off, it does not support -internal argument</e>
	<e id="PHY-CST-070">VREF should be set as external or internal exclusively</e>
	<e id="PHY-CST-071">PIO %s has IOLOGIC connection, it cannot be placed on CONFIG PAD</e>
	<i id="PHY-CST-072">Port %s is assigned to CONFIG PAD %s</i>
	<w id="PHY-CST-073">No pin location assignment(s) for %d pins of %d total pins. Refer to %s for details</w>
	<w id="PHY-CST-074">Pin %s not assigned to a location on the device</w>
	<e id="PHY-CST-075">Port %s : neither location nor property is assigned, please specify one</e>
	<e id="PHY-CST-076">Instance %s has got REGION constraint already</e>
	<e id="PHY-CST-080">%s is not a valid location. E.g RxCy</e>
	<e id="PHY-CST-081">Argument -add and -factor cannot appear in same command</e>
	<e id="PHY-CST-082">Delay factor is not support yet</e>
	<i id="PHY-CST-083">clear all Device Delay Adjust parameter</i>
	<e id="PHY-CST-084">Unknown ATTR %s</e>
    <e id="PHY-CST-085">LOC %s does not support EBR with INIT value, please correct 'phycst.loc.set' for Instance %s</e>
	<i id="PHY-CST-086">PAD %s belongs to BANK_ADC, change bank info</i>
	<w id="PHY-CST-087">Net %s is Primary NET, it does not support phycst.net.set command</w>

	<e id="PHY-CHK-001">This DIE has not been supported.</e>
	<e id="PHY-CHK-002">This PACKAGE has not been supported.</e>
    <w id="PHY-CHK-003">Unable to find pair DIFFM/DIFFS for IOB(%s).</w>
	<e id="PHY-CHK-004">Port %s has connection with non-IOB, need do IOB insertion before placement.</e>
    <w id="PHY-CHK-005">IO %s is not compatible with Bank's VCCIO, please check the pin assignment.</w>
    <w id="PHY-CHK-006">IO %s is not compatible with Bank's VREF, please check the pin assignment.</w>
    <e id="PHY-CHK-007">PIO %s require VOLTAGE %s, which is not compatible with Bank %d (%s).</e>
    <e id="PHY-CHK-008">DQS conflict, please check the DQS constraint for (%s) %s %s.</e>
    <e id="PHY-CHK-009">ECLK conflict, please check the ECLK connection between %s and %s.</e>
    <e id="PHY-CHK-010">Unable find LOC %s for Cell %s.</e>
    <e id="PHY-CHK-011">PIO %s(%s) need different VCCIO in (%s) group.</e>
    <e id="PHY-CHK-012">%s exceed the capacity.</e>
    <e id="PHY-CHK-013">Bad connection, %s %s is driven by multiple PRADD.</e>
    <e id="PHY-CHK-014">%s.</e>
    <e id="PHY-CHK-015">DQ group distributes in different sub group. Please check location constraint for following IO : %s.</e>
    <e id="PHY-CHK-016">%s %s and NET %s are assigned at same track, please check UPC.</e>
	<e id="PHY-CHK-017">The connection between instance %s(%s:%s) and instance %s(%s:%s) is incorrect</e>
    <e id="PHY-CHK-018">Unroutable NET %s, please check it</e>
    <e id="PHY-CHK-019">Conflict NETs : \n%s</e>
    <e id="PHY-CHK-020">Location of instance %s(%s:%s) conflicts with that of %s(%s:%s)</e>
	<w id="PHY-CHK-021">IO %s(%s) is not compatible with Bank's IOTYPE, please check the pin assignment</w>
	<e id="PHY-CHK-022">Net %s wrongly connects PAD pins of two IO cells</e>
	<e id="PHY-CHK-023">Only PLL's CLKOP can drive CM3's PLL_OUT, not %s::%s</e>
	<e id="PHY-CHK-024">Port %s is not connected with PAD</e>
	<e id="PHY-CHK-025">Net %s should be a dedicated connection between PIO and IOLOGIC</e>
	<w id="PHY-CHK-026">Only input port on Bank %d, please specify IO_TYPE same with VCCIO</w>
    <w id="PHY-CHK-027">ECLKSYNC %s's ECLKI is tied with power, disconnect it</w>
	<e id="PHY-CHK-028">SERDES_COM %s::%s need be driven by IBUFDS</e>
	<e id="PHY-CHK-029">PIO %s is used as CLK, PIO %s cannot be placed at complement side</e>
	<e id="PHY-CHK-030">PIO %s is clock, it should be placed on P-side</e>
    <w id="PHY-CHK-031">SERDES PIO %s need user constraint"</w>
    <w id="PHY-CHK-032">Unable to deduce the location for SERDES PIO</w>
    <w id="PHY-CHK-033"></w>
	<e id="PHY-CHK-034">COM %s does not got placed, flow error</e>
	<e id="PHY-CHK-035">PAD %s may drives multiple SERDES_CH</e>

    <i id="PHY-CLK-001">Clock Assignment starting...</i>
    <i id="PHY-CLK-002">Clock Assignment finished.</i>
    <i id="PHY-CLK-003">Create Clk Region at (%d, %d, %d, %d).</i>
    <i id="PHY-CLK-004">Create Clk Group for GBUF %s.</i>
    <i id="PHY-CLK-005">Create Clk Group for RBUF %s.</i>
    <i id="PHY-CLK-006">Create Clk Group for BUFIO %s.</i>
    <i id="PHY-CLK-007">Clock Assignment : iteration %d</i>
    <e id="PHY-CLK-008">Clock Assignment : No legal assignment found!</e>
    <i id="PHY-CLK-009">%s clock distribution :</i>
    <w id="PHY-CLK-010">PAD %s need access Clock network, but it has not been placed on CLKPAD</w>
    <i id="PHY-CLK-011">CE/SR NET max fanout = %d</i>
    <i id="PHY-CLK-012">User can change this threshold via 'set pl.cesr.fanout [int]'</i>
    <i id="PHY-CLK-013">Found SR/CE net, load = %d,  add it as candidator for PCLK %s</i>
    <e id="PHY-CLK-014">%s %s is placed at %s, cannot drives %s</e>
    <e id="PHY-CLK-015">Clock component placement failed, please check the IO/ECLK/PLL constraints</e>
    <e id="PHY-CLK-016">ECLKSYNC %s cannot be placed in Bank %d, each BANK only contains 4 ECLKSYNC resource</e>
    <i id="PHY-CLK-017">Bank %d needs ECLKSYNC (%s)</i>
	<e id="PHY-CLK-018">DDRDEL %s cannot be attached with PIO %s, only CLKPAD can drive DDRDEL</e>
	<e id="PHY-CLK-019">Unable to meet the USER constraints</e>
	<e id="PHY-CLK-020">PIO %s cannot be placed at %s, due to IO_TYPE issue</e>
    <w id="PHY-CLK-021">ECLKSYNC %s is driven by non-dedicated connection, Dedicated connection are listed at below</w>
	<e id="PHY-CLK-022">(%s) ECLKSYNC %s is unable to cross the boundary of bank. E.g: %s</e>
    <w id="PHY-CLK-023">ECLKSYNC %s drives CLKFB via non-dedicated connection.</w>
    <w id="PHY-CLK-024">Clock %s may meet imbalance issue.</w>

	<!--  messages related with Placer  -->
	<i id="PHY-PLA-000">Placement mode: %s</i>
	<i id="PHY-PLA-001">Start placement</i>
	<i id="PHY-PLA-002">Done placement</i>
	<e id="PHY-PLA-003">Design is not loaded</e>
	<e id="PHY-PLA-004">Capacity overflow. type: %s, total cell num: %lu, total spot num: %lu</e>
	<i id="PHY-PLA-005">Wire Length: %*.2f, WNS: %*.2f</i>
	<e id="PHY-PLA-006">Can't find an initial placement for %s "%s"</e>
	<i id="PHY-PLA-007">Wire Length: %*.2f</i>
	<e id="PHY-PLA-008">Global clock assignment failed</e>
	<w id="PHY-PLA-009">Can't find DIFFS node for DIFFM node %s</w>
	<w id="PHY-PLA-010">Differential IO %s is fixed at an illegal location</w>
	<e id="PHY-PLA-011">Error found when processing differential IO</e>
	<w id="PHY-PLA-012">Node %s is not placed</w>
	<w id="PHY-PLA-013">Relative Constraint is unable to met. Break RLOCSET %s</w>
	<i id="PHY-PLA-014">Best achievable WNS = %g</i>
	<i id="PHY-PLA-015">S-Ratio = %g (%d / %d)</i>
	<i id="PHY-PLA-016">Identify CE/SR net</i>
	<i id="PHY-PLA-017">Done initial placement</i>
	<i id="PHY-PLA-018">CLOCK net %s is promoted to PCLK</i>
	<i id="PHY-PLA-100">Placement mode: no timing constraint</i>
	<i id="PHY-PLA-101">Placement mode: ignore timing constraint</i>
	<i id="PHY-PLA-102">Placement mode: timing</i>
	<i id="PHY-PLA-103">    timing effort: low</i>
	<i id="PHY-PLA-104">    timing effort: std</i>
	<i id="PHY-PLA-105">    timing effort: high</i>
	<i id="PHY-PLA-106">    routability effort: low</i>
	<i id="PHY-PLA-107">    routability effort: std</i>
	<i id="PHY-PLA-108">    routability effort: high</i>
	<e id="PHY-PLA-109">Design has unsupported cell (%s), quit.</e>
	<i id="PHY-PLA-110">Wire Cost: %.2f</i>
	<i id="PHY-PLA-111">Placement SEED is set as %d by User</i>
	<i id="PHY-PLA-120">Placement stage %d/%d (signature=%g,%d,%d)</i>
	<i id="PHY-PLA-121">Placement stage %d/%d</i>
	<i id="PHY-PLA-122">Pre-Placement stage</i>
	<i id="PHY-PLA-125">progress %3.f%%, WL = %6.f, WNS = %6.f</i>
	<i id="PHY-PLA-125W">progress %3.f%%, stage cost = %.f</i>
	<i id="PHY-PLA-126">progress %3.f%%</i>
	<i id="PHY-PLA-130">Set delay factor : %g </i>
	<i id="PHY-PLA-130B">Restored delay factor</i>
	<i id="PHY-PLA-135">Promote net %s (fanout=%d) to SCLK</i>
	<w id="PHY-PLA-245">Instances driven by net %s may not be effectively placed due to mixed clock-data connection</w>
	<e id="PHY-PLA-300">Device %s does not support Clock regions.</e>
	<e id="PHY-PLA-301">PIO %s got failure in auto-placement, please add LOC constraint by manual</e>

	<!--      messages related with XIST Placer  -->
	<e id="PHY-PLA-601">Unable to resolve legal location for DQSDLL %s -- IOL driven by DQSDLL should be at EITHER top-left OR bottom-right side (but not both)</e>
	<e id="PHY-PLA-605">location assignment of %s(%s) to %s is illegal (most likely from user constraint)</e>
	<e id="PHY-PLA-610">Two instances %s and %s are assigned to the same location %s</e>
	<e id="PHY-PLA-612">Two ports %s and %s are assigned to the same location %s</e>
	<e id="PHY-PLA-615">Unable to resolve legal location for %s %s from IO location</e>
	<e id="PHY-PLA-625">Clock IO driving %s@%s(%s) has no location </e>
	<e id="PHY-PLA-635">Unable to resolve legal location for ECLKSYNC %s -- IOL driven by ECLKSYNC should be at EITHER top-side or bottom-side (but not both)</e>
	<e id="PHY-PLA-640">No location available for placing %s(%s) </e>
	<e id="PHY-PLA-645">Unable derive or random-assign a location for %s(CLKDIV)</e>
	<w id="PHY-PLA-645A">Random-place %s(CLKDIV) to %s, due to its irregular usage</w>
	<e id="PHY-PLA-650">Number of user IOs (%d) exceeds available IO# (%d) </e>
	<e id="PHY-PLA-655">JTAG %s has no location</e>
	<e id="PHY-PLA-660">JTAG pin %s is not connected</e>
	<e id="PHY-PLA-661">JTAG IO %s is not compatible with Bank's VCCIO</e>
	<e id="PHY-PLA-665">%s capacity overflow -- %lu to be placed, %lu available in device</e>
	<e id="PHY-PLA-670">Failed in initial placement of %s(%s)</e>
	<e id="PHY-PLA-675">Failed in initial group placement starting at %s(%s)</e>
	<e id="PHY-PLA-680">Instance %s(%s) has no location</e>
	<e id="PHY-PLA-681">Instance %s got wrong location %s</e>
	<e id="PHY-PLA-682">Instance %s has not got placed</e>
	<e id="PHY-PLA-683">Instance %s collides with %s at location %s</e>
	<e id="PHY-PLA-684">Instance %s requires BANKID attribute</e>
	<e id="PHY-PLA-685">Instance %s has same BANKID as %s</e>
	<i id="PHY-PLA-686">duplicate %s at %s%s</i>
	<i id="PHY-PLA-687">Identified SLICE->PLL.CLKI path, %s => %s</i>
	<i id="PHY-PLA-688">Identified PLL.RST net %s, its driver is to be placed at %s</i>
	<i id="PHY-PLA-688-A">Identified PLL.RST net %s, its driver has been fixed at %s</i>
	<w id="PHY-PLA-688-B">Identified PLL.RST net %s, unable to set location for its driver %s that contains chain element</w>
	<w id="PHY-PLA-688-C">PLL %s does not have dedicated reset driver</w>
	<i id="PHY-PLA-689">Promote Net %s to PCLK</i>

	<!--  messages related with SA engine  -->
	<p id="PHY-SA-001">.</p>
	<e id="PHY-SA-002">Can't find a legal initial placement</e>
	<!--  messages related with Netlist  -->
	<e id="PHY-NL-001">Bad MUX connection at Net %s</e>
	<e id="PHY-NL-002">Bad BXOUT connection at Net %s</e>
	<e id="PHY-NL-003">Bad BYOUT connection at Net %s</e>
	<e id="PHY-NL-004">Bad BYINVOUT connection at Net %s</e>
	<e id="PHY-NL-005">Bad DIG connection at Net %s</e>
	<e id="PHY-NL-006">Instance %s has special connection other than %s</e>
	<i id="PHY-NL-007">Adder chain broken at Instance %s</i>
	<i id="PHY-NL-008">Shifter chain broken at Instance %s</i>
	<w id="PHY-NL-009">The length of the shift chain (%s) is greater than 128bit</w>
	<e id="PHY-NL-010">Error occurred when processing MUX structure for nodes: %s</e>
	<e id="PHY-NL-011">Error occurred when processing SHIFT structure for nodes: %s</e>
	<e id="PHY-NL-012">Error occurred when processing CLB structure for nodes: %s</e>
	<i id="PHY-NL-013">Unable find corresponding SLICE for DPRAM %s</i>
	<i id="PHY-NL-014">Group DPRAM (%s, %s)</i>
	<e id="PHY-NL-015">Cell %s belongs to multiple chain, ignore the later one.</e>

	<e id="PHY-CHK-001">Multiple instances are placed on location [%s] :</e>

	<!--  messages related with EXTCELL  -->
	<e id="PHY-EC-001">Error assigning port %s to %s, which cannot be user-assigned</e>

	<!--  messages related with AP  -->
	<i id="PHY-AP-001">Start analytic placement</i>
	<e id="PHY-AP-006">Found unbound cell %s</e>
	<e id="PHY-AP-007">Found cell %s with mismatched binding</e>
  <i id="PHY-AP-008">The best HPWL by Analytical Placement is %d</i>

  <!--  messages related with Drc  -->
	<e id="PHY-DRC-001">PIO(%s) drives DQS, but its location(%s) has no such capability. Please check constraint for this PIO</e>
	<e id="PHY-DRC-002">DQS(%s) group distributes in different sub group. Please check location constraint for following IO: %s</e>
	<e id="PHY-DRC-003">PIO(%s) is overlap with Differential PIO(%s). Differential PIO consumes a pair of PIO(P-side and N-side)</e>
	<e id="PHY-DRC-004">PIO(%s) VCCIO(%s V) is not compatible with Bank(%d) VCCIO(%s V), please check constraint</e>
	<w id="PHY-DRC-004A">PIO(%s) VCCIO(%s V) is not compatible with Bank(%d) VCCIO(%s V), please check constraint</w>
	<e id="PHY-DRC-005">PIO(%s) IOTYPE(%s) is not compatible with Bank(%d) IOTYPE(%s), please check constraint</e>
	<e id="PHY-DRC-006">Bank(%d) ECLKSYNC overflow(cur is %d, limit is %d), please check: %s</e>
	<e id="PHY-DRC-007">ECLKSYNC(%s) has no connection with instance(%s)</e>
	<w id="PHY-DRC-008">ECLKSYNC(%s) is driven by non-dedicated connection</w>
	<e id="PHY-DRC-009">No ECLKSYNC can drive following PIO(%s). Because they spans multiple banks(%s)</e>
	<w id="PHY-DRC-010">ECLKSYNC(%s) directly drives CLKBRANCH(%s). It is not recommended to use ECLKSYNC drive CLKBRANCH</w>
	<w id="PHY-DRC-011">Diff mode of PIO(%s) is different from the following PIOs in Bank(%d): %s</w>
	<w id="PHY-DRC-012">PIO(%s)'s %s register is missing</w>
	<e id="PHY-DRC-013">DRC failed</e>
	<p id="PHY-DRC-999">%s</p>
	<i id="PHY-DRC-100">Running DRC..</i>
	<i id="PHY-DRC-105A">-- not applicable to current device, skip </i>
	<i id="PHY-DRC-110">Done DRC</i>

<!--  messages related with Packed Dsp  -->
	<e id="PHY-DSP-001">The %s attributes of the following packed DSP instances have conflicts. Please check: %s</e>
	<w id="PHY-DSP-002">Unable to find a suitable ALU location due to the constraints of instance %s</w>
	<i id="PHY-DSP-003">The net %s try connect Port %s, which has been occupied by other net: %s</i>
	<e id="PHY-DSP-004">The location(r:%d, c:%d, idx:%d) for DSP layout is illegal</e>

	<!--  messages related with Slice transform  -->
	<e id="PHY-SLT-001">Cfg %s Confilct: %s, %s</e>
	<e id="PHY-SLT-002">Unexpected SEAL cfg %s: %s</e>
	<e id="PHY-SLT-003">Unexpected SHARK cfg %s</e>
	<e id="PHY-SLT-004">Get instance %s cfg failed</e>
	<w id="PHY-SLT-005">Unable to find pin %s for Cell %s</w>
	<e id="PHY-SLT-006">Pin %s::%s connect to another net</e>
	<w id="PHY-SLT-007">Unable to find SLOC for Instance %s</w>
	<e id="PHY-SLT-008">SLICEM transform to wrong cell %s</e>
	<e id="PHY-SLT-009">SLICEM site need transform to top</e>
	<e id="PHY-SLT-010">Can not merge two SLICEM now</e>
</messages>
