<?xml version="1.0" ?>
<!--
//	the XML files will be parsed by tinyXML which does not
//	support DOCTYPE

<!DOCTYPE messages [
	<! -- i:info e:error w:warning f:fatal -- >
	<!ELEMENT messages ((i|e|w|f)+)>
	<!ELEMENT i (#PCDATA)>
	<!ATTLIST i id CDATA #REQUIRED>
	<!ELEMENT p (#PCDATA)>
	<!ATTLIST p id CDATA #REQUIRED>
	<!ELEMENT e (#PCDATA)>
	<!ATTLIST e id CDATA #REQUIRED>
	<!ELEMENT w (#PCDATA)>
	<!ATTLIST w id CDATA #REQUIRED>
	<!ELEMENT f (#PCDATA)>
	<!ATTLIST f id CDATA #REQUIRED>
]>
-->

<messages>
	<!-- YACC region language hack messages, added by daniel -->
	<p id="YERR-001">syntax error</p>
	<p id="YERR-002">memory exhausted</p>
	<p id="YERR-101"><![CDATA[syntax error, unexpected "."]]></p>
	<p id="YERR-102"><![CDATA[syntax error, unexpected ]]></p>
	<p id="YERR-103"><![CDATA[, expecting ]]></p>
	<p id="YERR-104"><![CDATA[ or "."]]></p>
	<p id="YERR-105"><![CDATA[ or ]]></p>

	<!-- Info messages -->
	<i id="SFE-I-0">%s</i>
	<i id="SFE-I-1">Design analyzed successfully</i>
    <i id="SFE-I-3">
        Error preprocessing file %s
    </i>
    <i id="SFE-I-4">
        Analyzing Verilog file %s
    </i>
    <i id="SFE-I-5">
        Analyzing design
    </i>
    <i id="SFE-I-6">
        %s: message %s has occurred for too many times, the later same message would be ignored
    </i>
    <i id="SFE-I-7">
        Found '%s = %s' directive
    </i>
    <i id="SFE-I-8">
        Found '%s' directive
    </i>
    <i id="SFE-I-9">
        JSON file generated successfully
    </i>
    <i id="SFE-I-10">
        clear module '%s' from design
    </i>
    <i id="SFE-I-11">
        File filter completed, %d module(s) have been removed
    </i>

    <i id="ELAB-I-0">Design elaborated successfully</i>
    <i id="ELAB-I-1">Error elaborating design</i>
    <i id="ELAB-I-2">
        SDB transformed into UDM successfully
    </i>

    <i id="ELAB-I-4">
        Design top module is set as "%s"
    </i>
    <i id="ELAB-I-5">
        Outputting obfuscated file "%s"
    </i>
	<!-- Info messages 'end'-->
	<!-- Warning messages -->
    <w id="SFE-W-1">
        Error locating current working directory
    </w>
    <w id="SFE-W-2">
        %s is not supported yet in this version, ignored
    </w>
    <w id="SFE-W-3">
        %s is not a synthesizable construct, ignored
    </w>
    <w id="SFE-W-4">
        Signals duplicated in sensitive list, older one ignored
    </w>
    <w id="SFE-W-5">
        Signal "%s" missed in sensitive list
    </w>
    <w id="SFE-W-6">
        Pragma "%s" is not recognized, ignored
    </w>
    <w id="SFE-W-7">
        Could not find a corresponding target for pragma in meta-command %s
    </w>
    <w id="SFE-W-8">
        Assigning initial value to %s is not supported in this version, ignored
    </w>
    <w id="SFE-W-9">
        Unnecessary %s, ignored
    </w>
    <w id="SFE-W-11">
        Found X or Z in case statement, condition is always false
    </w>
    <w id="SFE-W-12">
        Found X in casez statement, condition is always false
    </w>
    <w id="SFE-W-13">
        Redundant digits given in number %s
    </w>
    <w id="SFE-W-14">
        "%s" is not a module instance parameter, defparam statement for it is not supported in this version, ignored
    </w>
    <w id="SFE-W-15">
        Number of module instantiation parameters "%d" exceed that of module declared parameters "%d", the additional ones ignored
    </w>
    <w id="SFE-W-16">
        Indexed part-select may exceed the bounds [%d:%d], potential simulation mismatch
    </w>
    <w id="SFE-W-17">
        Index of bit-select may exceed the bounds [%d:%d], potential simulation mismatch
    </w>
    <w id="SFE-W-18">
        "%s" is not a module parameter, ignored
    </w>
    <w id="SFE-W-19">
        More than one defparam statement exists for "%s", the last one would take into effect
    </w>
    <w id="SFE-W-20">
        Case equality '===' is synthesized as logic equality '==', potential simulation mismatch
    </w>
    <w id="SFE-W-21">
        Case inequality '!==' is synthesized as logic inequality '!=', potential simulation mismatch
    </w>
    <w id="SFE-W-22">
        Macro "%s" already defined, override old value with the new one
    </w>
    <w id="SFE-W-23">
        UDP is not a synthesizable construct, ignored
    </w>
    <w id="SFE-W-24">
        %s is already implicitly declared earlier
    </w>
    <w id="SFE-W-26">
        More than one default branch in case generate construct
    </w>
    <w id="SFE-W-27">
        Only variable are allowed as level event
    </w>
    <w id="SFE-W-28">
        Identifier "%s" inside initialization assignment not equal to identifier "%s" inside replication assignment
    </w>
    <w id="SFE-W-29">
        %s is not synthesizable, ignored
    </w>
    <w id="SFE-W-30">
        Range of port "%s" in port declaration and body are different
    </w>
    <w id="SFE-W-31">
        Repetition multiplier in concatenation is zero
    </w>
    <w id="SFE-W-32">
        Port "%s" is redeclared, the previous declaration will be discarded
    </w>
    <w id="SFE-W-33">
        Use binary expressions as edge-triggered events
    </w>
    <w id="SFE-W-41">
        Implicit net, "%s", is declared
    </w>
    <w id="SFE-W-42">
        Implicit net, "%s", is explicitly declared again. Explicit declaration take effect
    </w>
    <w id="SFE-W-43">
        "%s" has been declared previously. Discard this declaration
    </w>
    <w id="SFE-W-44">
        The variable "%s" declared in function cannot be initialized
    </w>
    <w id="SFE-W-45">
        Identifier "%s" is used before its declaration as a localparam or parameter
    </w>
    <w id="SFE-W-46">
        The parameter "%s" type(%s) in the instance is different from the type(%s) in the corresponding module
    </w>
    <w id="SFE-W-47">
        The long runtime may be due to the large size (%d Bytes) of the encrypted data block
    </w>
    <w id="SFE-W-48">
        The parameter "%s" declaration becomes localparam in module with formal parameter declaration list
    </w>
    <w id="SFE-W-49">
        Unsized number will be treated as 32 bits in concatenation
    </w>
    <w id="SFE-W-50">
        Overriding attribute "%s" with new value
    </w>
    <w id="SFE-W-51">
        Overriding attribute "%s" with new value "%s"
    </w>
    <w id="SFE-W-52">
        %s is not synthesizable, ignored in initial construct
    </w>
    <w id="SFE-W-100">
        Instance '%s' is specified twice in config, later one win
    </w>
    <w id="SFE-W-101">
        Both command line and config structure specify top module. The one in config structure takes effect
    </w>
    <w id="SFE-W-110">
        Event control statement should be the top statement of always construct. '@(*)' is added automatically for the always construct
    </w>
    <w id="SFE-W-111">
        always_latch doesn't infer latch logic
    </w>
    <w id="SFE-W-112">
        Cast real %f to %lld
    </w>
    <w id="SFE-W-113">
        Cast '%s' from real %f to %lld
    </w>
    <w  id="SFE-W-114">
		Size mismatch between enum value (%d bits) and enum declaration(%d bits) - will resize to %d bits
    </w>
    <w  id="SFE-W-115">
		Input port "%s" has an internal driver
    </w>
    <w id="SFE-W-116">
        Found an empty module (%s)
    </w>
    <w id="SFE-W-117">
        The '%s' directive applied to memory reg '%s' will be ignored
    </w>
    <w id="SFE-W-118">
        The '%s' directive applied to array '%s' will be ignored
    </w>
    <w id="SFE-W-119">
        For directive '%s', value '%s' is not supported and ignored
    </w>
    <w id="SFE-W-120">
        For directive '%s', no value is not supported and ignored
    </w>
    <w id="SFE-W-121">
        The '%s' directive applied to submodule port '%s' will be ignored
    </w>
    <w id="SFE-W-122">
        The '%s' directive applied to module instantiation '%s' will be ignored
    </w>
    <w id="SFE-W-123">
        The '%s' directive applied to '%s' driven by constant will be ignored
    </w>
    <w id="SFE-W-124">
        The '%s' directive applied to module declaration '%s' will be ignored
    </w>
    <w id="SFE-W-125">
        The '%s' directive applied to '%s' with no driven will be ignored
    </w>
    <w id="SFE-W-126">
        Found empty port in module declaration
    </w>
    <w id="SFE-W-127">
        The wildcard named port connections can only appear at most once in the port list
    </w>

    <w id="ELAB-W-0">
        Module call "%s" has less terminals than module declaration "%s"
    </w>
    <w id="ELAB-W-01">
        Instance "%s" of module "%s" has %d ports, but none of them is connected
    </w>
    <w id="ELAB-W-1">
        Module %s's %dth port "%s" is left unconnected during instantiation
    </w>
    <w id="ELAB-W-2">
        Module instance %s's port "%s" is left unconnected
    </w>
    <w id="ELAB-W-3">
        False branch met in case statement
    </w>
    <w id="ELAB-W-4">
        For used-but-never-assigned global var "%s", tied to zero
    </w>
    <w id="ELAB-W-5">
        '%s' statement is ignored in initial construct
    </w>
    <w id="ELAB-W-6">
        %s's file name argument is not a valid string, ignored
    </w>
    <w id="ELAB-W-7">
        For used-but-never-assigned global var "%s" in top module, will be tied to hiZ
    </w>
    <w id="ELAB-W-8">
        Port "%s" bit-width (%d) is greater than the output bit-width (%d) of the submodule to which it is connected, extra pins tied to zero
    </w>
    <w id="ELAB-W-9">
        No value is specified as the return value of function "%s", use default 0
    </w>
    <w id="ELAB-W-10">
        Array index [%d] is out of bounds in initial construct, valid bounds are [%d:%d], ignored
    </w>
    <w id="ELAB-W-11">
        '%s' has already been initialized by $readmem, subsequent assignment will be ignored
    </w>
    <w id="ELAB-W-50">
        More than one top module exist in current design, however only the first one "%s" would be design top
    </w>
    <w id="ELAB-W-51">
        Index width is too large. Shrink it to 32-bit width
    </w>
    <w id="ELAB-W-52">
        Comparison with 'X' or 'Z' values will always be false
    </w>
    <w id="ELAB-W-60">
        Latch inferred for variable %s, possible missing assignment in an if/case statement
    </w>
    <w id="ELAB-W-65">
        Port %s bit-width mismatch (formal bit-width = %d, actual = %d)
    </w>
    <w id="ELAB-W-70">
        Net %s is multi-driven and has no sink
    </w>
    <w id="ELAB-W-71">
        Cast real %f to integer %lld
    </w>
    <w id="ELAB-W-72">
        Input port "%s" has an internal driver
    </w>
    <w id="ELAB-W-73">
        On instance "%s(%s)", input port "%s" is unconnected
    </w>
    <w id="ELAB-W-74">
        On instance "%s(%s)", output port "%s" is unconnected
    </w>
    <w id="ELAB-W-75">
        On instance "%s(%s)", inout port "%s" is unconnected
    </w>
    <w id="ELAB-W-76">
        On instance "%s(%s)", mixed port "%s" is unconnected
    </w>
    <w id="ELAB-W-77">
        All output ports of instance "%s" are unconnected and this instance may be removed
    </w>
	<!-- Warning messages 'end'-->
	<!-- Error messages -->
    <e id="SFE-E-0">
        Macro "%s" is not defined
    </e>
    <e id="SFE-E-1">
        In macro call "%s", actual argument number %d does not match that of formal argument %d
    </e>
    <e id="SFE-E-3">
        */ outside of comment context
    </e>
    <e id="SFE-E-4">
        "%s" has been declared previously
    </e>
    <e id="SFE-E-5">
        Hierarchical ID "%s" is not supported in this version
    </e>
    <e id="SFE-E-6">
        Internal message: Error occurred within %s
    </e>
    <e id="SFE-E-8">
        String value contains an escaped octal value %d larger than 255
    </e>
    <e id="SFE-E-9">
        String value has a meaningless tailing escaped char
    </e>
    <e id="SFE-E-10">
        /* embedded into block comment
    </e>
    <e id="SFE-E-11">
        Invalid explicit parameter type
    </e>
    <e id="SFE-E-12">
        Syntax error, identifier expected
    </e>
    <e id="SFE-E-14">
        Initialization value of for-loop iteration variable "%s" is not a constant
    </e>
    <e id="SFE-E-15">
        Syntax error, only binary expression expected as for-loop replication expression
    </e>
    <e id="SFE-E-16">
        Step value of for-loop iteration variable "%s" is not a constant
    </e>
    <e id="SFE-E-18">
        Invalid task/function port type
    </e>
    <e id="SFE-E-19">
        %s is not synthesizable
    </e>
    <e id="SFE-E-20">
        Empty argument list in function call "%s"
    </e>
    <e id="SFE-E-21">
        %s
    </e>
    <e id="SFE-E-22">
        Internal error, please contact the vendor
    </e>
    <e id="SFE-E-23">
        Variable "%s" is not declared
    </e>
    <e id="SFE-E-24">
        Size of indices "%d" does not match array dimension "%d"
    </e>
    <e id="SFE-E-25">
        Error accessing "%s" as array
    </e>
    <e id="SFE-E-27">
        Event control statement is not allowed in procedural context in this version
    </e>
    <e id="SFE-E-28">
        Hierarchical identifier is not allowed as the operand of disable statement
    </e>
    <e id="SFE-E-29">
        Array element as event expression has variable index
    </e>
    <e id="SFE-E-30">
        Bit select as event expression has variable bit index
    </e>
    <e id="SFE-E-31">
        Part select as event expression has variable part index
    </e>
    <e id="SFE-E-32">
        Invalid event expression type
    </e>
    <e id="SFE-E-33">
        Value of attribute "%s" could only be constant
    </e>
    <e id="SFE-E-34">
        Data identifier "%s" is not declared
    </e>
    <e id="SFE-E-35">
        Error using constant "%s" as LHS
    </e>
    <e id="SFE-E-36">
        Array type required for system function "%s"
    </e>
    <e id="SFE-E-37">
        Array index [%d] out of bounds, valid bounds are [%d:%d]
    </e>
    <e id="SFE-E-38">
        Base of subscript operator "%s" must be a vector
    </e>
    <e id="SFE-E-39">
        Repetition multiplier in a concatenation is not constant expression
    </e>
    <e id="SFE-E-40">
        Called function (or task) "%s" not defined as a function (or task)
    </e>
    <e id="SFE-E-41">
        Wrong number of arguments in call to function or task "%s"
    </e>
    <e id="SFE-E-42">
        Illegal digit '%c' in based number
    </e>
    <e id="SFE-E-43">
        Circular dependency exists for parameter "%s"
    </e>
    <e id="SFE-E-44">
        Initial value of "%s" is not a constant
    </e>
    <e id="SFE-E-45">
        Vector size mismatch on port "%s"
    </e>
    <e id="SFE-E-46">
        Port "%s" could not be an array
    </e>
    <e id="SFE-E-47">
        Port inside function (or task) could only be reg or integer
    </e>
    <e id="SFE-E-48">
        Serious internal error, please contact the vendor
    </e>
    <e id="SFE-E-49">
        Not top modules exist in current design
    </e>
    <e id="SFE-E-50">
        Module "%s" is not found for instance "%s"
    </e>
    <e id="SFE-E-51">
        MSB (or LSB) must be a constant
    </e>
    <e id="SFE-E-52">
        Part-select indices reversed from the declared direction(declared [%d:%d], part-select is [%d:%d])
    </e>
    <e id="SFE-E-53">
        Part-select [%d:%d] out of bounds, valid bounds are [%d:%d]
    </e>
    <e id="SFE-E-54">
        Width of indexed part-select %d exceeds the bounds, valid bounds are [%d:%d]
    </e>
    <e id="SFE-E-55">
        Indexed part-select exceeds the bounds, valid bounds are [%d:%d]
    </e>
    <e id="SFE-E-56">
        Width operand in indexed part-select must be a constant
    </e>
    <e id="SFE-E-57">
        Width operand in indexed part-select must be greater than zero
    </e>
    <e id="SFE-E-58">
        Module "%s" is redeclared
    </e>
    <e id="SFE-E-59">
        Illegal redeclaration of port "%s"
    </e>
    <e id="SFE-E-60">
        Error overriding "%s" with defparam statement
    </e>
    <e id="SFE-E-61">
        Index of bit-select "%d" exceeds the bounds [%d:%d]
    </e>
    <e id="SFE-E-62">
        Error using supply0/supply as port type
    </e>
    <e id="SFE-E-63">
        `include expects "FILENAME"
    </e>
    <e id="SFE-E-64">
        The directive "%s" was found without a corresponding "%s" directive
    </e>
    <e id="SFE-E-65">
        The directive "%s" must have an identifier name after it
    </e>
    <e id="SFE-E-66">
        Redefinition of compiler directive "%s" not supported
    </e>
    <e id="SFE-E-67">
        Unable to create necessary temporary file
    </e>
    <e id="SFE-E-68">
        "%s" is not a valid macro identifier
    </e>
    <e id="SFE-E-69">
        "%s" was used invalidly
    </e>
    <e id="SFE-E-70">
        File "%s" left but not entered
    </e>
    <e id="SFE-E-71">
        "%s" is not a valid filename
    </e>
    <e id="SFE-E-72">
        Not found */ for block comment
    </e>
    <e id="SFE-E-73">
        Incomplete argument list for macro call `%s
    </e>
    <e id="SFE-E-74A">
        The input file "%s" specified by the "`include" directive cannot be found
    </e>
    <e id="SFE-E-74B">
        The input file "%s" specified by the "`include" directive cannot be recursive
    </e>
    <e id="SFE-E-75">
        Formal argument "%s" occur more than once in macro definition "%s"
    </e>
    <e id="SFE-E-76">
        Unable to open file "%s": too many level of symbolic links
    </e>
    <e id="SFE-E-77">
        "%s" instantiation is not synthesizable
    </e>
    <e id="SFE-E-78">
        Unexpected end-of-file before getting a legal based number
    </e>
    <e id="SFE-E-80">
        Type "%s" is not synthesizable
    </e>
    <e id="SFE-E-81">
        "%s" statement is not synthesizable
    </e>
    <e id="SFE-E-82">
        "%s" procedural statement is not synthesizable
    </e>
    <e id="SFE-E-84">
        If generate construct has non-const condition
    </e>
    <e id="SFE-E-85">
        Loop generate construct has non-const expression
    </e>
    <e id="SFE-E-86">
        Parameter cannot be used as loop index in loop generate construct
    </e>
    <e id="SFE-E-87">
        Loop generate construct has repeated genvar values
    </e>
    <e id="SFE-E-88">
        Too many (more than 100000) blocks are generated by loop generate construct
    </e>
    <e id="SFE-E-89">
        Case generate construct has non-const condition
    </e>
    <e id="SFE-E-90">
        Case generate construct switch No. %d value No. %d is not const one
    </e>
    <e id="SFE-E-91">
        Genvar is abused outside loop generate construct
    </e>
    <e id="SFE-E-92">
        A same genvar is required by index initialization and index iteration of loop generate construct
    </e>
    <e id="SFE-E-93">
        Real number is used in an invalid context
    </e>
     <e id="SFE-E-93A">
        Real number operation type '%s' is not supported
    </e>
    <e id="SFE-E-93B">
        Operation is failed or not supported, please check
    </e>
    <e id="SFE-E-95">
        Nonblocking assignment can not exist in a function
    </e>
    <e id="SFE-E-96">
        Time-controlled statement can not exist in a function
    </e>
    <e id="SFE-E-97">
        Can not enable task in a function
    </e>
    <e id="SFE-E-98">
        Too many parameter assignments in instance of module "%s"
    </e>
    <e id="SFE-E-99">
        Divisor must be a positive constant power of 2
    </e>
    <e id="SFE-E-100">
        Argument of system function %s at position %d must be a constant
    </e>
    <e id="SFE-E-101">
        Argument value of system function %s is invalid
    </e>
    <e id="SFE-E-102">
        Argument bit width of system function %s exceeds limitation(%d bits)
    </e>
    <e id="SFE-E-103">
        Value of defparam '%s' is not a constant
    </e>
    <e id="SFE-E-104">
        Address expression in "%s" is not a constant
    </e>
    <e id="SFE-E-105">
        Repeat expression is not a constant in repeat statement
    </e>
    <e id="SFE-E-110">
        Data file "%s" is empty
    </e>
    <e id="SFE-E-111">
        Variable "%s" doesn't exist
    </e>
    <e id="SFE-E-112">
        Variable "%s" is not declared as an array
    </e>
    <e id="SFE-E-113">
        Variable "%s" has more than one dimension, can't be initialized by "%s"
    </e>
    <e id="SFE-E-114">
        Variable "%s" has been initialized more than one time
    </e>
    <e id="SFE-E-115">
        Argument "%s" is invalid, only integer is supported
    </e>
    <e id="SFE-E-116">
        Argument "%s" is out of range of variable "%s"
    </e>
    <e id="SFE-E-117">
        Range [start, finish] is invalid
    </e>
    <e id="SFE-E-118">
        Invalid range select on array
    </e>
    <e id="SFE-E-119">
        Module "%s" is not found
    </e>
    <e id="SFE-E-120">
        Circular dependency happens during resolving ID "%s"
    </e>
    <e id="SFE-E-121">
        Too many indices for "%s"
    </e>
    <e id="SFE-E-122">
        Expecting the keyword 'module'
    </e>
    <e id="SFE-E-123">
    	Unsupported module name (%s) with "$"
    </e>
    <e id="SFE-E-124">
        Cycle detected or recursion limit reached during expansion of macro '%s'
    </e>
    <e id="SFE-E-125">
    	parameter binding by order is not supported for blackbox (%s)
    </e>
    <e id="SFE-E-126">
        syntax error, unexpected %s
    </e>
    <e id="SFE-E-127">
        Unsupported data type '%s' in Verilog HDL
    </e>
    <e id="SFE-E-128">
        %s inside another %s element
    </e>
    <e id="SFE-E-129">
        '%s': Port default value is not allowed in Verilog HDL
    </e>
    <e id="SFE-E-130">
        syntax error, unexpected %s, expecting %s
    </e>
    <e id="SFE-E-131">
        Declaring port '%s' as an array is not allowed in Verilog HDL
    </e>
    <e id="SFE-E-132">
        Declaring %s port '%s' as %s is not allowed in Verilog HDL
    </e>
    <e id="SFE-E-133">
        Value of the %dth defparam is not a constant
    </e>
    <e id="SFE-E-134">
        Multiple overrides for parameter '%s'
    </e>
    <e id="SFE-E-135">
        function/task has multiple statements without begin/end
    </e>
    <e id="SFE-E-136">
        Unsupported operator '%s' in Verilog HDL
    </e>
    <e id="SFE-E-137">
        Loop generate index "%s" is not declared
    </e>
    <e id="SFE-E-138">
        illegal operand for operator '%s'
    </e>
    <e id="SFE-E-139">
        unpacked value cannot be used in assignment
    </e>
	<e id="SFE-E-140">
        Argument in constant function call is non-constant
    </e>
    <e id="SFE-E-141">
        wrong element type in unpacked array concatention
    </e>
    <e id="SFE-E-142">
        wrong element count in unpacked array concatention
    </e>
    <e id="SFE-E-143">
        wrong element count in assignment pattern
    </e>
    <e id="SFE-E-144">
        structure pattern cannot be used with simple pattern
    </e>
    <e id="SFE-E-145">
        more than one default pattern in assignment pattern
    </e>
    <e id="SFE-E-146">
        left hand side of assignment pattern is a scalar
    </e>
    <e id="SFE-E-147">
        repeat index pattern in assignment pattern
    </e>
    <e id="SFE-E-148">
        index pattern is out of range
    </e>
    <e id="SFE-E-149">
        repeat member pattern in assignment pattern
    </e>
    <e id="SFE-E-150">
        count of repeat pattern must be more than zero
    </e>
    <e id="SFE-E-151">
        invalid assignment pattern
    </e>
    <e id="SFE-E-152">
        unpacked array is not allowed as left hand side
    </e>
    <e id="SFE-E-153">
        incompatible type of lhs and rhs
    </e>
    <e id="SFE-E-154">
        incompatible packed dimension
    </e>
    <e id="SFE-E-155">
        incompatible unpacked dimension
    </e>
	<e id="SFE-E-156">
        The ports of module '%s' do not match instance '%s'
    </e>
	<e id="SFE-E-157">
        multiple packed dimensions are not allowed
    </e>
    <e id="SFE-E-158">
        '%s' with too many range indices
    </e>
    <e id="SFE-E-159">
        In system function %s, the %dth argument %d is out of range, valid range is [%d:%d]
    </e>
    <e id="SFE-E-160">
        Operator '%s' only supports standalone statement, not as RHS
    </e>
    <e id="SFE-E-161">
        only support vector, memory or 2D packed arrays in verilog mode
    </e>
    <e id="SFE-E-162">
        rtl.file_filter does not support encrypted files
    </e>
    <e id="SFE-E-163">
        The wildcard named port connections(.*) for primitive is not supported yet
    </e>
    <e id="SFE-E-164">
        Implicit port connection failed, the data identifier '%s' is not declared
    </e>

    <e id="SFE-E-200">
        File name is missed in command line
    </e>
    <e id="SFE-E-201">
        In macro call '%s', too many actual arguments (%d), expected only %d
    </e>
    <e id="SFE-E-202">
        In macro call '%s', default text required for formal argument '%s'
    </e>
    <e id="SFE-E-203">
        In macro '%s', unterminated default text for argument '%s'
    </e>
    <e id="SFE-E-204">
        In macro '%s', parenthesis is required for macro with formal argument
    </e>
    <e id="SFE-E-205">
        Constant value %s exceeds 32-bit number limit
    </e>
    <e id="SFE-E-206">
        A 32-bit signed integer overflow occurred with constant value %u
    </e>
    <e id="SFE-E-207">
        MSB (or LSB) requires signed integer; invalid x/z value or integer overflow detected
    </e>
    <e id="SFE-E-208">
        The bit width of '%s' exceeds 32-bit unsigned number limit
    </e>
    <e id="SFE-E-209">
        The bit width of index exceeds 32-bit signed number limit
    </e>
    <e id="SFE-E-210">
        Packed dimensions are not allowed for unpacked type '%s'
    </e>
    
    <e id="SFE-E-301">
        Invalid instance name '%s'. A hierarchical name is expected
    </e>
    <e id="SFE-E-302">
        Instance name '%s' is not started with design name
    </e>
    <e id="SFE-E-303">
        Instance hierarchical path '%s' occurs within another instance hierarchical path '%s'
    </e>
    <e id="SFE-E-304">
        Instance hierarchical path '%s' occurs within another instance hierarchical path
    </e>
    <e id="SFE-E-305">
        Found more than one config. Currently only one config is allowed
    </e>
    <e id="SFE-E-306">
        Library name '%s' specified in config is invalid
    </e>
    <e id="SFE-E-307">
        Illegal reference to array on '%s'
    </e>
    <e id="SFE-E-308">
         Net %s has no description info
    </e>
    <e id="SFE-E-309">
         Encountered problem(s) in assignment to '%s'
    </e>
	<e id="SFE-E-310">
		Port assignment is only allowed for variable types
	</e>
	<e id="SFE-E-311">
		range width must be a positive integer
	</e>
	<e id="SFE-E-312">
		invalid assignment pattern
	</e>
	<e id="SFE-E-313">
		incorrect usage of unpacked type
	</e>
	<e id="SFE-E-314">
		initialization error
	</e>
    <e id="SFE-E-315">
        Repetition multiplier in concatenation is negative (%d)
    </e>
    <e id="SFE-E-316">
        Repetition multiplier in concatenation is illegal
    </e>
	<e id="SFE-E-317">
		Failed to find Hqfpga key in envelope
	</e>
	<e id="SFE-E-318">
		 Tail label should match head name "%s"
	</e>
	<e id="SFE-E-319">
		An enum variable may only be assigned to same enum typed variable
	</e>
	<e id="SFE-E-320">
		package "%s" is not declared
	</e>
	<e id="SFE-E-321">
		Not support module instantiation inside interface
	</e>
	<e id="SFE-E-322">
		Syntax error in current language
	</e>
	<e id="SFE-E-323">
		interface "%s" is redeclared
	</e>
	<e id="SFE-E-324">
		modPort "%s" is redeclared
	</e>
	<e id="SFE-E-325">
		Number of values does not match with elements
	</e>
	<e id="SFE-E-326">
		not support unpacked union
	</e>
	<e id="SFE-E-327">
		not support initialize packed structure at declaration
	</e>
	<e id="SFE-E-328">
		member size of packed union must be equal
	</e>
	<e id="SFE-E-329">
		unpacked element declared in packed struct/union
	</e>
	<e id="SFE-E-330">
		signed must used with packed struct/union
	</e>
 	<e id="SFE-E-331">
        illegal assign to array "%s" directly -- dimension incompatible
    </e>
	<e id="SFE-E-332">
		missing else(or default) statement in always_comb statement
	</e>
	<e id="SFE-E-333">
		always_ff doesn't infer flip-flop logic
	</e>
	<e id="SFE-E-334">
		"%s" value does not fit in enum type
	</e>
	<e id="SFE-E-335">
		enum value on %s conflict with %s
	</e>
	<e id="SFE-E-336">
		net data types must be 4 states
	</e>
	<e id="SFE-E-337">
		port "%s" is not connected on function(or task) call "%s"
	</e>
	<e id="SFE-E-338">
		incomplete pattern specified, no value is specified for "%s"
	</e>
	<e id="SFE-E-339">
		not support mixed pattern
	</e>
	<e id="SFE-E-340">
		port "%s" is not defined
	</e>
	<e id="SFE-E-341">
		Currently we only support one-dimensional reg array write in constant function call evaluation
	 </e>
    <e id="SFE-E-342">
        Found an user-defined module (%s), with the same name as the cell in synthesis library
    </e>
    <e id="SFE-E-343">
		More than one default branch in case statement
	</e>
	<e id="SFE-E-344">
		The value type of the '%s' attribute is unsupported
	</e>
    <e id="SFE-E-345">
        Enum range values must be non-negative integral numbers
    </e>
    <e id="SFE-E-346">
        Apostrophe bit is only supported in SystemVerilog
    </e>
    <e id="SFE-E-347">
        Enum with range must be explicitly declared with type
    </e>
    <e id="SFE-E-348">
        only support the vector or scalar as function or task ports
    </e>
    <e id="SFE-E-349">
        only support the vector or scalar as function return value
    </e>

    <e id="SFE-E-401">
        '%s': The semantic width (%d) is smaller than the self size (%d)
    </e>
    <e id="SFE-E-402">
        '%s': The value size (%d) should be 1 when the number represents an apostrophe bit
    </e>
    <e id="SFE-E-403">
        '%d': Unexpected operator type
    </e>
    <e id="SFE-E-404">
        Meet an unexpected error when dealing with constant '%s'
    </e>
    <e id="SFE-E-405">
       Meet an unexpected error
    </e>
    <e id="SFE-E-406">
        '%s': Unexpected data type
    </e>
    <e id="SFE-E-407">
        The initial value should not equal to adjusted value
    </e>
    <e id="SFE-E-408">
        The value of string should be (\"\")
    </e>
    <e id="SFE-E-409">
        Meet an unexpected error when inserting an instance config '%s'
    </e>
    <e id="SFE-E-410">
        Meet an unsupported function in the current version
    </e>
    <e id="SFE-E-411">
        '%s': The type of variable should be port
    </e>
    <e id="SFE-E-412">
        '%s': The count of arguments (%d) should match the count of actual arguments (%d)
    </e>
    <e id="SFE-E-413">
        'System function $%s': The number of arguments (%d) should be 1
    </e>
    <e id="SFE-E-414">
        Unexpected null symbol id for type '%d'
    </e>
    <e id="SFE-E-415">
        '$%s': No system function call name matches the expected pattern
    </e>
    <e id="SFE-E-416">
        '%s' should have been declared beforehand
    </e>
    <e id="SFE-E-417">
        Unexpected event control type
    </e>
    <e id="SFE-E-418">
        Unexpected statement type
    </e>
    <e id="SFE-E-419">
        Unexpected expression type
    </e>
    <e id="SFE-E-420">
        The hexadecimal number provided '%s' is invalid
    </e>
    <e id="SFE-E-421">
        Meet an unexpected error when processing '%s'
    </e>
    <e id="SFE-E-422">
        The %s should not have been initialized
    </e>
    <e id="SFE-E-423">
        '%s': The type of variable should not be port
    </e>
    <e id="SFE-E-424">
        '%s': Unexpected object type
    </e>
    <e id="SFE-E-425">
        '%s': The system function call name should be 'signed' or 'unsigned'
    </e>
    <e id="SFE-E-426">
        Variables cannot be declared outside a module in Verilog
    </e>
    <e id="SFE-E-427">
        Meet an unexpected error, please check Verilog
    </e>
    <e id="SFE-E-428">
        Meet an unexpected error when declaring '%s'
    </e>
    <e id="SFE-E-429">
        The number (%d) of top modules in the top library '%s' should be less than 1
    </e>
    <e id="SFE-E-430">
        The statement should be a blocking statement
    </e>
    <e id="SFE-E-431">
        Unexpected number type
    </e>
    <e id="SFE-E-432">
        The bit width of the constant is zero
    </e>
    <e id="SFE-E-433">
        Identifier "%s" is declared before its declaration as a localparam or parameter
    </e>
    <e id="SFE-E-434">
        Tasks cannot be declared outside a module in Verilog
    </e>
    <e id="SFE-E-435">
        Variables declared outside a module is unsupported in this version
    </e>
    <e id="SFE-E-436">
        "%s" used in incorrect context
    </e>
    <e id="SFE-E-437">
        Failed to get range width for '%s'
    </e>
    <e id="SFE-E-438">
        Enum declared inside struct is unsupported in this version
    </e>
    <e id="SFE-E-439">
        Meet an unsupported enum function when processing '%s'
    </e>
    <e id="SFE-E-501">
        The cast expression requires SystemVerilog
    </e>
    <e id="SFE-E-502">
        The cast expression with '%s' is unsupported in this version
    </e>
    <e id="SFE-E-503">
        The number in a width cast expression should be a constant positive integer
    </e>
    <e id="SFE-E-504">
        Cast expression must be integral when changing size or sign
    </e>
    
    <!-- Error message related with elaborate handling-->
    <e id="ELAB-E-0">
        No analyzed design to apply the specified operation
    </e>
    <e id="ELAB-E-2">
        Circular module dependency exists for module "%s"
    </e>
    <e id="ELAB-E-3">
        Event list missing
    </e>
    <e id="ELAB-E-4">
        Blocking assignment mixed with non-blocking for variable "%s"
    </e>
    <e id="ELAB-E-5">
        module/primitive "%s", port "%s" has more than one port-map connections
    </e>
    <e id="ELAB-E-6">
        Module call "%s" has more terminals than its module declaration "%s"
    </e>
    <e id="ELAB-E-7">
        Module/primitive "%s" does not has a port named "%s"
    </e>
    <e id="ELAB-E-8">
        Non-LHS expression is connected to module call %s's output/inout port "%s"
    </e>
    <e id="ELAB-E-9">
        Error creating pin net for module call %s's port "%s"
    </e>
    <e id="ELAB-E-10">
        Non-LHS expression is connected to the output port of gate instance "%s"
    </e>
    <e id="ELAB-E-11">
        Non-LHS expression is connected to the output port of gate instance
    </e>
    <e id="ELAB-E-20">
        No enough terminals specified for gate instance "%s"
    </e>
    <e id="ELAB-E-21">
        No enough terminals specified for gate instance
    </e>
    <e id="ELAB-E-22">
        Inconsistent terminal width found on gate instance "%s"
    </e>
    <e id="ELAB-E-23">
        Inconsistent terminal width found on gate instance
    </e>
    <e id="ELAB-E-24">
        "%s" is not declared as port
    </e>
    <e id="ELAB-E-25">
        Illegal port
    </e>
    <e id="ELAB-E-27">
        "%s" is not a variable
    </e>
    <e id="ELAB-E-28">
        Variable "%s" is not declared
    </e>
    <e id="ELAB-E-29">
        Variable "%s" is not a LHS
    </e>
    <e id="ELAB-E-30">
        Only single bit can be used as valid edge event
    </e>
    <e id="ELAB-E-31">
        Module "%s" does not support binding by name
    </e>
    <e id="ELAB-E-33">
        Edge sensitive events mixed with level sensitive events
    </e>
    <e id="ELAB-E-34">
        The case equality and case inequality operators (=== and !==) are not supported in this version
    </e>
    <e id="ELAB-E-35">
        Unsupported sensitive list pattern
    </e>
    <e id="ELAB-E-36">
        No value is specified as the return value of function "%s"
    </e>
    <e id="ELAB-E-37">
        %s is not supported in this version
    </e>
    <e id="ELAB-E-38">
        Iteration variable "%s" is updated inside for loop body by variable
    </e>
    <e id="ELAB-E-39">
        Loop condition checking against a non-const value
    </e>
    <e id="ELAB-E-40">
        Error specifying range property for %s
    </e>
    <e id="ELAB-E-41">
        Invalid function type
    </e>
    <e id="ELAB-E-42">
        Address of write target can not be a non-const value.
    </e>
    <e id="ELAB-E-43">
        Recursive function/task must be automatic
    </e>
    <e id="ELAB-E-44">
        Recursive iterates more than the static bound
    </e>
    <e id="ELAB-E-45">
        Array element or sub array can not be port
    </e>
    <e id="ELAB-E-46">
        Invalid event expression, only simple variable is supported in event expression
    </e>
    <e id="ELAB-E-47">
        Event expression list is empty
    </e>
    <e id="ELAB-E-48">
        %s operator is not supported currently
    </e>
    <e id="ELAB-E-49">
        %s statement is not supported currently
    </e>
    <e id="ELAB-E-50">
        Inconsistent assignment statement type
    </e>
    <e id="ELAB-E-51">
        Number of arguments of function call/task enable "%s" is different from its declaration
    </e>
    <e id="ELAB-E-52">
        One output terminal is connected to an unwritable net
    </e>
    <e id="ELAB-E-53">
        Terminal number is incorrect
    </e>
    <e id="ELAB-E-54">
        Output terminal width is different from its gate instance array size
    </e>
    <e id="ELAB-E-55">
        Input terminal width is invalid in gate instance array. The width should be 1 or array size
    </e>
    <e id="ELAB-E-56">
        Enable signal bit width is not 1
    </e>
    <e id="ELAB-E-57">
        Input bit width is different from output's
    </e>
    <e id="ELAB-E-58">
        Variable "%s" is not writable in current context
    </e>
    <e id="ELAB-E-59">
        Design is not read in
    </e>
    <e id="ELAB-E-60">
        Wrong disable target '%s'. It is invisible in this context or it is not a task or named block
    </e>
    <e id="ELAB-E-61">
        Input or inout port should be of type net. But '%s' is a variable
    </e>
    <e id="ELAB-E-62">
        Port %s of module instance array requires a %d-bit net(array-size * port-size)
    </e>
    <e id="ELAB-E-63">
        The bit width of "%s" exceeds limit (%d)
    </e>
    <e id="ELAB-E-64">
        Module '%s' doesn't support parameter '%s'
    </e>
    <e id="ELAB-E-101">
        SDB database is empty
    </e>
    <e id="ELAB-E-102">
        Failed to transform SDB into UDM
    </e>
    <e id="ELAB-E-103">
        Unsupported flip flop pattern, fail to infer flip flop for signal "%s"
    </e>
    <e id="ELAB-E-104">
        %d async signals are missed, fail to infer flip flop for signal "%s"
    </e>
    <e id="ELAB-E-106">
        Illegal multi-driven signal "%s"
    </e>
    <e id="ELAB-E-107">
        Net "%s" of type wand/wor can not be connected to inout terminal
    </e>
    <e id="ELAB-E-108">
        Unsupported operation with 'X' or 'Z' values
    </e>
    <e id="ELAB-E-109">
        The number of loop iterations exceeds limit (%d)
    </e>
    <e id="ELAB-E-110">
        Bit width of loop variable has exceeded "%d", too big
    </e>
    <e id="ELAB-E-111">
        Value of loop variable "%d" is out of bound
    </e>
    <e id="ELAB-E-112">
        Index %d is out of range, valid range is [%d, %d]
    </e>
    <e id="ELAB-E-113">
        Index [%d, %d] is out of range, valid range is [%d, %d]
    </e>
    <e id="ELAB-E-114">
        Identifier "%s" inside replication assignment of for-loop is not a constant
    </e>
    <e id="ELAB-E-115">
        Operator "%s" is not supported in replication assignment of for-loop, only "+", "-" operation is allowed
    </e>
    <e id="ELAB-E-116">
        Can not find a module named "%s" in design. Make sure use correct name for top module
    </e>
    <e id="ELAB-E-117">
        The %dth dimension's index "%d" is out of range, valid range is [%d, %d]
    </e>
    <e id="ELAB-E-118">
        Invalid zero bit net
    </e>
    <e id="ELAB-E-119">
        Currently, complex div and mod expression cannot be synthesized
    </e>
    <e id="ELAB-E-120">
        Invalid call of an undefined task "%s"
    </e>
	<e id="ELAB-E-121">
		 void function "%s" cannot be used in expression
	</e>
	<e id="ELAB-E-122">
	    Unexpected null id symbol.
	</e>
	<e id="ELAB-E-123">
		localparam "%s" cannot be overridden
	</e>
	<e id="ELAB-E-124">
        Met unexpected error during elaboration
	</e>
	<e id="ELAB-E-125">
        Met null statement during ifelse/case assign-statements legal-checking
	</e>
    <e id="ELAB-E-126">
        Expecting wire for output/inout port connection in module instantiation, but found reg "%s"
    </e>
    <e id="MACRO-E-0">
        Unable to map RAM to target device: "%s"
    </e>
	<w id="ELAB-W-130">
        %d data input of DataMerge has NO driver
	</w>
    <e id="ELAB-E-127">
        Meet an unexpected error
    </e>
    <e id="ELAB-E-128">
        Meet unexpected error related %s
    </e>
    <e id="ELAB-E-132">
        Wrong recursion level founded in '%s'
    </e>
    <e id="ELAB-E-133">
        Unexpected expression type
    </e>
    <e id="ELAB-E-134">
        '%s": Unexpected port direction: P_INVALID_TYPE
    </e>
    <e id="ELAB-E-137">
        '%s':  recursive concat is not supported
    </e>
    <e id="ELAB-E-138">
        No module in this design
    </e>
    <e id="ELAB-E-140">
        Meet invalid edge-type in sense list
    </e>
    <e id="ELAB-E-141">
        Invalid event expression, and failed to get it's value
    </e>
    <e id="ELAB-E-144">
        Get null (%s) variable assignment statement in if-statement
    </e>
    <e id="ELAB-E-145">
        Illegal case type: CASE_INVALID_TYPE
    </e>
    <e id="ELAB-E-146">
        At least two branches to merge
    </e>
    <e id="ELAB-E-147">
        Unknown assignment type when processing %s
    </e>
    <e id="ELAB-E-148">
        Get unexpected null statement in case-statement for var (%s)
    </e>
    <e id="ELAB-E-149">
        Bitwidth mustn't be greater than 32
    </e>
    <e id="ELAB-E-150">
        '%s': No parameter, set parameters failed
    </e>
    <e id="ELAB-E-151">
        JSON file generation failed
    </e>
    <e id="ELAB-E-152">
        The Initial value has already been set
    </e>
    <e id="ELAB-E-153">
        Unexpected port direction %s
    </e>
    <e id="ELAB-E-154">
        Unexpected port type
    </e>
    <e id="ELAB-E-155">
        Empty target path
    </e>
    <e id="ELAB-E-156">
        '%s': Met a invalid gate type: G_INVALID_TYPE
    </e>
    <e id="ELAB-E-157">
        '%s': Gate inst misses its terminal(s)
    </e>
    <e id="ELAB-E-158">
        Meet illegal constant, cannot get the real value, please check
    </e>
    <e id="ELAB-E-159">
        '%s': New array element indices' size doesn't match the origin array dimensions' size
    </e>
    <e id="ELAB-E-160">
        Meet invalid net value while processing %s
    </e>
    <e id="ELAB-E-161">
        Failed to get net when processing %s
    </e>
    <e id="ELAB-E-163">
        Failed to create net when processing %s
    </e>
    <e id="ELAB-E-164">
        Failed to get concat event expression
    </e>
    <e id="ELAB-E-165">
        Unexpected null name
    </e>
    <e id="ELAB-E-166">
        Meet NULL formal argument while processing %s
    </e>
    <e id="ELAB-E-167">
        Meet NULL actual argument while processing %s
    </e>
    <e id="ELAB-E-169">
        Member variable is NULL when processing %s, which is unexpected
    </e>
    <e id="ELAB-E-173">
        Mutually exclusive appears when dealing with disable condition %s
    </e>
    <e id="ELAB-E-174">
        Expression bitwidth doesn't match the corresponding net bitwidth while processing %s
    </e>
    <e id="ELAB-E-175">
        Unexpected null expression
    </e>
    <e id="ELAB-E-176">
        Failed to get net
    </e>
    <e id="ELAB-E-177">
        Failed to get sense-list net initial value
    </e>
    <e id="ELAB-E-178">
        Failed to get module while processing %s
    </e>
    <e id="ELAB-E-179">
        Meet null id when processing %s
    </e>
    <e id="ELAB-E-181">
        %s: Signed flag of return value and function is different
    </e>
    <e id="ELAB-E-182">
        Unexpected null expression while processing %s
    </e>
    <e id="ELAB-E-183">
        Meet unexpected null element while traversing
    </e>
    <e id="ELAB-E-184">
        type mismatch in subprogram port
    </e>
    <e id="ELAB-E-185">
        ADB database is empty
    </e>

	<!-- Error messages 'end'-->

    <!-- Message related with Flow&step -->
    <i id="FLOW-000">Start "%s" ... </i>
    <i id="FLOW-001">Done "%s"</i>

    <!-- Message related with FSM handling-->
    <e id="FSM001">Invalid FSM setting value %d of argument %s, should be in range (%d,%d)</e>

    <!-- 	Message that should be printed out using MSG_RTL 	-->
    <i id="FSM300">Skip FSM optimization of "%s" -- number of states (%d) exceeds limit (%d) </i>
    <i id="FSM305">Skip FSM optimization of "%s" -- input bit size (%d) exceeds limit (%d)</i>
    <i id="FSM306">Skip FSM optimization of "%s" -- at state "%s", input bit size (%d) exceeds limit (%d)</i>
    <i id="FSM310">Skip FSM optimization of "%s" -- output bit size (%d) exceeds limit (%d)</i>
	<i id="FSM315">Skip FSM optimization of "%s" -- number of STT item (%d) exceeds limit (%d). FYI: state#=%d, input-bits=%d</i>
    <i id="FSM320">Skip FSM optimization of "%s" -- state bit size (%d) exceeds limit (%d)</i>

    <i id="FSM400"><![CDATA[Optimizing FSM]]></i>
    <w id="FSM400-0">For state register "%s", invalid initial value "%s" is !IGNORED!</w>
    <i id="FSM400-1"><![CDATA[               State register : %s]]>"</i>
    <i id="FSM400-2"><![CDATA[               State encoding : %s]]>"</i>
    <i id="FSM400-3"><![CDATA[   state# before optimization : %d]]>"</i>
    <i id="FSM400-4"><![CDATA[   state# after  optimization : %d]]>"</i>
    <w id="FSM400-5">FSM of state register "%s" has no default branch found! </w>
    <i id="FSM400-S">======================================================</i>
    <i id="FSM400-6">Parallel-Mux is %s excluded</i>
    <i id="FSM400-7">Extract CE out of candidate state reg: %s</i>
    <i id="FSM400-8">CE of DFF %s is recovered</i>

    <!-- Message related with MUX optimization-->
    <i id="MUX000">Start MUX optimization</i>
    <i id="MUX001">Done MUX optimization</i>
    <i id="MUX100">unexpected boundary data nets num = %d (not 1) on mux out net: %s</i>
    <w id="MUX101">MUX's %d-th control fanin EQ node is unexpected</w>

    <i id="MUX-200">%d-th mux2-chain (size = %d) is optimized</i>
    <i id="MUX-201">Totally %d (among %d) mux2-chains %s optimized</i>
    <i id="MUX-202">Too big parallel/priority mux encountered: #ctrl_width = %d, #impl_cnt of off_set = %d, mux-opt not handle it</i>
    <w id="MUX-203">%s</w>
    <w id="MUX-204">%s</w>
    <i id="MUX-205">try to partition a mux%d</i>
    <i id="MUX-206">%s</i>
    <i id="MUX-207">did %d partition</i>

    <e id="MUX-301">Unexpected: Not find successive MUX for mux %s</e>
    <e id="MUX-302">Unexpected: Not get successive mux unit for %s !</e>
    <e id="MUX-303">Unexpected type %d of Mux %s !</e>
    <e id="MUX-304">Unexpected: Parallel/Priority MUX %s has no EQ/Decoder as control fanin!</e>
    <e id="MUX-305">Net %s has no driver terminal!</e>
    <e id="MUX-306">Unexpected EQ node %s found !</e>
    <e id="MUX-307">Unexpected: Net %s still has sub-nets !</e>
    <e id="MUX-308">Unexpected: Not find mux %s in the hash-set !</e>
    <e id="MUX-309">Unexpected: Failed to remove pre-mux of mux %s !</e>
    <e id="MUX-310">Unexpected: Split %s by %s into list failed!</e>
    <e id="MUX-311">Unexpected: Mux %s has no data terminals!</e>
    <e id="MUX-312">MuxTree::hasShareData() doesn't work for two same mux unit!</e>
    <w id="MUX-313"> homo-mux-tree (%d trees), recoding result of 1st tree is not integrity w.r.t boundary net, give up replacement of other trees</w>
    <e id="MUX-314">Unexpected: size (%d) of boundary_data_ is less than that (%d) of idx_map!</e>
    <e id="MUX-315">Unexpected: Net %s has different bit-width from net %s: %d vs. %d !</e>
    <e id="MUX-316">Unexpected: Empty vector found!</e>

    <w id="MUX-317">Unexpected: Empty mark_cnets_map_! Something wrong in recoding to first mux of homo-mux-opt</w>
    <w id="MUX-318">Unexpected: Not get ctrl nets for MuxCtrlMark below! Something wrong in recoding to first mux of homo-mux-opt</w>
    <e id="MUX-319">Unexpected: Something wrong in recoding of %s</e>

    <!-- Message related with RAM-->
    <i id="RAM-INFER-000">Found single-port RAM, depth=%d, width=%d</i>
    <i id="RAM-INFER-001">Found dual-port   RAM, depth=%d, width=%d</i>
    <i id="RAM-INFER-002">Found RAM, depth=%d, width=%d</i>
    <i id="RAM-INFER-003">Found (%d) candidate CdfgProcAssign</i>
    <i id="RAM-INFER-004">%s</i>

    <w id="RAM-INFER-010">RAM "%s", ADDR variable "%s" access scope [%d:%d] is out of declared scope [%d:%d], extra WE generated</w>
    <w id="RAM-INFER-011">write-address "%s" with width = %d can't fully address RAM "%s" whose depth = %d</w>
    <e id="RAM-INFER-012">Unexpected: RAM "%s" has set depth = %d, but its other ArraryElementWrite Node has depth = %d, MISMATCH</e>
    <w id="RAM-INFER-013">byte-width of BE-RAM "%s" on addr "%s" is not uniform: %s</w>
    <w id="RAM-INFER-014">BE-RAM "%s", byte-data of width %d is driven by a net of width %d, width mis-match</w>
    <w id="RAM-INFER-015">BE-RAM "%s", driver node of %d byte-data is neither ConstIdxRangeRead nor ConstIdxBitRead, Data sort not work</w>
    <w id="RAM-INFER-016">BE-RAM "%s", Not get valid index for %d byte-data, Data sort not work</w>
    <w id="RAM-INFER-017">Candidate RAM "%s" has mixed styles of if-elseif and byte-enable</w>
    <e id="RAM-INFER-018">Candidate RAM "%s" has %d data-ins, but their bit-widths are not uniform, Unexpected</e>
    <w id="RAM-INFER-019">Candidate RAM "%s" has different width of write data: %d vs. %d</w>
    <w id="RAM-INFER-020">Abandon infer RAM for candidate with depth=%d, width=%d, #ports=%d, #write_ports=%d</w>

    <e id="MEM-CHK-021">Unable to process multi-dimension net "%s" -- size (%d) exceeds limit (%d)</e>

    <w id="RAM-INFER-022">Unsupported value of RAM synthesis directive of %s = %s . Ignored</w>
    <i id="RAM-INFER-023">RAM "%s" has synthesis directive: %s = %s, NOT infer RAM</i>

    <w id="RAM-INFER-024">RAM "%s", begin index of write-nodes of if-elseif RAM are different: %d vs. %d, unexpected</w>
    <w id="RAM-INFER-025">Candidate RAM "%s" has %d write-ports with different width: %s Can't infer RAM</w>
    <w id="RAM-INFER-026">RAM "%s", WritePort (ADDR: %s, DI: %s) has no direct write-enable DataMerge</w>
    <w id="RAM-INFER-027">Candidate RAM "%s" has %d (>1) sensitive signals, normally should be only one</w>
    <i id="RAM-INFER-028">RAM "%s", %d read-ports with same address (addr: %s) are merged into one</i>
    <i id="RAM-INFER-029">Unexpected: For candidate BE-RAM, #data != #we!, %d vs. %d</i>
    <i id="RAM-INFER-030">Unexpected: %d piece of data %s has %d drivers, not unique!</i>
    <i id="RAM-INFER-031">Node "%s" appears to be a fake RAM</i>
    <i id="RAM-INFER-032">RAM "%s", %d read-ports (ADDRs: %s) on one DataMerge are merged into one</i>
    <i id="RAM-INFER-033">RAM "%s", %d write-ports (ADDRs: %s, DIs: %s) are merged into one</i>
    <w id="RAM-INFER-034">Candidate RAM "%s" with %d ports can't be inferred: #read-write=%d, #write-only=%d, read-only=%d</w>
    <e id="RAM-INFER-035">RAM "%s", unexpected happens when generating write controls for a write-port (ADDR: %s, DI: %s)</e>
    <w id="RAM-INFER-036">RAM "%s", Unexpected data-merge node to infer write-port of a ram: its %d data-in net's driver DataMerge node has no write-node fanin</w>
    <w id="RAM-INFER-037">RAM "%s", Unexpected data-merge node to infer write-port of a ram: its %d data-in net is driven by neither write-node nor data-merge</w>
    <w id="RAM-INFER-038">RAM "%s", Unexpected data-merge node to infer write-port of a ram: not get any write net</w>
    <w id="RAM-INFER-039">RAM "%s", ADDR variable "%s" is %s while RAM's access index is %s : [%d:%d]</w>
    <e id="RAM-INFER-040">RAM "%s", byte-enable RAM has un-uniform byte number on different ports: %d vs. %d, Not support</e>
    <i id="RAM-INFER-041">RAM "%s", data-width of port of ADDR "%s" is extended from %d to %d</i>
    <e id="RAM-INFER-042">RAM "%s", byte-enable RAM has different un-uniform patterns of byte-width on different ports, Not support</e>
    <w id="RAM-INFER-043">Candidate true-dual-port RAM "%s" has async-read port(s): %s, BRAM/DRAM implementation is not possible and dissolved into registers</w>
    <w id="RAM-INFER-044">RAM "%s" has async-read port(s): %s, true-dual-port distributed RAM is inferred but impossible to implement</w>
    <w id="RAM-INFER-045">RAM "%s" has repeated write-in by data-in "%s" and addr "%s" </w>
    <e id="RAM-INFER-046">RAM "%s", byte-enable RAM has un-uniform byte number on different ports: %d vs. %d, Not support</e>
    <w id="RAM-INFER-047">RAM "%s" has only write-port and no read-port</w>
    
    <w id="RAM-INFER-050">Duplication of node of type %s is not supported yet, from which RAM-infer is infeasible</w>

    <!-- Message related with ROM-->
    <i id="ROM-INFER-000">Found ROM, depth=%d, width=%d</i>

    <i id="ROM-INFER-100">Not Infer ROM from CdfgDataMerge %s due to sparse INIT</i>
    <w id="ROM-INFER-101">Not Infer ROM from CdfgDataMerge %s due to its bit-width (%d) being different from that of followed CdfgContAssign (%d)</w>
    <w id="ROM-INFER-102">un-integrity Data-Merge encountered, abandon ROM infer</w>
    <i id="ROM-INFER-103">ROM "%s", length of ADDR "%s" is shrinked from %d to %d</i>
    <i id="ROM-INFER-104">ROM "%s", bit-width of ADDR "%s" is %d, ROM depth is shrinked from %d to %d</i>
    <i id="ROM-INFER-105">Candidate ROM has synthesis directive: %s = %s, NOT infer ROM</i>
    <w id="ROM-INFER-106">%d-th INIT: "%s" is illegal , abandon ROM infer</w>

    <!-- Message related with SRL-->
    <i id="SRL-INFER-000">Inferring SRL from Cdfg ... </i>
    <i id="SRL-INFER-001">SRL Inferred successfully!</i>
    <i id="SRL-INFER-002">Found shift register (%s), length=%d, width=%d</i>
    <i id="SRL-INFER-003">Merging SRLs in Cdfg %x</i>
    <i id="SRL-INFER-004">%d bus-SRLs are got from homo-SRLs by SRL-merge</i>
    <i id="SRL-INFER-005">Splitting SRLs in Cdfg %x</i>
    <i id="SRL-INFER-006">%d static-SRLs are split</i>
    <i id="SRL-INFER-007">Split SRL (length = %d, width = %d) into two SRLs with length of %d and %d</i>
    <i id="SRL-INFER-008">%s DFF %s of DFF-chain (length = %d) is not inferred into SRL</i>
    <i id="SRL-INFER-009">DFF-chain (with length = %d, width = %d, first-FF: %s) is not inferred into RAM-based SRL</i>
    <w id="SRL-INFER-010">Some FFs of SRL have INIT while others not. Set INIT %s to those without</w>
	<w id="SRL-INFER-011">%s is not inferred by %s because the device does not support it</w>

    <w id="SRL-INFER-101">Candidate dynamic SRL to infer with #dff = %d, bin-mux with #data = %d, Unexpected!</w>
    <w id="SRL-INFER-102">Mismatch found for candidate dynamic SRL: %d-th #dff doesn't connect with %d-th data of bin-mux</w>

    <!-- Message related with SEQ infer-->
    <w id="SEQ-INFER-001">A Non-standard flip-flop is inferred for "%s", because edge and condition may mismatch on async control "%s" </w>
    <w id="SEQ-INFER-002">if condition of async control "%s" does not match its edge in sensitivity list</w>
    <e id="SEQ-INFER-003">Logic for "%s" does not match a standard flip-flop</e>
    <w id="SEQ-INFER-004">if condition contains unexpected %s logic of async controls in sensitivity list</w>
    
    <!-- Message related with SEQ infer-->
    <w id="ACC-INFER-001">Load Value of candidate accumulator %s is %d, skip size-shrink</w>
    <i id="ACC-INFER-002">infer ACC from DFF "%s" with INIT %s </i>
    
	<!-- Message related with MG-->
	<e id="MG-EXC-001">Exception found when processing macro : %s</e>
    <e id="MG-EXC-002">
        Unable to infer block RAM for "%s" that has multiple processes
    </e>

    <e id="MG-ROM-001">Currently addr-partition can't work for user sync-ROM %s on macro-lib-ROM %s</e>

    <i id="MG-ROM-010">%s Data width of ROM "%s" is shrinked from %d to %d</i>
    <w id="MG-ROM-011">%s ROM "%s" (width=%d, depth=%d) is totally simplified and removed</w>

    <e id="MG-RAM-001">%s, RAM %s is not implemented by block-ram although with such synthesis directive</e>
    <e id="MG-RAM-002">Unexpected: %s, RAM %s has %d ports</e>
    <w id="MG-RAM-003">%s, RAM %s : #ports is reduced from %d to %d ..</w>
    <w id="MG-RAM-004">%s, Very small %s "%s" (size = %d) is implemented by block-ram under such synthesis directive</w>
    <e id="MG-RAM-005">%s, RAM %s, in RamInfCell::addPort, unexpected port name got: "%s", xdname[1] should be a digit</e>
    <e id="MG-RAM-006">%s, RAM %s, in RamInfCell::moveRamDout2FFqout,varDo has %d nets, but #FFqnets = %d, NOT same, Unexpected</e>
    <w id="MG-RAM-007">%s, RAM %s, DOUT of port %d (%s) has %d dangling nets</w>
    <e id="MG-RAM-008">%s, RAM %s, data-width is unmatched between DI/DO: %d vs. %d, Unexpected</e>
    <e id="MG-RAM-009">%s, RAM %s, %s has dangling DOUT bit(s) on its ASYNC-read port %d, CAN'T be supported</e>
    <e id="MG-RAM-010">%s, RAM %s, RAM with unmatched DI/DO width at port-%d: %s width = %d vs. %s width = %d</e>
    <e id="MG-RAM-011">%s, RAM %s, True-Dual-Port RAM has %d async-read port: port-%s, Unexpected</e>
    <w id="MG-RAM-012">%s, RAM %s with byte-width of %d; while for %s, RAM's byte-width is %s</w>
    <e id="MG-RAM-013">%s, RAM %s has %d ports and can't be supported</e>
    <w id="MG-RAM-014">%s, RAM %s, in RamInfCell::isAbsorbFF,varDo has %d nets, but #FFqnets = %d, dout-FF can't be absorbed</w>
    <w id="MG-RAM-015">WARN: All nets of RamInfPort::Var %s are NULL, abnormal</w>
    <e id="MG-RAM-016">%s, too huge %s %s with addr-width of %d, need %d %s to implement</e>
    <w id="MG-RAM-017">%s, RAM %s, Remove useless DI/DO.. </w>
    <w id="MG-RAM-018">%s, RAM %s, Data width are shrinked from %d to %d. Shrinked bits are.. </w>
    <w id="MG-RAM-019">%s, RAM %s, Data-shrink not done due to .. </w>
    <i id="MG-RAM-020">%d macro nodes are ungrouped before macro build </i>
    <i id="MG-RAM-021">%s, RAM %s is %s, write-mode of both ports are set to %s</i>
    <w id="MG-RAM-022">%s, RAM %s has big size of %d (%d X %d) but is NOT implemented by block-ram!</w>
    <w id="MG-RAM-023">%s, RAM "%s" read-port's addr-ff "%s" has %s, unable to compact with some write-port</w>
    <i id="MG-RAM-024">%s, RAM "%s", read-port %d with ADDR-FF is compacted with write-port</i>
    <i id="MG-RAM-025">%s, Very small partitioned residual of %s "%s"  (size = %d) may not be implemented by block-ram although with such synthesis directive</i>
    <i id="MG-RAM-026">Very small partitioned residual of %s "%s"  (size = %d) may not be implemented by block-ram although with such synthesis directive</i>
    <e id="MG-RAM-027">%s, RAM %s has no ADDR on port-%d, unexpected</e>
    <w id="MG-RAM-028">%s, RAM %s has neith DI nor DO on port-%d</w>
    <e id="MG-RAM-029">%s, RAM %s has different address size at different ports: port-%d's mem_size = %d vs. port-%d's: mem_size = %d</e>
    <e id="MG-RAM-030">%s, RAM %s, data-width of ports is NOT SAME : port-%d = %d vs. port-%d = %d</e>

    <w id="MG-SRL-001">SRL %s is not implemented by ram although with such synthesis directive</w>

    <e id="MG-INIT-001">%s, for RAM %s, InitMap::map4Block() meets unexpected data width: src_data_width = %d, init_data_width = %d, initp_data_width = %d</e>
    <e id="MG-INIT-002">%s, for RAM %s, in InitMap::map4Block(), data_width_ = %d, while expected value is 36/72/32/64</e>
    <e id="MG-INIT-003">%s, for RAM %s, t_init = %s, whose length NOT equal to data_width_ = %d</e>
    <w id="MG-INIT-004">%s, for RAM %s, target macro cell %s has unexpected addr_width: %d, should be only 5 or 6</w>
    <w id="MG-INIT-005">%s, for RAM %s, Different size of INIT elements found: %s vs. %s</w>
    <w id="MG-INIT-006">%s, for RAM %s, Unexpected: Generate RAM's INIT %s, its length (%d) exceeds %d</w>
    <w id="MG-INIT-007">%s, for RAM %s, target macro cell %s has unexpected data_width: %d, should be 2/4/8</w>

    <e id="MG-DFF-000">MacroDFF %s contains non-DFF instances, causing initial value information loss</e>
    
    <!-- Message related with DSP MG -->
    <i id="MG-DSP-000">module(%s) with synthesis directive: %s = %s, instance(%s) will be mapped to logic not DSP</i>
    <i id="MG-DSP-001">module(%s) with synthesis directive: %s = %s, instance(%s) will be mapped to DSP</i>
    <i id="MG-DSP-002">net(%s) with synthesis directive: %s = %s, its driver(%s) will be mapped to logic not DSP</i>
    <i id="MG-DSP-003">net(%s) with synthesis directive: %s = %s, its driver(%s) will be mapped to DSP</i>
    <i id="MG-DSP-004">net(%s) with synthesis directive: %s = %s, its driver(%s) is the cadidated for DSP mapping</i>
    <i id="MG-DSP-005">module(%s) with synthesis directive: %s = %s, instance(%s) is the cadidated for DSP mapping</i>
    <w id="MG-DSP-006">instance(%s) cannot be mapped into DSP although its output net with synthesis directive: %s = %s</w>
    <w id="MG-DSP-007">instance(%s) cannot be mapped into DSP although its module with synthesis directive: %s = %s</w>

    <!-- Message related with DSP ACC -->
    <i id="MG-ACC-000">Following %d %s are merged into one: </i>
    <i id="MG-ACC-001">%d accumulator(s) are rebuild </i>

    <!-- Message related with HqInsight handling-->
    <i id="INSIGHT-000">Session to Jtag server %s:%d is successfully set up</i>
    <w id="INSIGHT-001">A session is already set up</w>
    <e id="INSIGHT-002">La index %d is out of the valid range [0, %d]</e>
    <w id="INSIGHT-003">Fail to connect to the Jtag server</w>
    <e id="INSIGHT-004">Error occurred for the Jtag connection. Please close the session and restart it</e>
    <e id="INSIGHT-006">Error occurred when initializing LA commands</e>
    <e id="INSIGHT-008">Error occurred when reading memory from LA "%d"</e>
    <e id="INSIGHT-009">Error occurred when operating on the Jtag</e>
    <e id="INSIGHT-010">Please load DDF file first</e>
    <e id="INSIGHT-011">The dimension size of data read from device is not equal with the value specified in DDF file</e>
    <e id="INSIGHT-012">No signals are specified to dump out in DDF file</e>
    <e id="INSIGHT-013">Error occurred when setting offset for LA %d</e>
    <e id="INSIGHT-014">Error occurred when reading status of LA %d</e>
    <e id="INSIGHT-015">Error occurred when resetting LA %d</e>
    <e id="INSIGHT-016">No trigger condition is set for LA %d</e>
    <e id="INSIGHT-017">Condition index %d is not in the valid range [%d, %d]</e>
    <w id="INSIGHT-019">No session exists. Please use insight.start to start a session</w>
    <e id="INSIGHT-020">Offset %d is not in the valid range [%d, %d]</e>
    <e id="INSIGHT-021">Operation %s for condition %d is invalid</e>
    <e id="INSIGHT-022">Operand %s for condition %d is invalid. Please check the format and the length</e>
    <e id="INSIGHT-030">Error occurred when loading DDF file %s</e>
    <e id="INSIGHT-040">%s: root element is not found</e>
    <e id="INSIGHT-041">%s: device family %s is not supported. Supporting family includes VIRTEX, VIRTEXE, VIRTEX2, VIRTEX5 and SPARTAN3</e>
    <w id="INSIGHT-043">%s: design element is absent or its value is empty</w>
    <e id="INSIGHT-044">%s: family element is absent or its value is empty</e>
    <w id="INSIGHT-045">%s(%d): refclk element is not defined for the la_core</w>
    <w id="INSIGHT-046">%s(%d): error occurs when creating clock for the la_core</w>
    <w id="INSIGHT-047">%s(%d): trigger element is not defined for the la_core</w>
    <w id="INSIGHT-048">%s(%d): error occurs when creating trigger for the la_core</w>
    <w id="INSIGHT-049">%s(%d): storage element is not defined for the la_core</w>
    <w id="INSIGHT-050">%s(%d): error occurs when creating storage for the la_core</w>
    <w id="INSIGHT-051">%s(%d): error occurs when creating the la_core</w>
    <w id="INSIGHT-052">%s(%d): error occurs when creating the condition</w>
    <w id="INSIGHT-053">%s(%d): depth element is not defined for the storage</w>
    <w id="INSIGHT-054">%s(%d): error occurs when creating the signal for the storage</w>
    <w id="INSIGHT-055">%s(%d): type element is absent or its value is not supported for the condition</w>
    <w id="INSIGHT-056">%s(%d): op element is absent or its value is not supported for the condition</w>
    <w id="INSIGHT-057">%s(%d): operand element is absent or its value is invalid for the condition. Please check the format and the length</w>
    <w id="INSIGHT-058">%s(%d): error occurs when creating the signal for the condition</w>
    <w id="INSIGHT-059">%s(%d): name element is absent or its value is empty for the signal</w>
    <w id="INSIGHT-060">%s(%d): file element is absent or its value is empty for the signal</w>
    <w id="INSIGHT-061">%s(%d): line no element is absent or its value is empty for the signal</w>
    <w id="INSIGHT-062">%s(%d): error occurs when creating the bit for the signal</w>
    <w id="INSIGHT-063">%s(%d): net element is absent or its value is empty for the bit</w>
    <w id="INSIGHT-064">%s(%d): net element is absent or its value is empty for the clock</w>
    <w id="INSIGHT-065">%s(%d): period element is absent or its value is empty for the clock. Default 10ns is used</w>
    <e id="INSIGHT-066">The size of Trigging windows is too large</e>
    <i id="INSIGHT-067">Dumping VCD file %s</i>
    <i id="INSIGHT-068">Done with dumping VCD file</i>
    <i id="INSIGHT-069">Generating IP file</i>
    <i id="INSIGHT-070">Done with generating IP file</i>
	<e id="INSIGHT-071">module%s no ports</e>
	<i id="INSIGHT-072">Error the design top netlist does not exist</i>

    <w id="INSIGHT-080">Fail to connect to the JTAG cable</w>
    <w id="INSIGHT-081">Connected to libftd2xx driver</w>
    <w id="INSIGHT-082">Fail to open svf file</w>

    <!-- Message related with macro unmap-->
    <e id="DSP-UNMAP-001">Non-constant net %s found on port %s of DSP %s, NOT support</e>
    <e id="DSP-UNMAP-002">Unmap FAILED due to DSP %s has more nets on port C than P (%d vs. %d)</e>
    <e id="DSP-UNMAP-003">Single DSP %s has cascaded output (PCOUT/ACOUT/BCOUT), which is not supported by DSP unmap!</e>
    <e id="DSP-UNMAP-004">DSP %s has attribute %s = %s, which is not supported by DSP unmap!</e>
    <e id="DSP-UNMAP-005">DSP group %s has different addsub: %s , %s, not supported by DSP unmap!</e>
    <e id="DSP-UNMAP-006">DSP group %s has addsub but unsupported ALUMODE, not supported by DSP unmap!</e>
    <e id="DSP-UNMAP-007">OPMODE = %s, ALUMODE = %s, not supported by DSP retarget</e>

    <e id="DSP-UNMAP-010">FAILED to unmap %d DSPs: %s</e>
    <e id="DSP-UNMAP-011">%s DSP Unmap in Nview %x FAILED!</e>
    <i id="DSP-UNMAP-012">Unmap %s %s%s %s</i>
    <i id="DSP-UNMAP-013">Succeed to remap	%s (%s) into %s</i>
    <i id="DSP-UNMAP-014">Retarget %s %s%s ...</i>
    <w id="DSP-UNMAP-015">FAILED to unmap a DSP-group of %d DSPs: %s</w>
    <i id="DSP-UNMAP-016">Succeed to preprocess %s (%s): mapped into Xist dsp</i>

    <i id="BRAM-UNMAP-101">%s retarget %s (%s)</i>
    <w id="BRAM-UNMAP-102">%s %s (depth = %d, width = %d) NOT retarget to block_ram</w>
    <e id="BRAM-UNMAP-103">Block RAM retarget FAILED</e>

    <e id="BRAM-UNMAP-001">Not unmap RAMB %s due to not support DO_REG=1</e>
    <e id="BRAM-UNMAP-002">Not unmap RAMB %s due to not support byte-wide-write-enable</e>
    <w id="BRAM-UNMAP-003">Not unmap RAMB %s which has no valid CLOCK on both port A and B</w>
    <e id="BRAM-UNMAP-004">Two ports of RAM %s have different data width: %d vs. %d</e>
    <w id="BRAM-UNMAP-005">As a ROM, %s %s has %d un-initialized words and set to 0. Their hex addr are: %s</w>
    <e id="BRAM-UNMAP-006">for RAM %s, its port %s has non-const net %s, cascade RAM is not support</e>
    <e id="BRAM-UNMAP-007">#parity-bit = %d, data_width = %d, data_width % parity_bits != 0, unexpected</e>
    <e id="BRAM-UNMAP-008">for RAM %s, at port-%d, merge %s into DI failed</e>
    <e id="BRAM-UNMAP-009">unexpect bye_width (%d), neither 9 or 8</e>
    <i id="BRAM-UNMAP-010">RAM "%s" is asym whose two ports are of different aspect-ratio: %dX%d vs. %dX%d</i>
    <e id="BRAM-UNMAP-011">both ports of RAM "%s" are empty after data-trim, delete it directly</e>
    <e id="BRAM-UNMAP-012">Two ports of RAM "%s" have unexpected width of WE, %d vs. %d</e>
    <e id="BRAM-UNMAP-013">BE-RAM "%s" has WE width of %d and data-width of %d, unexpected</e>
    <e id="BRAM-UNMAP-014">RAM "%s", port %d with data-width of %d and WE width of %d, unexpected</e>
    <e id="BRAM-UNMAP-015">RAM "%s", two ports have different byte-width: %d vs. %d, unexpected</e>
    <i id="BRAM-UNMAP-016">RAM "%s", byte-width of both ports are 0 , possibly as two ROMs</i>
    <e id="BRAM-UNMAP-017">RAM %s, unexpect happens when running RamPort::trimDataWe(trim_idx, byte_width)</e>
        
		<e id="ASYM-RAM-000">FAIL to retarget RAM "%s"</e>
    <w id="ASYM-RAM-001">Asym RAM "%s" has non-zero INIT</w>
    <w id="ASYM-RAM-002">Asym RAM "%s" whose two ports have data-width: %d vs. %d, Can't retarget to one 36K ERB</w>
    <w id="ASYM-RAM-003">Asym RAM "%s" have two ports with data-width of dw0 = %d, dw1 = %d: dw0/dw1 must be 2^n and n is in [-4,4]</w>
    <e id="ASYM-RAM-004">target RAM "%s" has data-width of %d, unexpect</e>
    <e id="ASYM-RAM-005">Asym RAM "%s" whose two ports have data-width: %d vs. %d, unexpect</e>
    <e id="ASYM-RAM-006">From target RAM "%s", Not get %s-%d , unexpect</e>
    <w id="ASYM-RAM-007">Asym RAM "%s" is Byte-enable</w>
    
    <e id="MACRO-UNMAP-001">Macro Retarget FAILED</e>
    <i id="MACRO-UNMAP-002">Totally retarget %d %s</i>

    <!-- Message related with Accumulator-->
    <e id="ACC-E-000">The Accumulator %s output bit width %u is less than the required shrink size %u</e>
    <e id="ACC-E-001">The shrink size %u is non-positive</e>
    <e id="ACC-E-002">The Accumulator %s has floating ports</e>
    <e id="ACC-E-003">The Accumulator %s failed to be converted into a UDM instance</e>
    <e id="ACC-E-004">The enable signal of the DFF %s undergoing Accumulator inference is not driven by an INV-EQ or NE node</e>
    <e id="ACC-E-005">An erroneously structured datamerge was encountered during the Accumulator inference</e>
    <e id="ACC-E-006">Encountered an unexpected node type</e>

    </messages>
