******************************************************************* v* * HqFpga-XIST V3.0.6 Fast Track Build Release Note * ******************************************************************* * UPDATE HISTORY * [11/01/2025] V3.0.6 FT110125 - IP Creator IP updates: fl_ufm_ctrl_sl2_2k, SerDes,ERB Refine default right-click menu behavior of toolbars Fix the problem that the user manual cannot be opened under Linux - HqInsight Support X-value (mask) trigger Corrects signal capture and start-up problems related to two-dimensional packed array - Bitgen Fix the problem that Sealion 12k/25K devices cannot close OSC Correct configuration problems related to ECLK of sealion 15K - Packing Correct the cascade attribute of PLL O5/O6/O7 - RTL synthesis Support using the reg initial value to initialize RAM Refine handling of RAM INIT value and RAM capacity mismatches Improve empty statement handling Fix for loop statement iteration count in initial and function - Routing Minor reduction of runtime and improve of QoR - Design interface Print capture clock delay and skew in timing report [10/29/2025] V3.0.6 FT102925 - Bitgen **Fix 2-bit CSDECODE fuse issue for Seal 30k/50K devices - Design interface Update simulation model for xsBRAM16KTD_E0 and xsBRAM32KTD - RTL synthesis Enhance ByteEnable and SDP RAM inference/retargeting [10/27/2025] V3.0.6 FT102725 - RTL synthesis Fix a bug in ODC related with uni-directional "inout" port driven by combinational logic Refine message-prompt and handling of multi-driven net Fix issues related with empty port - Design interface Fix crash issue reading EDIF with VLA IP Update simulation model for xsBRAM16KS_E0 - IP Creator PLL IP: support cascaded port [10/26/2025] V3.0.6 FT102625 - RTL synthesis Fix a crash issue related with accumulator inference. fix issue related with dynamic and static shift register Update inference of RAM of OUTREG with different CE and OCE Extend Verilog parser to support System Verilog define - Downloader (Main program updates to V5.7) Fix hscable file for offline setting of efuse_aes key Update USB detection method of - IP Creator ERB IP updates to V3.2 (CE/OCE related) - HqInsight Support array and logic type of signal instrument - Place & Route Enhance ERB legalization related with OE/OCE/CSDECODE Improve initial placement for better clock assignment for Seal 200K device Improve delay correlation between place and route - Design interface Fix RTL resource report issue of DDR-co-packaged device Fix DSP resource report issue of Sealion 22K device Update simulation models of Seal ERB primitive: xsBRAM16KTD_E0, xsBRAM16KS_E0, xsFIFO16KB_E0, xsBRAM32KTD_E1, xsBRAM32KS_E1 [10/22/2025] V3.0.6 FT102225 - RTL synthesis Fix a corner issue in RAM inference Fix HqInsight false syntax-error alarm due to module name with number prefix - Place & Route Fix a corner exception issue in normal-mode router for Sealion 22K device - IP Creator Fix IP generation failure issue due to IP module name with number prefix [10/20/2025] V3.0.6 FT102025 - IP Creator DSP_Calculator IP: fix issue under R=A0*B0+X mode - Design interface Set JTAG pins as dedicated IOs for Sealion 12k/25K devices. Update xsPLLSA simulation model by adding PREDIVIDER_MUXE1/F1/G1 parameters Correct total IO number of SL2E-15V-U484 from 384 to 383 - RTL Synthesis Extern Verilog parser to support limited SystemVerilog syntax: logic/int/enum,...etc. [10/18/2025] V3.0.6 FT101825 - Downloader (Main program updates to V5.6) Support off-line setting of efuse_aes key Fix bit2bin issue of Seal 200K device - IP Creator IP updates of ERB, DDRC and DSP_Calculator - GUI Timing analysis dialog by default setting Refine auto program update [10/15/2025] V3.0.6 FT101525 - Device support Update timing info for ERB clock-to-output, setup/hold of OCE/RST ports support xsTDDRSA/TDDRX1 (tri-state control DDR) primitive - Placement Fix clock assignment issue related with bidirectional clock IO. - RTL synthesis Fix an insight dumper issue related with constant conditional ternary expression in generate statement Refine optimization of MUX with sparse control logic - Main UI Upgrade design assistant Support auto-checking for updates. Fix issues related with constraint editor, file path, flow and design hierarchy [10/12/2025] V3.0.6 FT101225 - Downloader (Main program updated to V5.5) Fix issue in Sealion 2K and Seal 420k device - IP Creator Fix issue of failing to config DDRC IP in design explorer. CortexM3/STAR_Processor IP updates to V3.0 DDRC IP updates to V3.2 DSP_MULT IP: Fix issue related with Sealion 22K pipeline/OREG - Place & Route Improve placer QoR by increasing WNS by ~80ps - RTL Synthesis Improve message prompt related with design hierarchy dumper ,IOBI multi-driven, ..etc - Device Modeling Speed up loading device information [09/30/2025] V3.0.6 FT093025 - IP Creator FIFO_Generateor update related ERB OUTREG ERB IP updates to V3.0 SerDes IP updates to V3.1 DDRC IP updates for Seal 30k/100K devices - Device support Add new devices: SA5Z-33-D1-8U213CI, SA5Z-33-D2-8U256CI - Design interface Fix user IO count issue for SL2S-12E-E176 and SL2D-25E-N96 Add YAD0/1 port to xsBRAM32KS primitive - RTL synthesis Add option to disable ERB absorbing OUTREG SystemVerilog updates related with global type definition, array, etc. [09/28/2025] V3.0.6 FT092825 - Device support Rename SL2E-5E-8M121CI to SL2E-5E-8M121I Update MULT18/9 timing info for Sealion 22K device LVDS diffdrive=emphasis support for Seal 200K/420K device - IP Creator CM/Star IP: Fix GPIO_OUT_EN as active-low for uart-tx-gpio-port - Design interface Update simulation model of xsPCIE_E1 Fix corner crash issue in EDIF reader - Downloader // Main program updates to V5.4 Add DNA information for Sealion 22K device. // User interface updates to V3.0 Add MSEL configuration mode for Sealion device - RTL Synthesis Add xsCLA(CARRY4) keep support Add warning message for empty port Fix corner issue in ROM inference Further speed up redundant register and shift register removal - Place & Route Support xsCDELAY Reduce routing runtime by ~40% for Seal 200 device, 5% for Seal 100K device Enhance level2 effort-low-packing [09/22/2025] V3.0.6 FT092225 - HqInsight VLA debugger updates to support continuous triggering and multi-windows triggering VLA_VIO IPGEN : output plain netlist Fix issues related with non-standard port declaration - IP Creator QSGMII IP updates to V1.2 - Downloader // Main program updates to V5.3 Add support to JTAG chain Support bit2bin, AES, MSPI download function, for Sealion 15K devices Support read states for Seal 200K device // User interface updates to V3.0 Support actions to JTAG chain - Design interface Change routing assertion to normal error report Fix LUTA/B/C/D location constraint issue for Seal 420K device Fix issues in JSON dumper related with multi-instances of a module - RTL Synthesis Support structural resources merging, reduce ~3% of LUTs and registers Reduce RTL synthesis runtime by ~10% Speed up redundant register and shift register removal Speed up merging of shift registers Refine dataopt multi run Enhance ROM inference for default branch of sparse cases statement Refine attribute handling to support value as result of expression evaluation - Place & Route Reduce ~30% of router runtime for Seal 200K device [09/14/2025] V3.0.6 FT091425 - IP Creator Support of New IPs: MIPI_CSI2_RX, MIPI_DSI_TX - Design interface Update xsSPRAM1KX32 simulation model - Place & Route Reduce ~15% runtime of router for Seal 100K/200K devices. - RTL synthesis Refine/fix SRL merge Skip checking of conditional branch with false value Add cut based logic merge function - GUI Fix issue of heatmap of Seal 200K device [09/11/2025] V3.0.6 FT091125 - Device modeling Fix timing modeling issue for xsSPRAM1KX32 - Place & Route Update SADC/GADC PIO mapping for Seal 50K device Fix DNA/DDRC cib issues for Seal 420K device Wide-ERB can still absorb inv for CLK/CE/OCE - Design interface Fix looptdo issue related with SCLK handling of Sealion 22K device Fix HQ.xx variable register related warning Add block prefix for mem_name of readmem in generate statement [09/10/2025] V3.0.6 FT091025 - Device update Add hidden option to turn on un-supported IO_TYPE (e.g LVCMOS12) - Place & Route Packer: avoid absorb inv for CLK/CE/OCE/RST/WR/CS port of dual-capacity ERBs Reduce router runtime by ~30% for Seal 200K device [09/09/2025] V3.0.6 FT090925 - Main UI Fix issues related with design hierarchy, file path, constraint editor ... - HqInsight Fix VLA IP/debugger issues related with retargeting flow Fix design hierarchy issue related with backslash in signal name - IP Creator EBR IP: Optimize resource usage FIFO IP: Update related with rd_valid, RPRset, asynchronous options New DDRC IP support for Seal 200K devices - Design interface Fix stub issue of DDRCTRL_E4/E5 simulation model in last release Update simulation model for xsDQSBUFS reduce hierarchical resource report time - Device update Update SADC PDL pin connection for Seal 100K/200K/366K devices. Disable trans_mode for Sealion 22K device - RTL Synthesis Update shortcut condition checking Add option to control using carry chain for comparison logic Fix an issue in register CE-data co-optimization [09/03/2025] V3.0.6 FT090325 - RTL synthesis Fix a bug in accumulator combining. - Device modeling Update timing data for DDRCTRL of Seal 200K devices. - Design interface Update simulation models: DDRCTRL_E4/DDRCTRL_E5 [08/31/2025] V3.0.6 FT083125 - Device support Add xsDMP primitive support for Sealion devices - Main UI Fix design hierarchy refresh stuck issue due to backslash char in signal name - Downloader // Main program updates to V5.2 Fix cp pass flag for Seal 50K/100K devices Add 324 package info. fix package info for Sealion 7K device Add ADC of 200K sampling rate Add read-status register for Sealion 12k/25k devices // User interface updates to V2.9 Add "close package detection" option on toolbar. - RTL Synthesis Fix MUX optimization issue that cause long runtime in corner cases Fix issue of generic 0/1 primitive in synthesized netlist Refine XXX_L/D primitive retargeting support Refine RAM inference related with bit-wise write, DO2DI feedback - IP Creator DIVIDER IP updates to V2.0 FIR_Filter IP updates to V3.1 Serdes IP updates to V3.0 PLL IP: update CLKI/CLKOP frequency upper limit to 1G Hz for Seal 200k/420K devices - Others Fix router assertion issue in corner cases. [08/23/2025] V3.0.6 FT082325 - Main UI Fix issue related with trans_mode variable - Design interface Update simulation model for xsBRAM32KS and xsPCIE_E1 Fix crash issue when processing EDIF with abnormal connection. Fix hierarchical resource report issue related with non-uniquified modules - HqInsight Fix issues related with combined triggering Fix downward compatibility issues Refine messages on dialog-boxes - IP Creator PLL IP : support CLKOPD for Seal 420K device - RTL synthesis Fix a bug of merging two registers with different clock phases Refined carry chain unit handling related with selection Sweep multiplier and shift register with constant inputs Fix a FSM optimization issue that may insert dangling net Refine initial statement handling Refine synchronous set/reset extraction for Seal 200K device - Placement Refine clock assignment for Seal 200K device - Routing Refine DATA_SKEW handling [08/17/2025] V3.0.6 FT081725 - Device support Support IO configuration retain mode for Sealion devices. Support xsCEM as xsEFB primitive Add DDRCTRL_E7 support for Seal 420K devices - HqInsight Fix signal renaming issue in EDIF flow Fix issues related with combined signal triggering - RTL synthesis Fix stack overflow issue due to combinational loop in MUX optimization Fix runtime issue in MUX optimization of a corner case. - Design interface Fix typos in prompt messages Fix packing issue related regional constraint handling - Bitgen Update PIO enlvds fuse for Seal devices Fix DQSBUF issue for Seal 200K devices [08/12/2025] V3.0.6 FT081225 - RTL synthesis Refine FF sweep related with constant CE connection - Design interface Fix an issue of OSC STDBY pin wrongly absorbing VCC [08/10/2025] V3.0.6 FT081025 - Downloader Fix error in downloading JED file Fix remap dialog box losing focus issue when merging MCU and FPGA bins - IP Creator DSP_CALC_SEALION IP: remove support to Sealion 22K device - Device modeling Update timing info of SLICE and routing wire for Seal 200K device - RTL synthesis Refine carry chain combining and constant propagation - Place & Route Fix clock assignment issues for Seal 420K devices Fix latch->x5FF issue in running pack -effort std [08/04/2025] V3.0.6 FT080425 - Main UI Fix issue related IO_TYPE value after bank VCCIO changes. - Place & Route Enhance placement with ~2% FMAX improvement for Seal 100K device Fix issues related with SERDES/COM GHIGH and RCALSEL connections for Seal 200k/420K devices - RTL synthesis Refine data-opt effort checking. Refine xor/xnor sweep. Add CARRY4 retargeting support. [07/31/2025] V3.0.6 FT073125 - Place & route Refine effort-low-packing related with pth LUT-to-reg and pth latch - Main UI Project open lock refine Fix editor search issue while outputting log message Enable checking report for finished steps Add "forbid configuration read back" bitgen option - Design interface Add xsPCIE_E1 simulation model - Bitgen Support -fuse_protect option - IP Creator New IP support of LLCR ERB_FIFO IP: add FWFT mode - HqInsight Enhance multi-LA support (up to 16 instances) - RTL synthesis Enhance inferring of shift register with controls [07/27/2025] V3.0.6 FT072725 - IP Creator SerDes IP updates to V2.1 FIR_Filter IP updates to V3.0 Add ip_device cfg item PLL IP update with ip_device cfg item - Main UI Refine language template display and close action - RTL synthesis Minor refine LUT combine Fix issue of inconsistent input and output bit widths of gate instance [07/21/2025] V3.0.6 FT072125 - RTL synthesis Combine accumulator across hierarchy Refine handling of arithmetic operation with constant input Fix an issue related with bit-access to variable with large width - Design interface Fix res.report output to log issue [07/18/2025] V3.0.6 FT071825 - Downloader Update related with Seal 100K, 70K, 30K, 200K devices Fix downloading issue of internal efuse without package info. - Main UI Add pdp_ram_ip/dp_ram_ip in language template Add resource perspective report Fix issues related with timing/physical constraint, flow and file handling. - Design interface Update PLL simulation model for Seal/Sealion devices Update looptdo to optionally generate uncompressed bin/bit file - Device modeling Fix IOLOGIC LSR related timing arc issue [07/16/2025] V3.0.6 FT071625 - IP Creator PLL IP: enable dynamic phase shift configuration - RTL synthesis Enhance register merging Fix corner issues in FSM optimization - STA Fix issues related with combinational loop and latch Fix an issue related with chars preceding/succeeding object access command, e.g. [get_clocks]aaa [07/13/2025] V3.0.6 FT071325 - IP Creator SERDES IP: fix userclk2-value-error on summary page Prompt error when re-configuring old(unsupported) IPs - RTL synthesis Fix an issure related with DSP48E1 retargetting. Error out on constant function call with non-constant argument Refine message file path Refine shift register config options [07/11/2025] V3.0.6 FT071125 - RTL synthesis Fix a bug of wrongly merging FFs with different clock edge into one shift register - Place & Route Fix placer and router issues related with DQS/PCIE for Seal 420 device [07/09/2025] V3.0.6 FT070925 - GUI Fix placement viewer problem related with Sealion 22K device - Place & Route Fix issue related with DSP/SERDES/EBR/TAP/BPLL for Seal 420K device Fix a router pin swapping issue related with redundant LUT5 for Seal devices Effort-low packing: reduce ~80% runtime of unrelated packing - RTL synthesis Fix assertion problem related with negative MSB and multi-bit reg Enhance width calculation [07/06/2025] V3.0.6 FT070625 - IP Creator SerDes IP updates to V2.0 Correct EthMac.xml issue : default value out of range; Correct issue of missing comment's