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*   HqFpga-XIST V3.0.6 Fast Track Build Release Note
*
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* UPDATE HISTORY *

[08/12/2025]  V3.0.6 FT081225
- RTL synthesis
  Refine FF sweep related with constant CE connection
- Design interface
  Fix an issue of OSC STDBY pin wrongly absorbing VCC

[08/10/2025]  V3.0.6 FT081025
- Downloader
  Fix error in downloading JED file
  Fix remap dialog box losing focus issue when merging MCU and FPGA bins
- IP Creator
  DSP_CALC_SEALION IP: remove support to Sealion 22K device
- Device modeling
  Update timing info of SLICE and routing wire for Seal 200K device
- RTL synthesis
  Refine carry chain combining and constant propagation
- Place & Route
  Fix clock assignment issues for Seal 420K devices
  Fix latch->x5FF issue in running pack -effort std

[08/04/2025]  V3.0.6 FT080425
- Main UI
  Fix issue related IO_TYPE value after bank VCCIO changes.
- Place & Route
  Enhance placement with ~2% FMAX improvement for Seal 100K device
  Fix issues related with SERDES/COM GHIGH and RCALSEL connections for Seal 200k/420K devices
- RTL synthesis
  Refine data-opt effort checking.
  Refine xor/xnor sweep.
  Add CARRY4 retargeting support.

[07/31/2025]  V3.0.6 FT073125
- Place & route
  Refine effort-low-packing related with pth LUT-to-reg and pth latch
- Main UI
  Project open lock refine
  Fix editor search issue while outputting log message
  Enable checking report for finished steps
  Add "forbid configuration read back" bitgen option
- Design interface
  Add xsPCIE_E1 simulation model
- Bitgen
  Support -fuse_protect option
- IP Creator
  New IP support of LLCR
  ERB_FIFO IP: add FWFT mode
- HqInsight
  Enhance multi-LA support (up to 16 instances)
- RTL synthesis
  Enhance inferring of shift register with controls

[07/27/2025]  V3.0.6 FT072725
- IP Creator
  SerDes IP updates to V2.1
  FIR_Filter IP updates to V3.0
  Add ip_device cfg item
  PLL IP update with ip_device cfg item
- Main UI
  Refine language template display and close action
- RTL synthesis
  Minor refine LUT combine
  Fix issue of inconsistent input and output bit widths of gate instance

[07/21/2025]  V3.0.6 FT072125
- RTL synthesis
  Combine accumulator across hierarchy
  Refine handling of arithmetic operation with constant input
  Fix an issue related with bit-access to variable with large width
- Design interface
  Fix res.report output to log issue

[07/18/2025]  V3.0.6 FT071825
- Downloader
  Update related with Seal 100K, 70K, 30K, 200K devices
  Fix downloading issue of internal efuse without package info.
- Main UI
  Add pdp_ram_ip/dp_ram_ip in language template
  Add resource perspective report
  Fix issues related with timing/physical constraint, flow and file handling.
- Design interface
  Update PLL simulation model for Seal/Sealion devices
  Update looptdo to optionally generate uncompressed bin/bit file
- Device modeling
  Fix IOLOGIC LSR related timing arc issue

[07/16/2025]  V3.0.6 FT071625
- IP Creator
  PLL IP: enable dynamic phase shift configuration
- RTL synthesis
  Enhance register merging
  Fix corner issues in FSM optimization
- STA
  Fix issues related with combinational loop and latch
  Fix an issue related with chars preceding/succeeding object access command, e.g. [get_clocks]aaa

[07/13/2025]  V3.0.6 FT071325
- IP Creator
  SERDES IP: fix userclk2-value-error on summary page
  Prompt error when re-configuring old(unsupported) IPs
- RTL synthesis
  Fix an issure related with DSP48E1 retargetting.
  Error out on constant function call with non-constant argument
  Refine message file path
  Refine shift register config options

[07/11/2025]  V3.0.6 FT071125
- RTL synthesis
  Fix a bug of wrongly merging FFs with different clock edge into one shift register
- Place & Route
  Fix placer and router issues related with DQS/PCIE for Seal 420 device

[07/09/2025]  V3.0.6 FT070925
- GUI
  Fix placement viewer problem related with Sealion 22K device
- Place & Route
  Fix issue related with DSP/SERDES/EBR/TAP/BPLL for Seal 420K device
  Fix a router pin swapping issue related with redundant LUT5 for Seal devices
  Effort-low packing: reduce ~80% runtime of unrelated packing
- RTL synthesis
  Fix assertion problem related with negative MSB and multi-bit reg
  Enhance width calculation

[07/06/2025]  V3.0.6 FT070625
- IP Creator
  SerDes IP updates to V2.0
  Correct EthMac.xml issue : default value out of range;
  Correct issue of missing comment's <!-- in Fifo.xml
  Fix issue of old-version IP preventing ipcreator start-up
  Support cfg's default value with expression
  Fixed IP selection bug from IP by type to IP by name by add reset;
- Place & Route
  Fix placement issues that cause routing fail for Seal 420k device
- GUI
  Fix HQ internal variable persist-across-project problem

[07/03/2025]  V3.0.6 FT070325
- HqInsight
  Fix crash issue launching downloader
  Optimize multi-windows triggering support
- Device modeling
  Fix ALU54 C port setup/hold value for Seal devices
- Place & Route
  Fix a packer crash issue related with kept object referenced in timing constraint
  Fix issue: latch is configured as flip flop issue in normal mode packer
- RTL Synthesis
  Fix SRL combine issue related with long DFF chain
  Refine text format synthesis data import/export related with platform line-end (CR/LF)
- Design interface
  Fix life time issue for HQ.DEBUG.STEP variables
  Refine timer object keep behavior

[07/01/2025]  V3.0.6 FT070125
- Device support
  Support new device/package SL2E-2V-8M132CI
  Update device ID for Seal 70K
- Downloader
  Fix ID/DNA location issue for Seal 70K device
  Fix bit2bin issue for Seal 200K device
  Embedded flash SSPI interface is changed to SSPI or IIC selectable
- Place & Route
  Fix PCLK sub-group routing conflict issue for Seal 200K device
- RTL synthesis
  Refine constant propagation across MUXF7/8
  Refine shift register infer related wit PLL reset
- Design interface
  Fix bank3 IOREG reported as "unregistered" issue for Sealion 22K device
  Print catched message in case of step problem (e.g. related with opening file)

[06/29/2025]  V3.0.6 FT062925
- IP Creator
  VBO/LSSD/SDRAM_Controller IP: Unified example and ui-reminder
  FIFO_Generator IP: support prog_full/prog_empty range changed with write_address-width
  New IP support: pcie_endpoint IP v1.0
- GUI
  Fix issues related with terminal, EDIF project, file path
  Fix a issue with closing project in a long time.
- RTL synthesis
  Refine shift register inference and reduce runtime
- Place & Route
  Seal 200K clock assignment update
  Seal 200K router update for many clocks in
- Bitgen
  Add driver for unused GCLK track for Seal 366k/126k/200k devices
- Design interface
  Update simulation model and timing info for DDRCTRL_E4/DDRCTRL_E5

[06/22/2025]  V3.0.6 FT062225
- IP Creator
  EBR IP updates:
    fix issues related with 9K/18K configuration for Seal 30K device
    fix an issue related with 36K configuration for Seal 366K device
  UFM IP:  support SL2E-4V device
  Refine progress message when generating UFM IPGEN
- Bitgen
  Support differential/N-side input for Seal 100K device
  Fix an issue of SSTL15D_I IO_TYPE of bottom IOs in Sealion 22K device
- Place & Route
  Fix modeling issues of clock path between BPLL0 to region 9/13 for Seal 200K device
  Enhance effort-low packing : 3-way LC packing, greedy SLICE packing for Seal devices
- Device modeling
  Update timing data of PCI-E for Seal 200K device
- RTL Synthesis
  Support rtl.macro.define a macro without value
  Improve LUT-combine
  Enhance carry chain combine
  Enhance constant propagation across carry chain, MUXF7/MUXF8
  Enhance basic logic reduction
  Fix crash on mix-assignment assertion in task call
  Fix a DSP inference issue related with open CIN connection issue

[06/15/2025]  V3.0.6 FT061525
- GUI
  Support sort/filter columns in hierarchical resource report
  Design hierarchy view update: in case of multi-top-module candidates,
    display current top module in the front
- HqInsight
  Enhance main program and reduce ~50% memory consumption
  Fix debug issue in case of not using default module when generating VLA/VIO IP
- IP Creator
  EBR IP: Add resource type selection for Seal 100K/366K device
  PLL IP: disable phase-shift config-item for NON-Seal 30K devices
  HDL IP: support post-processing script
  Support enum used as numeric
  Fix synchronization issue of range type of item.
- RTL synthesis
  Support ROM/reg initial value assigned in initial statement
  Fix a stack-overflow problem in SDB processing
  Fix a crash problem caused by illegal(negative) repeat number
  Enhance debug support: refine message, support stack-trace
  Support '~' in include path
- Design interface
  Update simulation model of xsSERDES_COM_E2
  Fix clock pin 23 displayed as normal IO issue for SL2S-12E-EA176
- Place & Route
  Fix a crash problem caused by illegal PIO connection
  Refine resource report related with IPAD/OPAD (no count as user IO)
- Bitgen
  Update PCLK4/5 related settings for Sealion 2K device
  Enhance undriven long-line config

[06/05/2025]  V3.0.6 FT060525
- RTL synthesis
  Fix an assertion issue related with dummy array signal assignment like :
    reg [0:0] yyy [2:0]; wire [0:0] xxx = yyy[0];
  Refine message related with file path
  Fix a corner crash issue in RAM inference
- Place & Route
  Fix clock related issue in placement for Seal 200K device
  Improve router FMAX by ~2% for Seal devices

[06/04/2025]  V3.0.6 FT060425
- Downloader
  (main program updates to V4.6)
  Fix problems of merging bin file of Seal 30K devices
  (UI updates to V2.4)
  Adjust SVF download interface
- IP Creator
  Fixed display issue of range with expression
- RTL synthesis
  Fixed a crash issue on netlist with IBUF driving output port

[06/02/2025]  V3.0.6 FT060225
- IP Creator
  UI improvement related with output, value range, image and config description
  Support new IP: SGMII IP
  DDRC IP : updated to V2.3:
  DSP_Calculator IP: updated to v2.0
- RTL synthesis
  Fix a crash issue in if/else statement related with sub-net and empty subnet
  Refine MUX optimization related with naming and stability.
- Place & Route
  Reduce runtime of placement ~10% for Seal devices

[05/29/2025]  V3.0.6 FT052925
- Main GUI interface
  ** Integrates AI assistant **
- RTL synthesis
  Support exporting synthesis data in plain text format
  Refine register handling related with initial value and name.
  Fix issue related with redundant  if (!clk) branch
  Refine BlockRAM inference, fix corner crash issues.
  Refine DSP inference, fix corner crash issues.
  Refine file line message in case of assertion-failure.
- Place & Route
  Fix ECLKMUX source issue for Sealion 2K devices
  Avoid placing two MULT9 with different signed inputs on one MULT18 site
- HqInsight
  Refine VLA/VIO IP related with adding new signals
  Add [stop] and [force trigger] button in cool bar
  Fix issues related with trigger conditions
- Design interface
  Update simulations models for DSP primitives
  Update SERDES simulation model

[05/25/2025]  V3.0.6 FT052525
- RTL synthesis
  Fix an issue in expression optimization when LSB > 32bits
  Enhance wide input logic of NEQ for Sealion devices
  Enhance DSP handling, fix MULT9->ALU54 wrong conn. issue
  Enhance RAM infer and retargeting
- IP Creator
  Support searching function
  Support sorting function of project IPs
  New IP support : VBO_TX
  DDRC IP: updates to V2.2
  SDRAM_Controller IP : update config, add example
  LSSD IP: Add example

[05/19/2025]  V3.0.6 FT051925
- IP Creator
  DDRC IP: Refine config name description, e.g. change range to density, add unit (Mb, Gb)
- RTL synthesis
  Refine net naming
  Refine message prompt with Async set/reset register with INIT value.

[05/17/2025]  V3.0.6 FT051725
- Bitgen
  Refine DSP MASK01 configuration
- IP Creator
  Support new IP: SDRAM_Controller
- RTL Synthesis
  Fix a crash issue when inferring register with non-standard style.
  Refine RAM/ROM inference and MUX optimization
  Fix an issue related with const function call return width

[05/13/2025]  V3.0.6 FT051325
- Bitgen
  Fix ECLK related issue for Sealion 22K device
- GUI
  Fix `elsif issue in language template
  Refine ifdef macro handling
  Fix a regression issue of source file list related with one include file
- IP Creator
  Linux file/path fix for EBR/LSSD IPs

[05/10/2025]  V3.0.6 FT051025
- downloader
  (Main-program updates to V4.5)
  Fix bit2svf issue for Seal 100K device
  Add SVF data parsing function
  (GUI updates to V2.3)
  Add option to use high-speed downloader
  Add serial port assistant interface
- RTL synthesis
  Support multi `include in one line
  Enhance conditional macro support
  Enhance wide input logic handling for Sealion devices
  Refine keep support
  Fix memory leak issues in macro/DSP handling
- IP Creator
  Support new IPs: Sealion-22k EBR, LSSD, GMII2RGMII
  QSGMII IP update: support new clock structure, refine interface
  EBR IP: update user manual
  DDRC IP: refactor GUI
  PLL IP: Disable OS2/3/5 phase shift for Sealion devices
  Refine example support for RAA file format
- HqInsight
  Switch long/short name display in waveform viewer
  Enhance handling in case of syntax error in RTL file
  Fix issues related with triggering condition, EDIF project
- Place & Route
  Fix issues related with CIBTEST on row 59/60 for Seal 200K device
- Design interface
  Support location/regional constraint on xsCLA.
  Enhance HQ_DATA_SKEW message prompt

[04/27/2025]  V3.0.6 FT042725
- Device support
  Add new device/package: SA5T-70-D0-8UA324CI
- IP Creator
  FIFO_generator : hide internal config parameters
- GUI
  Main GUI : fix issues related with blank project, top level module, device name, etc.
  Fix blank-area display issue of Seal 200K device in ChipViewer.
- RTL synthesis
  Supported HQ_DATA_SKEW directive
  Refine dummy ALOAD DFF handling

[04/23/2025]  V3.0.6 FT042325
- Device support
  Add new device/package: SA5T-200-D0-7H676CI
- Place & Route
  Fix clock routing issue related with PCLK0/2 entry, PLL O5 for Sealion 22K device
- RTL synthesis
  Improve register inference for fully split bus net
  Refine keep support
- HqInsight
  Refine hierarchical signal name display in waveform
  EDIF file change detection support
  Refine continuous trigger and multi-window support

[04/19/2025]  V3.0.6 FT041925
- Bitgen
  Fix bottom right DLLDEL config issue of Seal 100K device
- Place & Route
  Refine PLL reset logic auto placement & route for Seal 126K/100K/366K devices
  Fix a false-alarm delay-exceed-limit issue when there's no timing constraint
  Enhance IO DRC
- RTL synthesis
  Enhance synthesis attribute/directive support
  Initial support of fanout limit
  Add checking of const value against value range.
  Refine file path in prompting message
  Enhance shift-register support
- IP Creator
  MDIO IP: fix uppercase directory name issue and fix doc file search path
  DDRC IP: fix read-locked error issue
- GUI
  Fix issues with console text, project migration, Linux symbolic link path, ..etc.

[04/16/2025]  V3.0.6 FT041625
- Place & Route
* Refine PLL reset logic auto placement & route for Seal 30K/50K/100K devices
- IP Creator
  PLL IPGEN: enhance reset logic handling
- RTL synthesis
  Fix crash issue related with mux-as-latch and numeric literal, e.g.
  	assign q = g ? d + 0 : q
- Design interface
  Add simulation model for xsFIFO16KD
- GUI
  Fix issues with launching directory, linux, history-project,...etc.

[04/13/2025]  V3.0.6 FT041325
- IP Creator
  Update eSPI_Slave verson 1.1
  Support new IP: MDIO IP
- HqInsight
  Fix a stuck-issue when saving project.
- RTL synthesis
  Fix several memory leak issues in analyzer, expr-opt, mux-opt and RAM inference
  Fix wrong bit width issue in initial constant expression of reg
- Place & Route
  FIFO16KB DataCount support for Seal devices
  PLL reset logic special handling for Seal 30K devices
- Design interface
  Update simulation models : xsSERDES_CH, xsSERDES_COM_E1 and xsPLLSA of Seal devices

[04/03/2025]  V3.0.6 FT040325
- RTL synthesis
  Fix a bug in ROM width shrinking.
  Add option to force performing wide-input logic optimization
  Fix an issue related with function return value in generate statement
  Fix a bug related with abnormal port connection message-report in module instantiation
  Enhance RAM infer with asynchronous controlled dout-reg.
- IP Creator
  Update Cordic, LIN, eSPI and xstc_8b10 IPs
- Place & Route
  Enhance analytical placement with tbb support for Seal 100K/366K devices

[03/29/2025]  V3.0.6 FT032925
- IP Creator
  FIFO_Generator : update to v2.0, fix issues related with AF/AE flags.
  Support new IPs: LIN, eSPI_Slave
  Add example scheme for non-HDL IP
- GUI
  Fix issue related with N/A LVDS DIFFDRIVE in pin assignment
  Fix issues related with editor, design hierarchy, logging, ...etc
- Design interface
  Report I/O/T reg status in IO report
- RTL synthesis
  Fix bugs in constant propagation and ROM width-shrinking
  Support comment in macro's formal argument list
  Refine file path name in tri-buffer handling related messages
  Refine RAM interface related with address-register
  Refine string type parameter checking of primitives
  Fix report assertion issue due to mix blocking/non-blocking
    assignment and disable statement
- HqInsight
  Support SVF interface with downloader

[03/23/2025]  V3.0.6 FT032325
- HqInsight
  Fix issue related with loading updated EDIF
  Fix issue related with changing VLA trigger condition.
- IP Creator
  Add a new IP: QSGMII
  Serdes IP: fix preprocess module and signal connection bug
  Tiny_SoC IP : update datasheet version to v1.3
- GUI
  Fix issues related with EDIF project, flow, message, console ...
- RTL synthesis
  Enhance range-select and parallel case checking
  Refine scope handling for un-named generate statement
  Match sensitive list of (* ) and ( *)
  Fix a bug in SRL merging related in non-io-insertion flow.
  Refine register inference related with conditional assignment
- Place & Route
  Fix routing issue related with HSBX of Sealion 22K device.
- IO handling
  Change default mode of some CFGIOs from input to output-Z for some Sealion devices
- Design interface
  Fix parameter value changed from 0x... ->56'h... issue in synplify EDIF.
  Add BUF simulation model for seal devices
- Bitgen
  Add 50k/100k add ddr_vref_trim fuse support

[03/15/2025]  V3.0.6 FT031525
- GUI
  Add tools: xsBertEye, hierarchical resources report
  Fix typo in language template
  Fix false warning related with empty FMAX setting.
- RTL synthesis
  Refine FSM optimization related with duplicated logic.
  Enhance inference of FF with non-standard clock/control signal style
- IP Creator
  SERDES IP, update to V1.2: enhance IP generation, fix issues in GUI

[03/10/2025]  V3.0.6 FT031025
- RTL synthesis
  Fix a regression issue in SRL merge which causes XSBERT IP generation issue.

[03/09/2025]  V3.0.6 FT030925
- Downloader
  (Main program update to V4.3)
  Fix bit file verification failure issue for Sealion 2k device.
  Fix AES shadow and efuse encryption issues for Sealion 22K device.
  Add read status register function.
  (UI update to V2.1)
  Fix FPGA file import exception issue when merging files.
  Update AES shadow setting by writing data to AES bin file at the same time.
  Add firmware versions in the script0/ path.
- GUI
  Fix last-group data missing issue of language template.
  Remember last-opened directory of editor.
- IP Creator
  Support new IPs : XSBERT, Bus_Bridge.
- RTL synthesis
  Refine static shift register merging.
- Place & Route
  Improves QoR for Seal 100K/366K devices.
  +- improves FMAX by ~1.5% with ~%5 runtime reduction

[03/01/2025]  V3.0.6 FT030125
- Downloader
  (Main program/UI) update to V4.3/V2.1
  Fix ID detecting issue before sampling ADC
  Refine SVF_DEBUG idle cycles
  Add bin-to-SSPIbin support
- GUI
  Update language template content
  Refine timing constraint editor
  Refine file-add function by remembering last visited directory
  Integrate xsberteye
- Insight
  Fix issues related with signal trigger, VLA IP, waveform, ...etc.
- IpCreator
  Add a new IP: I2C_Multiplexer v1.0
  SERDES IP : update datasheet on reference link
  Fir_filter IP : fix compile and UI issues
  Tiny_SoC IP : update datasheet on configuration
  DDRC IP fix issue related with read-data buffering
- RTL synthesis
  Refine PDP-RAM handling with two ports using same clock
  Refine RAM DOREG handling related with reset.
  Fix false multi-driven issue caused by function handling.
- Place & Route
  Update for AE/AF/EF/FF port of EBR18 for Seal366K device
  Refine routing for Seal 366K device

[02/23/2025]  V3.0.6 FT022325
- Device modeling
  Update clock-to-q timing values of MULT9/18 and PRADD9/18 for Seal devices

[02/21/2025]  V3.0.6 FT022125
- IP Creator
  PLL IP: refine message related with vco and tolerence rate.
  FIFO_Generator IP:
    Change WRITEMODE from "READBEFOREWRITE" to "NORMAL" in EBR-SFIFO
    Fix SFIFO's EBR stability issue working in high-frequency
  CAN_v20 IP: fix datasheet filename low/upper case issue
- BITGEN
  Update EBR READBEFOREWRITE mode fuse for Seal device
  Update TESTCNT fuse for Sealion 2K device
  Fix pgng on ng1_n fuse for Seal 200K device
- Device support
  Fixed IOTYPE typo : SSTL_15D => SSTL15D
- RTL synthesis
  Refine RK decomposition and LO flow
  Fix issue in MULT9-ALU24 inference related with specific input
    output data width combination
  Refine EBR retargeting for corner cases.
- Place & Route
  Fix issue of placing DCC on DCS location for Seal 366k device

[02/12/2025]  V3.0.6 FT021225
- Device support
  Add new device/package: SL2-22E-FA256
- IP Creator
  Refine IP user manual
- RTL synthesis
  FSM optimization
    Fix a corner issue of state registers with asynchronous set/reset
    Fix huge memory consumption corner issue in FSM optimization
  Support task declaration without argument
  Enhance irregular clock detection in sensitive list
  Fix a corner crash issue in RAM inference.
- Place & Route
  Support IDDRXN_ODDRXN mode for IOLOGIC of Seal 30K device
- Others
  Seal 200K weekly update

[02/04/2025]  V3.0.5 <============================================
- Device Support
** New model support **
  SL2E-2V-8E100CI
  SL2E-2V-8N48CI
  SL2E-2V-32SY
  SL2-25E-8U324A
  SL2S-22E-FA256CI
  SA5Z-30-D0-8U324A
  SA5Z-30-D3-8U256CI
  SA5T-100-D0-8UA324CI
  SA5T-100-D0-7FA676CI
  SA5T-100-D0-8U324CI
  SA5T-100-D0A2-U324
  SA5T-100-D0A2-UA324
  SA5T-100-D0A2-7FA676CI
- Downloader
  Add AES encryption feature
  Add ADC sampling feature
  Add Read FLASH command
  Add output TDO data file command
  Add download comparison file and package information
  Add MSPI flash download write protection removal
  Add offline download mode
  Support multiple interface instances
  Add Read FLASH box to automatically import/open flash files
  Fix issue where error count could display negative values
  Fix bit download alignment issue between CTRL command and bit file
  Fix HQFPGA interface freeze when calling JED files
  Fix XUC error message during bit verification
  Fix DualBoot loading failure in X2/X4 modes
  Fix FPGA+ARM merge exception when encountering read-only files
  Fix DualBoot issue, now supports 4-byte address mode
  Fix key input box unit (changed to char)
- HqInsight (Debugger)
  Add standalone VLA IP (Virtual Logic Analyzer) support
  Add standalone debugging support (Linux development, Windows debugging)
  Support simultaneous VLA+VIO debugging
  Support multi-window trigger function
  Add signal annotation enable feature
  Improve HqWave zoom and Zoom Fit functionality
  Improve message output efficiency and exception handling
  Support access to internal signals in "generate" blocks
  Fix Insight freeze when user sets FMAX to 0
  Fix "Download cable connection error" after continuous triggering
  Fix debugger crash in projects with RTL include directories
  Fix unexpected signal deletion, slow response, and crashes
  Fix language switching, waveform display, and signal addition issues
- IP Creator
  Add New IPs
    CAN_v20
    CAN_FD
    Device_UID
    DSP_Calculator
    FIR_Filter
    Floating_Point
    JESD204
    Serdes
    XSTC_8B10B
    Tiny_Soc
  Renamed IPs: Aurora_8b10b ¡ú 8b10b_Encoder_Decoder, CM33 ¡ú STAR
  DDRC-IP Updates
    Fix tXPR error in DDR3 mode; updated phy_io source code; fixed reset errors
    Improve Seal 100K device support; fixed RT flag errors; fixed 30K/50K address mapping
    Update 50K phyio
    Fix row address bit width error in DDR2-128Mb mode
    Fix Seal 30K BL8 read FIFO space issue
    Fix cmd_clk merging into data_clk clock issue for Seal 30K devices
    Restored extra read FIFO size to match hardware FIFO for Seal 30K BL=8 logic
    Fix conditions for 30K-DDR3-8Gb support
    Add missing 128Mb TRFC capacity branch under DDR2
    Update documentation
  FIFO_GENERATOR IP updates
    Fix rdata reset in FWFT mode
    Fix FIFO internal reset logic; added auto-reset function
  EBR/FIFO IP updates
    Merged ENCODE and DECODE ports into "Code" in FIFO/EBR_PDP IP
    Adjusted FIFO IP minimum address bit width to 3
    Improve 100K device support: added full signal reference; optimized RDC port display
    Fix PDP_wr2048x32_rd8192x8 IP high-byte data[31:16] loss
    Fix PDP_wr512x256_rd512x256 IP output errors
    Fix FIFO IP connection errors in specific configurations
    Fix filename case sensitivity issues
    Fix RDC port mismatch between FIFO IP files and UI configuration
    Fix RDC enable condition in FIFO IP
    Fix undeclared variable issue in pseudo-dual-port RAM configurations
    Fix EBR/FIFO address expansion issues for Seal 30K/50K/100K/366K devices
    Fix single-port EBR IP generation with specific address widths
    Fix incorrect optional address range
    Fix IP generation failure status issues
    Add source files for widths >16 and BE-enable
    Fix redundant error logic in output files for specific configurations
  PLL IP updates
    Improve reset logic for stability
    Add Sealion 2K/4K/22K device support
    Update RESETM reset synchronization logic
    Disabled OPD output for Seal device PLLs
    Adjusted VCO upper limit based on current device
  GDDR71 IP updates
    Fix STOP signal connection error under specific names
    Fix IP naming conflict with keyword 'xsODDRSA71'
    Fix module name conflicts in GDDR7_1 and DDR_GENERIC IP multi-instantiation
    Fix FIFO IP empty signal anomaly causing read data errors
  ADC IP updates
    Add sample_ack handshake signal and unused channel protection
    Add Seal 126K device support
    Fix ADC IP name conflict with primitive names
  VLA IP: Add option to include VIO for simultaneous use
  SED IP: Update Seal 100K device support
  CORDIC IP: Removed non-existent parameters in cordic_rotate mode
  ETH_MAP IP: Improve cross-clock domain handling
  STAR IP: Optimized GPIO page inout control to IOB control
  Improve HDL-type IP output encryption control
  Fix reconfiguration error when output filename prefix is not "xsIP"
  Fix HDL-IP generation failure when working directory contains spaces
  Fix illegal configuration failure causing generated IP files to be deleted
  Fix folder deletion issues during IP generation failures
- Graphical User Interface
  Add file add/delete functionality in design hierarchy
  Add manual hierarchy refresh
  Add project cleanup function
  Add editor thumbnail toggle
  Add file staging function
  Support external editor configuration
  Support Excel batch import for pin constraints (pin2csv, csv2upc)
  Support language template functionality
  Improve PULLMODE handling
  Improve unused communication port detection
  Enhance design hierarchy: faster refresh, improved "generate" block display
  Improve constraint editor, design hierarchy, and file selection UX
  Enhance editor right-click menu and toolbar
  Editor TAB pages: added right-click options (close current/other tabs, open file directory)
  Optimized help menu
  Fix issues when opening legacy projects in new software
  Fix log output failure when modifying source files during runtime
  Fix EDIF project top module name update failure
  Fix device switching failure when initial device not found
  Fix window display issues due to rapid multi-window operations
  Fix relative path tooltip displaying ".."
  Fix file/path-related issues (e.g., Linux file links, spaces in paths)
  Fix ChipViewer crashes and Seal device DSP display issues
  Fix missing sidebar icons
  Fix slow startup of physical constraint editor
  Fix file duplication causing batch add failure
  Fix UPC/SDC comment issues in editor
- RTL Synthesis
  RAM Inference
    Fix large DOREG-RAM partitioning issues
    Improve PDP-RAM read/write same-clock handling
    Enhance RAM inference/remapping error checking and reporting
    Support "_" as separator in RAM initialization files
    Support inference for patterns like `mema[wa] <= memb[rb]`
    Fix normal-mode write port merging issues
    Fix RAM inference crash cases
    Optimized unused port handling
  ROM Inference
    Support constant read addresses
    Support multiple read addresses
    Support concatenated outputs
    Support multiple ports (different depth/width ratios)
    Support ROM style synthesis directive (`syn_romstyle`)
    Fix data width reduction issues in ROM processing
    Improve ROM inference for constant comparisons
  FSM Optimization
    Improve handling of priority encoding (if statements)
    Skipped FSM extraction for complex state transitions
    Improve FSM optimization for if-else inputs
    Fix FSM optimization failures due to non-standard coding styles
  DSP Inference/Mapping
    Improve Sealion 22K multiplier handling
    Fix signedA/B and P connection issues
    Fix multiplier handling errors in devices without DSPs
    Improve pre-adder DSP inference
    Enhance DSP processing for Seal devices with pre-adder and multiplier C registers
  MUX Optimization
    Optimized redundant MUX connected to register R/S
    Optimized MUX with redundant control signals
    Improve MUX generation for range selections
    Fix errors caused by large numbers in range declarations
    Reduce runtime for large-scale MUX optimization
    Fix occasional long runtime in MUX/expression optimization
  Register Optimization
    Improve FF async control conversion
    Fix crash in set/reset optimization (redundant logic)
    Reduce runtime for CE-data optimization
    Fix unconnected D input exception
    Add synthesis directive to block shift register generation for specific signals
    Improve register merging
    Change minimum shift register length from 3 to 2
    Fix shift register inference crashes
    Fix initial value propagation issues
    Fix instability in shift register inference
  Expression & Logic Optimization
    Improve array range selection support (e.g., `part = data[W * idx +: W]`), reduced runtime
    Fix memory overflow in constant propagation under extreme cases
    Fix XOR optimization assertion failures
    Fix sub-wire merging issues in expression optimization
    Improve width-related comparison optimization (e.g., `var[7:0] < 128` is always true)
    Improve optimization for constant-only operations
    Enhance constant propagation across carry chains for Seal devices
    Fix long runtime in specific logic optimization cases
    Fix long expression optimization runtime on Linux
  Parser
    Enhance SDB (CDFG) debugging
    Fix parameter instantiation with empty list `#()`
    Support global parameters/functions/tasks (defined outside modules)
    Strengthened primitive instantiation parameter type checks
    Fix gate instance port width issues
    Improve parameter checks during module instantiation
    Fix assertion errors for `para[idx]` out-of-bounds
    Fix assertion errors for zero-width constants
    Fix crashes due to redundant modules and empty strings
    Fix macro parameter recognition with concatenation operators
    Support unnamed module instantiation
    Fix false redundant bit warnings
    Fix `rtl.macro.define` issues
    Fix `repeat(1'bx)` illegal loop count format
    Support more sensitivity list expressions
    Improve local variable handling in named blocks
    function Handling
      Fix freeze caused by excessive recursive function calls
      Support access to function elements
      Fix assignment exceptions for function name bit-selects
      Add error for functions missing begin/end with multiple statements
      Improve multi-drive handling for functions
      Improve signedness handling
      Improve `repeat` statement handling
      Enhance function support in generate blocks
      Add warning and default return (0) for functions without return statements
    generate Statement Handling
      Fix null pointer errors during parsing
      Improve error messages (previously "fatal error")
      Support nested begin-end blocks in generate statements
      Fix unnamed gate instances in generate blocks
      Add genvar checks for generate loops
      Improve message handling for generate statements and genvars
      Improve global function support
      Support multi-level indexed variables in generate blocks
      Improve defparam message handling in generate blocks
  Message Handling
    Fix incorrect error for constant `2147483648`
    Improve duplicate instantiation error handling
    Fix message file-code inconsistencies
    Fix occasional crash in module instantiation debug info
    Improve parser error/warning accuracy
    Enhance parameter usage warnings
    Add error for duplicate parameter assignments
    Fix functional errors related to `[0:0]` bus signals
    Improve unassigned RHS checks and reporting
    Fix typos in messages
    Improve error reporting for failed instance parameter assignments
    Enhance error tolerance and continuation after parsing failures
    Improve `$readmem` and missing include file error handling
    Improve `$clog` error handling for variables
    Enhance array port checks and reporting
  Miscellaneous
    Improve hierarchical name handling
    Change unconnected output ports from 0 to Z
    Fix garbled messages for Chinese characters in source code
    Update netlist processing to remove redundant multi-drive nets
- Place & Route
  Improve Seal 30K device placement (FMAX ¡ü ~4%, runtime ¡ý ~5%)
  Improve Seal 100K device P&R (FMAX ¡ü ~5%, runtime ¡ý ~20%)
  Enhance congestion control for high-resource designs
  Improve assembly for 2-pin EBR/DSP/DDRC connections
  Improve PRADD9 and DDRC placement for Seal devices
  Improve DSP bypass input register C handling for Seal devices
  Enhance power net routing
  Improve FIFO async reset logic replication
  Support DELAYD packing into IDDRX1/IREG
  Fix EBR18 AF/AE/EF/FF placement issues
  Fix cascaded LUT packing errors
  Fix EBR36 placement freeze in analytical mode
  Fix pin locking routing issues
  Fix DSP clock ID loss during legalization swaps
  Fix Seal device VCC routing issues
  Fix Seal 100K DQS IO placement errors
  Fix Seal 100K SERDES pinmap and DDRC clock placement
  Fix Seal 100K SERDES0/1 REFCLK routing modeling
  Fix Seal 100K JDIVCIB routing issues
  Fix missing IO in SA5T-100-D0-U324 device
  Fix crash caused by LUTs used as GND
- Bitstream Generation
  Optimized Seal 50/100K LVCMOS33 configuration with _OP/_BA attributes
  Fix Seal 30K PLL CLKO5/O6/O7 output configuration
  Fix DSP/pre-adder configuration issues
  Improve MULT18X18C compatibility with bypass ALU C inputs
- Design Interface
  Enhance Seal device PULLMODE checks
  Enhance third-party synthesis tool SERDES/ALU input legalization
  Update Seal device simulation models: DDRCTRL, PCIE, DLLDLY, DELAYDYN, SERDES, EBR, ALU54, MULT18, PLL, ADC, SPRAM32K
  Support hierarchical resource reporting
  Support SED SEDEXCLK feature
  Add safeguards in `seal/sealion_syn_prim.v` to prevent misuse in simulation
  Fix Seal50K internal/external bank name mapping
  Fix Seal50K U324 E9 (CCLK) pin mapping
  Fix Seal4K PLL count error in resource reports
  Fix Seal device MULT9/ALU9 resource count errors
  Fix `phyrule.set` command failure in debug mode for UPC files
  Fix parameter case conversion in third-party Verilog attributes
  Renamed Sealion ADC primitive to `xsADC_SL` to avoid confusion with Seal
  Add error for simultaneous JTAGENB and JTAG pin usage in Sealion 2K devices
- Device Modeling
  Update Seal device timing parameters for EBR, DSP, DQS, DDRCTRL, IOLOGIC, DQSBUF
  Update Seal DQS PAUSE and INPUT_FIFO_RST timing
  Update Seal100K routing delay parameters
  Add LVDS IO_TYPE support for Seal 30K inout ports
- Static Timing Analysis
  Fix `set_false_path` endpoint issues for clock source pins
  Improve handling of combinational loops in clock paths (e.g., PLL feedback)
- Miscellaneous
  Enhance `looptdo` with `-hold_slack`, `-n`, `-min_slack` options
  Update user manual

[07/21/2024]  V3.0.4 <============================================
- Device support
  ** New device/packages support **
    SL2E-4V-8E144CI
    SL2E-4V-8U256CI
    SL2E-2V-8U256CI
    SA5T-100-D0-8FA676C
  Fix issue related with external 1.2V VREF support for Seal device
  Seal 30K IO_TYPE updates
    Support LVDS18
    Disable IO_TYPE under 1.8v, except SSTL15
  Add LVTTL33D support for Seal device
- GUI
  Enhance design project migration with relative path handling
  Fix IO type missing issue in constraint editor for Seal devices
  Integrate routing heatmap viewer
  Add option to disable IO insertion
  Support import RTL with .f list file
  Enhance stability and usability of IDE-style GUI, fix issues related with
     editor, terminal, constrained editor, design hierarchy, flow control,
     special file hierarchy/path, message, list file, ...etc.
- HqInsight (debugger)
* Support multiple LA core
* Improve user interaction performance
  Enhance handling of large files
  By default use internal waveform viewer (HqWave) instead of GtkWave
  Support VIO retargetting flow
  Keep instrumented signal settings when source file change
  Enhance source file change detection
  Enhance save/load of instrumented signal settings
  Support customized trigger position (pre-stored tap count).
  Optimize trigger condition
  Remove 'X' values (wait enough data stored before trigger)
  Refine VLA setting
  Refine UI (font, backcolor)
  Fix various issue related with :
    signal selection, waveform, color setting, radix,
    VLA setting, VIO debugger, editor display, EDIF flow,
    Continuous triggering, combined trigger condition
    top/sub module change/removal,
    synthesis directive, linux platform, ..etc.
- IP Creator
  Refine error checking and prompt upon fail-run of an ipgen executable.
  Add new IPs:
    CM33 IP for Seal 50K device.
    SED IP for Seal device
    FIFO-Generator IP
  CORDIC IP: fix output data range error in complex modular(translate) mode
  DDRC IP update:
    add device checking
    Refine datasheet, diagram;
    Add an option to ouput file for simulation;
    Update for DDR3 mode;
    Fix clock-frequency setting issue in DDR3-SDRAM mode
    Add generation status checking and prompt
  FIFO IP: fix issues related with FULL/EMPTY flag
  PLL IP: Add PHASESEL bus width info in diagram, fix wrong messages
  GDDR71 IP: fix issues related with LVDS18
  EBR IP: fix USE_XY_DA/DB parameter value issue for Seal 100K device
  CM3 IP: Fix typo on AHB master config page
  FFT IP: fix issues related with datawith 18
  Filter IP: Update dataSheet on dual-chan-mode's control&data info
  Fix IP output file rename issue
  Solved issue related with white-space in path name
- Downloader
  updates related with 50K/100K/4K devices
  update DNA information detection, bit-verify for sealion devices;
  refine output message and GUI
  Fix golden address issue for 4K/7K/12K/30K/50K devices
  Fix EBR initialization issue for Seal devices
  Add download support and DNA detection for 100K A2 device
  Fix svf.log-missing issue when hqfpga invoking cable
  Enhance dualboot to make primary address customizable
  Add dualboot primary address entry in GUI
  Fix EBR data issue when doing bit2bin of Seal 100K device
  Add dialog box upon multiple HqFpga instances
  Fixed the problem of deleting bit files by mistake
- Bitgen
  Fix PRADD/MULT C fuse
  Update package pins related with NCSO/ASDO/MCLK for Seal 50K devices
  Fix issue for HSTL12D SSTL12D POD12D IO types
  Support IO PGNG fuse setting for Seal devices.
    Adjust pgng fuse setting of LVCMOS33 io type for Seal 50K/100K devices
  Add an argument -dclk for specifying DCLK frequency
  Fix issues of pnterm fuse on differential IO_TYPE for Seal devices
- RTL synthesis
  Fix an issue related with complex FSM state minimization
  Reduce runtime for redundant FF removal for corner cases.
  Enhance check of ROM infer size
  Improve if statement related with constant value if branch
  Refine RAM infer, map and retargetting:
    Support one-write two-read ports, open DO bits
    Support more complex coding styles using if/case statements
    Improve distributed PDP RAM inference related with byte-enable
    Support ROM address size reduction
    Fix issues related with single port RAM, addr-reg, byte-enable
    Improve SDP RAM inference related with ADDR-REG, ByteEnable
    Enhance error checking and message prompt during retargetting
  Refine DSP infer, map and retargetting:
    Enhance inference/map related with MULT+REG, DSP driving multiple ADD/SUBs
    Enhance DSP48 retargetting by supporting more OPMODEs
    Enhance DSP48 retargetting related with A/BREG mode and C port connection
  Enhance attribute support and parameter checking
  Enhance error checking for case statement with more than one default branches
  Refine error message prompt when instance name is the same as net name
  Fix analyzer issues related with function, task, multi-driven
  Refine DSP retargetting
  Refine big-sized ROM inference.
  Fix crash issue related with undriven input of MUX.
  Refine message prompt related with parameter, localparam and partial-selection
  Add checking for unconnected ports
  Support empty module which is actually a primitive
  Support non-blocking assignment in task
  Enhance constant FF removal
  Enhance large binary-mux partition handling.
  Enhance expression optimization on consecutive LSB 0s
  Refine exception checking and message prompt
  Check parameter value of primitives at early stage
  Refine naming of inferred shift-register logic
  Support one-dimensional reg array write in constant function;
  Improve constant array index handling
  Fix abnormal exit on syntax error of parameter by name
  Fix typos in message file
  Enhance attribute support for concated values.
  Reduce runtime for shift register inference.
  Reduce runtime for binary MUX handling
  Enhance array index net handling
  Enhance debug message upon exception in analyzer
  Fix issue related with array initialization
  Enhance exception handling in MUX optimization
  Improving $readmem statement for empty mem init file
  Fix dead loop issue in expression optimization
  Fix an cross-probing issue related with macro
  Add checking of port-redecalration and illegal definition
  Remove FF dummy control pins
  Fix issues in FSM state extraction and minimization
  Fix long runtime issue when parsing encrypted file
  Fix crash issues related with module without port
  Unified error message in Chinese and English;
  Refine error message related with port declaration
- Place & Route
  Enhance routability and congestion handling of router for Seal devices
    reduce ~10% routing runtime
  Enhance routability for Seal device with ~10% routing runtime reduction
  Fix packing crash issue related with abnormal SERDES connection
  Balance net/slice to avoid congestion for effort-low packing
  Refine SCLK clock/data sink routing policy for Sealion devices
  Enhance IOLOGIC packing support IREG and OREG/TREG with inverted clock phase
  Fix SADC placement issue for Seal 100K device
  Fix placement issue related with ALU24 for Seal devices
  Refine Bank ADC VCCIO checking for Seal 30K device
- device modeling
  Fix timing arc missing issue between RSTm and CLKn for Seal DSP cells
  Update timing information related with DWA of EBR18/36, CLKm->RSTn of DSP
  Update wide-EBR support and timing info.
- Design interface
  Add differential clock IO checking
  Set DMP, ECC_EFB, ISCPU as dont-touch to keep it from being swept.
  More strict checking on string-type parameters of primitives
  Do EBR/DSP retargetting immediately after EDIF reader.
  Enhance type/range validity checking to primitive parameters
  Seal pack update for EDIF lut pairing
  Report un-used resources in utilization report
  Support IS_*_INVERTED parameters for primitives generated by 3rd-party tool
  Refine mixed-clock-data check for inverter/buffer
  update Verilog write NOT to write equation for non-generic logic cells (e.g. MUXCY)
  Simulation model update:
    Add DDRCTRL models for modelsim
    EBR model update for READ_BEFORE_WRITE mode of both ports
    SERDES_CH/SERDES_COM_E1
  Expose new SERDES ports to users: SERDES_CH.QPLLCLK and SERDES_COM_E1.QPLLOUTCLK
  IO report: show package pin name instead of inner pad location for seal devices
  Include IREG/OREG/TREG numbers when reporting IOLOGIC resources.
  Add checking of IREG/OREG/TREG usage and pairing
  Report PRADD utilization
- STA
  Support analysis/report for unconstrained clocks
  Fix a crash bug related with enormous path constraints
  Enhance validity checking for clock group constraint

[02/18/2024]  V3.0.3 <============================================
- IDE-look UI
  Fixed issues in previous release
  Improved usability
- Core components are same as those in HqFpga 2.14.4 Build 021824:
  http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.4/

[11/06/2023]  V3.0.2 <============================================
- IDE-look UI
  Fixed issues in previous release
  Improved usability
- Core components are same as those in HqFpga 2.14.3 Build 110623:
  http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.3/

[06/19/2023]  V3.0.1 <============================================
- IDE-look UI
  Fixed issues in previous release
  Improved usability
- Core components are same as those in HqFpga 2.14.2 Build 061923:
  http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.2/

[02/19/2023]  V3.0.0 <============================================
- IDE-look UI
- Core components are same as those in HqFpga 2.14.1 Build 021923:
  http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.1/