******************************************************************* v* * HqFpga-XIST V3.1.1 Fast Track Build Release Note * ******************************************************************* * UPDATE HISTORY * [04/16/2026] V3.1.1 FT041626 - Downloader (Main program updates to V6.6) Add bit2xfb function for Sealion 15K device Fix download failure in mspi mode for Sealion 15K device Display package info when detecting Sealion 22K device. - IP Creator PLL IP updates related with feedback clock - Device modeling Update TARGEXP0/1, HWRITE, HSEL, HTRANS, HADDR related timing data - Timing Analysis Fix issue related with CLKO5 used as CLKOPD wile CLKOP has no connection Fix issue related with CDIV1 of CLKDIV for Sealion device - RTL synthesis Fix issue related with signed and unsigned operands with typedef Fix issue related with using simulation system task/function inside function RAM infer: refine byte-enable logic handling - Place & Route Fix crash issue due to unhandled exception in placement for Sealion device [04/14/2026] V3.1.1 FT041426 - RTL synthesis Fix casex comparator crash from X-input count mismatch Optimize bit-width for const-compared vars/accumulators - Place and route Fix PCLK clock distribution issues for Sealion 15K devices Update IOTYPE support for Seal 50K/100K/126K/420K devices: remove LVDS18 from HR Bank [04/12/2026] V3.1.1 FT041226 ## IP Creator - DDRC IP updates to V4.0 - Main UI Refine setting page - RTL synthesis Fix FSM issue related with state register -> output with reversed bit order Support function port without direction - Place & Route Fix SCLK routing issue for Sealion 22K device Refine routing - Design interface support UTF-8 encoding in UPC file [04/10/2026] V3.1.1 FT041026 - Design interface Update simulation models: xsDMP/xsIDDRSAX4 - RTL synthesis Add support for typedef struct under SystemVerilog mode Add basic package support under SystemVerilog mode (typedef/function/parameter and import pkg::*) Disable variable definitions in unnamed blocks under SystemVerilog mode Fix analysis failure exception and memory leak for named port connections in function/task - Place and route Report post-placement WNS even if placer is not timing driven [04/06/2026] V3.1.1 FT040626 - Device support New package support : SL2E-2V-8E144CI - Main UI Fix issues related with wrong timing constraint, multi-top-module, project clean, ..etc. Refine setting page from dialog box to tabular page Support state of placement is done while routing is not - IP Creator ERB IP updates to V3.7 New IP support : TEN_GIG_ETCH_PHY IP, SDI IP, LTPI IP UI update : fix config value issue for PLL IP cascaded frequency division - Place & Route Enhance area optimization in packing for Seal devices. - RTL synthesis support return statement as the last one in function call [04/03/2026] V3.1.1 FT040326 - RTL synthesis Fix a crash issue caused by a floating port connection Support comments in RAM initialization files Fix memory leak issue in FSM optimization Add enum cast and bit-stream cast support under SystemVerilog mode [04/01/2026] V3.1.1 FT040126 - RTL synthesis Add support for OUTREG during byte RAM merge Add struct assignment and struct array support under SystemVerilog mode - Device modeling Fix timing modeling issue for SAIOLOGIC of Sealion 22K device Fix timing modeling issue for IOLOGIC of Seal device - HqInsight Fix trigger option persistence issue Fix signal marking issue when opening waveform [03/29/2026] V3.1.1 FT032926 - Place & Route Enhance packing on high register usage ratio (>75%) of Sealion device Enhance IO placement error report - Bitgen Support PIO PADDIN - HqInsight Fix abnormal program exit related with cable connection failure Enhance stability for triggering conditions - Main UI Support GUI-text bi-directional editing for physical constraint Fix STA path anlysis no-result issue due to "[]" in signal name Refine icon of AI assistant No need to run RTL synthesis anymore before adding physical/timing constraint - IP Creator DSP_Calculator IP updates to v3.1 Tiny_SoC IP updates to V1.4 MIPI_CSI2_RX IP updates to V1.3 CM3 and STAR IP updates to V5.1 Fix issue related with importing IP without vfile Fix issue of parsing ">= <=" - RTL synthesis Fix issues related with logical shift and FSM extraction - Device modeling Fix timing arc missing issue in SAIOLOGIC and CIBBOUT of Sealion 22K device [03/25/2026] V3.1.1 FT032526 - Downloader (Main program updated to V6.5) Fix false-alarm of CRC when verifying flash for Seal 126K devices - Bitgen Fix ERB INIT data CRC error for Seal 126K devices - RTL synthesis Fix issues related to missing generate instances caused by undefined modules Add support for SPRAM1KX32 inference on Sealion 22K devices [03/21/2026] V3.1.1 FT032126 - RTL synthesis Fix issues related with same net slice operation coupled with resource sharing FSM optimization: fix runtime issue for corner cases. - IP Creator New IP support: DISPLAYPORT_RX Update CM3 and STAR IP to V5.0 Update UI related with icon, validity checking, report, title, ...etc. - Device modeling Finalize clock region de-skew parameters for Seal 200K device - Main UI Refine startup process Refine auto-updater [03/19/2026] V3.1.1 FT031926 - RTL synthesis Fix incorrect default values for enum constants defined with ranges (name[N] or name[N:M]) Refine FSM extraction to optimize when input count exceeds 10 - Place and route Output the congestion estimation message to hqfpga.log [03/15/2026] V3.1.1 FT031526 - RTL synthesis Refine hier-id support - Main UI Fix issues related with auto-update, constraint editor and EDIF IP handling - Place and route Refine clock skew handling for Seal 200k device [03/11/2026] V3.1.1 FT031126 - Design interface Update simulation models: xsTDDRSA/xsTDDRSAX2/xsTDDRSAX4 - RTL synthesis Fix meaningless net names caused by port mismatch handling and longint support Fix an issue with misjudgment under multi-driver conditions Fix cross-platform netlist naming inconsistency Fix an issue with floating D inputs on output registers when retargeting DSP48E1 [03/08/2026] V3.1.1 FT030826 - IP Creator MIPI_DSI_TX IP updates to V1.1 MIPI_CSI_RX IP updates to V1.2 SerDes IP updates to V3.2 QSGMII IP updates to V1.2 XSTC_8B10 IP updates to V2.0 New IP support : PSRAM_Controller - RTL synthesis Fix runtime issue of prime factorization after longint (64-bit) update Fix FF sweep issue related with constant CE Enhance logic optimization of unreachable case branch [03/05/2026] V3.1.1 FT030526 - Downloader (Main program updated to V6.3) Fix issue: when flash start address has offset, data before offset is wrongly erased - Device modeling Update timing data for PCIE_E1 [03/04/2026] V3.1.1 FT030426 - Downloader (Main program updated to V6.2) Fix an issue with flash offset erase failure. - RTL synthesis Fix an issue related to mismatched port width/signed in module instantiation Fix a crash issue related to grounded write clock in SDP mode RAMB18E1 Support longint under verilog mode Release limitation to assignment of reg/logic/int/longint under verilog mode Refine SRL merging for redundant enable DFFs. [03/01/2026] V3.1.1 FT030126 - IP Creator LFSR_IP IP updates to V1.1 (Sealion) CM3/STAR IP updates to V4.5 (SA5Z-30/SA5Z-50) User interface updates related with file browser, path and console - RTL synthesis MUX optimization update for sparse branches FSM optimization update for large output bits - Device modeling Update timing data for PCIE_E1 - Main UI Fix issues related with new project refine lock-screen and app-close behavior - Place & Route Fix routing issue for Shark device [02/20/2026] V3.1.0 <============================================ - New Device and Package Support SL2E-2V-8M132CI SL2E-2V-8NA48CI SL2E-2V-8N48CI SL2-22E-FA256 SL2-22E-FA256 SA5Z-33-D1-8U213CI SA5Z-33-D2-8U256CI SA5T-70-D0-8UA324CI SA5T-200-D0-7H676CI - RTL Synthesis Improved RAM/ROM Inference: Supports byte enable, pseudo dual-port, output register, OREG absorption control, sparse case, READMODE control, etc. Optimized shift register recognition and merging, supports dynamic/static tapping, cross-module recognition, control signal extraction. Improved DSP/ALU/MULT Inference: Fixed MULT9/ALU54 connection anomalies, opmode variable handling, floating low bits of multiplication, etc. Enhanced optimization capabilities for FSM, MUX, carry chains, wide-input logic, constant propagation, expression simplification, etc. Supports division by any non-zero integer for / and % operations, undefined values in macros, ROM initialization within initial blocks, etc. Fixed numerous crash issues: e.g., IBUF directly connected to output, nested generate, array out-of-bounds, multiple drivers, bit-width mismatch, mixed assignments, etc. Improved Verilog parser's fault tolerance and compatibility for include, macros, generate, function, and other constructs. Supports synthesis guidance directives such as HQ_DATA_SKEW and HQ_MAX_FANOUT. Supports partial SystemVerilog syntax: logic, enum, array use before declaration, for loop ++/--, macros with default values, nested macros with empty values, etc. - Place & Route (P&R) Improved placement optimization for the Seal series products, achieving ~3% timing performance improvement. Improved routing optimization for the Seal series products, achieving ~5% timing performance improvement, ~30% reduction in runtime, and ~25% reduction in memory usage. Improved area-priority mode Packing (-effort low), reducing resource utilization by ~1% and runtime by ~30%. Supports xsCDELAY, CLKBRANCH driving IMUX, dual-stitch EBR inverter handling, legality checks, etc. Fixed issues such as multi-round routing contention, corner routing failures, and loss of region constraints. Corrected issues for Seal 200K/30K/50K and other devices regarding clock placement, PCLK/RCLK allocation, BPLL/HBUF connections, SERDES path modeling, etc. Corrected resource modeling errors for EBR/DSP/PIO/CIB/DDRCTRL, etc., to prevent misjudgment or connection failures. - IP Creator [New IPs] Hyper_DSP MIPI CSI2 MIPI RX QSGMII LLCR UART FIR_LOOP Bus_Bridge I2C_Multiplexer HFC GMII2RGMII MDIO Device_UID [IP Functionality Improvements] PLL IP: Supports dynamic phase shift, cascaded outputs, LOCK synchronization, disabling invalid phase shift options; updated frequency upper limit to 1GHz. EBR/FIFO IP: Supports AUTO resource type, prog_full/prog_empty, read-ahead mode, OREG control, byte enable corrections. DDRC IP: Supports SA5T-200/366/420K; improved Read Leveling, DQ Delay, AXI interface, example designs. SerDes IP: Updated to v3.x; corrected TX/RX configuration rules, userclk frequency display. [IP Framework and GUI Improvements] Supports IP search, sorting, adding to projects, automatic copying of examples, synchronization of XML conditional dependencies, dynamic updating of parameter ranges. Fixed issues such as missing device information in modify mode, Chinese paths, paths with spaces, IP names starting with numbers, etc. - HqInsight / On-Chip Real-Time Debugging Supports VLA/VIO multi-window triggering, continuous triggering, X-value mask triggering, dual-edge triggering, virtual vector creation. Fixed issues such as EDIF flow crashes, abnormal signal capture, combinatorial trigger failure, waveform loading errors, etc. Supports capturing array/logic signals, signal renaming, saving debug settings with the project. Improved memory usage (reduced by ~50%), enhanced stability. - GUI and Main Interface Integrated "Crystal Assistant" (AI assistant), document tracking, eye diagram tool, heat map, hierarchical resource reporting. Improved design hierarchy refresh, file path handling, constraint editor, language templates, EDIF project support. Fixed issues such as empty project hangs, crashes due to signals containing backslashes, tab closing, log search, etc. Supports switching between long/short signal names, multi-top display, single-instance project opening control. - Bitstream Generation (Bitgen) Supports security features such as fuse_protect, SED_CRC, efuse_aes key settings, disabling configuration readback, etc. Corrected configuration issues for Seal/Sealion devices regarding ECLK, OSC, TESTCNT, DLLDEL, HPIO, DNA, BANKCTRL, etc. Improved driving strategy for unused global clock lines, disabled BL pull-up to reduce static power consumption. Supports special handling for Seal 50K/100K DDR_VREF_TRIM, Sealion 2K not supporting compressed .bin, etc. - Downloader Main program updated to V6.0, supports downloading for 2K/70K/100K/200K/420K series, AES encryption, .bin/.svf/.jed conversion. Supports SSPI/IIC/MSPI modes for embedded Flash, JTAG cascade, ADC sampling, status register reading. Corrected issues such as Linux path display, log flickering, file merging, package detection, etc. - Data Interface Updated simulation models for primitives such as xsBRAM, xsFIFO, xsPLLSA, xsSERDES, xsPCIE, xsDDRCTRL, xsDMP, xsDNA_PORT. Supports regional resource reporting (nl.report -region), capture clock delay printout, looptdo no-compression option. Corrected GTN timing parameters (clock-to-q, setup/hold, delay, etc.), improving STA accuracy. Optimized intermediate data serialization, text export, platform newline compatibility. - Static Timing Analysis (STA) Supports automatic inference for PLL cascaded clocks, automatically setting same-source CLKDIV as synchronous. Corrected false positives for MPW (Minimum Pulse Width) and analysis anomalies for latches in combinational loops. Improved cross-clock domain reporting, multi-clock handling, and accuracy of FMAX report information. - Others Corrected typos in the user manual, company names, and inconsistencies in IP descriptions. [02/04/2025] V3.0.5 <============================================ - Device Support ** New model support ** SL2E-2V-8E100CI SL2E-2V-8N48CI SL2E-2V-32SY SL2-25E-8U324A SL2S-22E-FA256CI SA5Z-30-D0-8U324A SA5Z-30-D3-8U256CI SA5T-100-D0-8UA324CI SA5T-100-D0-7FA676CI SA5T-100-D0-8U324CI SA5T-100-D0A2-U324 SA5T-100-D0A2-UA324 SA5T-100-D0A2-7FA676CI - Downloader Add AES encryption feature Add ADC sampling feature Add Read FLASH command Add output TDO data file command Add download comparison file and package information Add MSPI flash download write protection removal Add offline download mode Support multiple interface instances Add Read FLASH box to automatically import/open flash files Fix issue where error count could display negative values Fix bit download alignment issue between CTRL command and bit file Fix HQFPGA interface freeze when calling JED files Fix XUC error message during bit verification Fix DualBoot loading failure in X2/X4 modes Fix FPGA+ARM merge exception when encountering read-only files Fix DualBoot issue, now supports 4-byte address mode Fix key input box unit (changed to char) - HqInsight (Debugger) Add standalone VLA IP (Virtual Logic Analyzer) support Add standalone debugging support (Linux development, Windows debugging) Support simultaneous VLA+VIO debugging Support multi-window trigger function Add signal annotation enable feature Improve HqWave zoom and Zoom Fit functionality Improve message output efficiency and exception handling Support access to internal signals in "generate" blocks Fix Insight freeze when user sets FMAX to 0 Fix "Download cable connection error" after continuous triggering Fix debugger crash in projects with RTL include directories Fix unexpected signal deletion, slow response, and crashes Fix language switching, waveform display, and signal addition issues - IP Creator Add New IPs CAN_v20 CAN_FD Device_UID DSP_Calculator FIR_Filter Floating_Point JESD204 Serdes XSTC_8B10B Tiny_Soc Renamed IPs: Aurora_8b10b → 8b10b_Encoder_Decoder, CM33 → STAR DDRC-IP Updates Fix tXPR error in DDR3 mode; updated phy_io source code; fixed reset errors Improve Seal 100K device support; fixed RT flag errors; fixed 30K/50K address mapping Update 50K phyio Fix row address bit width error in DDR2-128Mb mode Fix Seal 30K BL8 read FIFO space issue Fix cmd_clk merging into data_clk clock issue for Seal 30K devices Restored extra read FIFO size to match hardware FIFO for Seal 30K BL=8 logic Fix conditions for 30K-DDR3-8Gb support Add missing 128Mb TRFC capacity branch under DDR2 Update documentation FIFO_GENERATOR IP updates Fix rdata reset in FWFT mode Fix FIFO internal reset logic; added auto-reset function EBR/FIFO IP updates Merged ENCODE and DECODE ports into "Code" in FIFO/EBR_PDP IP Adjusted FIFO IP minimum address bit width to 3 Improve 100K device support: added full signal reference; optimized RDC port display Fix PDP_wr2048x32_rd8192x8 IP high-byte data[31:16] loss Fix PDP_wr512x256_rd512x256 IP output errors Fix FIFO IP connection errors in specific configurations Fix filename case sensitivity issues Fix RDC port mismatch between FIFO IP files and UI configuration Fix RDC enable condition in FIFO IP Fix undeclared variable issue in pseudo-dual-port RAM configurations Fix EBR/FIFO address expansion issues for Seal 30K/50K/100K/366K devices Fix single-port EBR IP generation with specific address widths Fix incorrect optional address range Fix IP generation failure status issues Add source files for widths >16 and BE-enable Fix redundant error logic in output files for specific configurations PLL IP updates Improve reset logic for stability Add Sealion 2K/4K/22K device support Update RESETM reset synchronization logic Disabled OPD output for Seal device PLLs Adjusted VCO upper limit based on current device GDDR71 IP updates Fix STOP signal connection error under specific names Fix IP naming conflict with keyword 'xsODDRSA71' Fix module name conflicts in GDDR7_1 and DDR_GENERIC IP multi-instantiation Fix FIFO IP empty signal anomaly causing read data errors ADC IP updates Add sample_ack handshake signal and unused channel protection Add Seal 126K device support Fix ADC IP name conflict with primitive names VLA IP: Add option to include VIO for simultaneous use SED IP: Update Seal 100K device support CORDIC IP: Removed non-existent parameters in cordic_rotate mode ETH_MAP IP: Improve cross-clock domain handling STAR IP: Optimized GPIO page inout control to IOB control Improve HDL-type IP output encryption control Fix reconfiguration error when output filename prefix is not "xsIP" Fix HDL-IP generation failure when working directory contains spaces Fix illegal configuration failure causing generated IP files to be deleted Fix folder deletion issues during IP generation failures - Graphical User Interface Add file add/delete functionality in design hierarchy Add manual hierarchy refresh Add project cleanup function Add editor thumbnail toggle Add file staging function Support external editor configuration Support Excel batch import for pin constraints (pin2csv, csv2upc) Support language template functionality Improve PULLMODE handling Improve unused communication port detection Enhance design hierarchy: faster refresh, improved "generate" block display Improve constraint editor, design hierarchy, and file selection UX Enhance editor right-click menu and toolbar Editor TAB pages: added right-click options (close current/other tabs, open file directory) Optimized help menu Fix issues when opening legacy projects in new software Fix log output failure when modifying source files during runtime Fix EDIF project top module name update failure Fix device switching failure when initial device not found Fix window display issues due to rapid multi-window operations Fix relative path tooltip displaying ".." Fix file/path-related issues (e.g., Linux file links, spaces in paths) Fix ChipViewer crashes and Seal device DSP display issues Fix missing sidebar icons Fix slow startup of physical constraint editor Fix file duplication causing batch add failure Fix UPC/SDC comment issues in editor - RTL Synthesis RAM Inference Fix large DOREG-RAM partitioning issues Improve PDP-RAM read/write same-clock handling Enhance RAM inference/remapping error checking and reporting Support "_" as separator in RAM initialization files Support inference for patterns like `mema[wa] <= memb[rb]` Fix normal-mode write port merging issues Fix RAM inference crash cases Optimized unused port handling ROM Inference Support constant read addresses Support multiple read addresses Support concatenated outputs Support multiple ports (different depth/width ratios) Support ROM style synthesis directive (`syn_romstyle`) Fix data width reduction issues in ROM processing Improve ROM inference for constant comparisons FSM Optimization Improve handling of priority encoding (if statements) Skipped FSM extraction for complex state transitions Improve FSM optimization for if-else inputs Fix FSM optimization failures due to non-standard coding styles DSP Inference/Mapping Improve Sealion 22K multiplier handling Fix signedA/B and P connection issues Fix multiplier handling errors in devices without DSPs Improve pre-adder DSP inference Enhance DSP processing for Seal devices with pre-adder and multiplier C registers MUX Optimization Optimized redundant MUX connected to register R/S Optimized MUX with redundant control signals Improve MUX generation for range selections Fix errors caused by large numbers in range declarations Reduce runtime for large-scale MUX optimization Fix occasional long runtime in MUX/expression optimization Register Optimization Improve FF async control conversion Fix crash in set/reset optimization (redundant logic) Reduce runtime for CE-data optimization Fix unconnected D input exception Add synthesis directive to block shift register generation for specific signals Improve register merging Change minimum shift register length from 3 to 2 Fix shift register inference crashes Fix initial value propagation issues Fix instability in shift register inference Expression & Logic Optimization Improve array range selection support (e.g., `part = data[W * idx +: W]`), reduced runtime Fix memory overflow in constant propagation under extreme cases Fix XOR optimization assertion failures Fix sub-wire merging issues in expression optimization Improve width-related comparison optimization (e.g., `var[7:0] < 128` is always true) Improve optimization for constant-only operations Enhance constant propagation across carry chains for Seal devices Fix long runtime in specific logic optimization cases Fix long expression optimization runtime on Linux Parser Enhance SDB (CDFG) debugging Fix parameter instantiation with empty list `#()` Support global parameters/functions/tasks (defined outside modules) Strengthened primitive instantiation parameter type checks Fix gate instance port width issues Improve parameter checks during module instantiation Fix assertion errors for `para[idx]` out-of-bounds Fix assertion errors for zero-width constants Fix crashes due to redundant modules and empty strings Fix macro parameter recognition with concatenation operators Support unnamed module instantiation Fix false redundant bit warnings Fix `rtl.macro.define` issues Fix `repeat(1'bx)` illegal loop count format Support more sensitivity list expressions Improve local variable handling in named blocks function Handling Fix freeze caused by excessive recursive function calls Support access to function elements Fix assignment exceptions for function name bit-selects Add error for functions missing begin/end with multiple statements Improve multi-drive handling for functions Improve signedness handling Improve `repeat` statement handling Enhance function support in generate blocks Add warning and default return (0) for functions without return statements generate Statement Handling Fix null pointer errors during parsing Improve error messages (previously "fatal error") Support nested begin-end blocks in generate statements Fix unnamed gate instances in generate blocks Add genvar checks for generate loops Improve message handling for generate statements and genvars Improve global function support Support multi-level indexed variables in generate blocks Improve defparam message handling in generate blocks Message Handling Fix incorrect error for constant `2147483648` Improve duplicate instantiation error handling Fix message file-code inconsistencies Fix occasional crash in module instantiation debug info Improve parser error/warning accuracy Enhance parameter usage warnings Add error for duplicate parameter assignments Fix functional errors related to `[0:0]` bus signals Improve unassigned RHS checks and reporting Fix typos in messages Improve error reporting for failed instance parameter assignments Enhance error tolerance and continuation after parsing failures Improve `$readmem` and missing include file error handling Improve `$clog` error handling for variables Enhance array port checks and reporting Miscellaneous Improve hierarchical name handling Change unconnected output ports from 0 to Z Fix garbled messages for Chinese characters in source code Update netlist processing to remove redundant multi-drive nets - Place & Route Improve Seal 30K device placement (FMAX ↑ ~4%, runtime ↓ ~5%) Improve Seal 100K device P&R (FMAX ↑ ~5%, runtime ↓ ~20%) Enhance congestion control for high-resource designs Improve assembly for 2-pin EBR/DSP/DDRC connections Improve PRADD9 and DDRC placement for Seal devices Improve DSP bypass input register C handling for Seal devices Enhance power net routing Improve FIFO async reset logic replication Support DELAYD packing into IDDRX1/IREG Fix EBR18 AF/AE/EF/FF placement issues Fix cascaded LUT packing errors Fix EBR36 placement freeze in analytical mode Fix pin locking routing issues Fix DSP clock ID loss during legalization swaps Fix Seal device VCC routing issues Fix Seal 100K DQS IO placement errors Fix Seal 100K SERDES pinmap and DDRC clock placement Fix Seal 100K SERDES0/1 REFCLK routing modeling Fix Seal 100K JDIVCIB routing issues Fix missing IO in SA5T-100-D0-U324 device Fix crash caused by LUTs used as GND - Bitstream Generation Optimized Seal 50/100K LVCMOS33 configuration with _OP/_BA attributes Fix Seal 30K PLL CLKO5/O6/O7 output configuration Fix DSP/pre-adder configuration issues Improve MULT18X18C compatibility with bypass ALU C inputs - Design Interface Enhance Seal device PULLMODE checks Enhance third-party synthesis tool SERDES/ALU input legalization Update Seal device simulation models: DDRCTRL, PCIE, DLLDLY, DELAYDYN, SERDES, EBR, ALU54, MULT18, PLL, ADC, SPRAM32K Support hierarchical resource reporting Support SED SEDEXCLK feature Add safeguards in `seal/sealion_syn_prim.v` to prevent misuse in simulation Fix Seal50K internal/external bank name mapping Fix Seal50K U324 E9 (CCLK) pin mapping Fix Seal4K PLL count error in resource reports Fix Seal device MULT9/ALU9 resource count errors Fix `phyrule.set` command failure in debug mode for UPC files Fix parameter case conversion in third-party Verilog attributes Renamed Sealion ADC primitive to `xsADC_SL` to avoid confusion with Seal Add error for simultaneous JTAGENB and JTAG pin usage in Sealion 2K devices - Device Modeling Update Seal device timing parameters for EBR, DSP, DQS, DDRCTRL, IOLOGIC, DQSBUF Update Seal DQS PAUSE and INPUT_FIFO_RST timing Update Seal100K routing delay parameters Add LVDS IO_TYPE support for Seal 30K inout ports - Static Timing Analysis Fix `set_false_path` endpoint issues for clock source pins Improve handling of combinational loops in clock paths (e.g., PLL feedback) - Miscellaneous Enhance `looptdo` with `-hold_slack`, `-n`, `-min_slack` options Update user manual [07/21/2024] V3.0.4 <============================================ - Device support ** New device/packages support ** SL2E-4V-8E144CI SL2E-4V-8U256CI SL2E-2V-8U256CI SA5T-100-D0-8FA676C Fix issue related with external 1.2V VREF support for Seal device Seal 30K IO_TYPE updates Support LVDS18 Disable IO_TYPE under 1.8v, except SSTL15 Add LVTTL33D support for Seal device - GUI Enhance design project migration with relative path handling Fix IO type missing issue in constraint editor for Seal devices Integrate routing heatmap viewer Add option to disable IO insertion Support import RTL with .f list file Enhance stability and usability of IDE-style GUI, fix issues related with editor, terminal, constrained editor, design hierarchy, flow control, special file hierarchy/path, message, list file, ...etc. - HqInsight (debugger) * Support multiple LA core * Improve user interaction performance Enhance handling of large files By default use internal waveform viewer (HqWave) instead of GtkWave Support VIO retargetting flow Keep instrumented signal settings when source file change Enhance source file change detection Enhance save/load of instrumented signal settings Support customized trigger position (pre-stored tap count). Optimize trigger condition Remove 'X' values (wait enough data stored before trigger) Refine VLA setting Refine UI (font, backcolor) Fix various issue related with : signal selection, waveform, color setting, radix, VLA setting, VIO debugger, editor display, EDIF flow, Continuous triggering, combined trigger condition top/sub module change/removal, synthesis directive, linux platform, ..etc. - IP Creator Refine error checking and prompt upon fail-run of an ipgen executable. Add new IPs: CM33 IP for Seal 50K device. SED IP for Seal device FIFO-Generator IP CORDIC IP: fix output data range error in complex modular(translate) mode DDRC IP update: add device checking Refine datasheet, diagram; Add an option to ouput file for simulation; Update for DDR3 mode; Fix clock-frequency setting issue in DDR3-SDRAM mode Add generation status checking and prompt FIFO IP: fix issues related with FULL/EMPTY flag PLL IP: Add PHASESEL bus width info in diagram, fix wrong messages GDDR71 IP: fix issues related with LVDS18 EBR IP: fix USE_XY_DA/DB parameter value issue for Seal 100K device CM3 IP: Fix typo on AHB master config page FFT IP: fix issues related with datawith 18 Filter IP: Update dataSheet on dual-chan-mode's control&data info Fix IP output file rename issue Solved issue related with white-space in path name - Downloader updates related with 50K/100K/4K devices update DNA information detection, bit-verify for sealion devices; refine output message and GUI Fix golden address issue for 4K/7K/12K/30K/50K devices Fix EBR initialization issue for Seal devices Add download support and DNA detection for 100K A2 device Fix svf.log-missing issue when hqfpga invoking cable Enhance dualboot to make primary address customizable Add dualboot primary address entry in GUI Fix EBR data issue when doing bit2bin of Seal 100K device Add dialog box upon multiple HqFpga instances Fixed the problem of deleting bit files by mistake - Bitgen Fix PRADD/MULT C fuse Update package pins related with NCSO/ASDO/MCLK for Seal 50K devices Fix issue for HSTL12D SSTL12D POD12D IO types Support IO PGNG fuse setting for Seal devices. Adjust pgng fuse setting of LVCMOS33 io type for Seal 50K/100K devices Add an argument -dclk for specifying DCLK frequency Fix issues of pnterm fuse on differential IO_TYPE for Seal devices - RTL synthesis Fix an issue related with complex FSM state minimization Reduce runtime for redundant FF removal for corner cases. Enhance check of ROM infer size Improve if statement related with constant value if branch Refine RAM infer, map and retargetting: Support one-write two-read ports, open DO bits Support more complex coding styles using if/case statements Improve distributed PDP RAM inference related with byte-enable Support ROM address size reduction Fix issues related with single port RAM, addr-reg, byte-enable Improve SDP RAM inference related with ADDR-REG, ByteEnable Enhance error checking and message prompt during retargetting Refine DSP infer, map and retargetting: Enhance inference/map related with MULT+REG, DSP driving multiple ADD/SUBs Enhance DSP48 retargetting by supporting more OPMODEs Enhance DSP48 retargetting related with A/BREG mode and C port connection Enhance attribute support and parameter checking Enhance error checking for case statement with more than one default branches Refine error message prompt when instance name is the same as net name Fix analyzer issues related with function, task, multi-driven Refine DSP retargetting Refine big-sized ROM inference. Fix crash issue related with undriven input of MUX. Refine message prompt related with parameter, localparam and partial-selection Add checking for unconnected ports Support empty module which is actually a primitive Support non-blocking assignment in task Enhance constant FF removal Enhance large binary-mux partition handling. Enhance expression optimization on consecutive LSB 0s Refine exception checking and message prompt Check parameter value of primitives at early stage Refine naming of inferred shift-register logic Support one-dimensional reg array write in constant function; Improve constant array index handling Fix abnormal exit on syntax error of parameter by name Fix typos in message file Enhance attribute support for concated values. Reduce runtime for shift register inference. Reduce runtime for binary MUX handling Enhance array index net handling Enhance debug message upon exception in analyzer Fix issue related with array initialization Enhance exception handling in MUX optimization Improving $readmem statement for empty mem init file Fix dead loop issue in expression optimization Fix an cross-probing issue related with macro Add checking of port-redecalration and illegal definition Remove FF dummy control pins Fix issues in FSM state extraction and minimization Fix long runtime issue when parsing encrypted file Fix crash issues related with module without port Unified error message in Chinese and English; Refine error message related with port declaration - Place & Route Enhance routability and congestion handling of router for Seal devices reduce ~10% routing runtime Enhance routability for Seal device with ~10% routing runtime reduction Fix packing crash issue related with abnormal SERDES connection Balance net/slice to avoid congestion for effort-low packing Refine SCLK clock/data sink routing policy for Sealion devices Enhance IOLOGIC packing support IREG and OREG/TREG with inverted clock phase Fix SADC placement issue for Seal 100K device Fix placement issue related with ALU24 for Seal devices Refine Bank ADC VCCIO checking for Seal 30K device - device modeling Fix timing arc missing issue between RSTm and CLKn for Seal DSP cells Update timing information related with DWA of EBR18/36, CLKm->RSTn of DSP Update wide-EBR support and timing info. - Design interface Add differential clock IO checking Set DMP, ECC_EFB, ISCPU as dont-touch to keep it from being swept. More strict checking on string-type parameters of primitives Do EBR/DSP retargetting immediately after EDIF reader. Enhance type/range validity checking to primitive parameters Seal pack update for EDIF lut pairing Report un-used resources in utilization report Support IS_*_INVERTED parameters for primitives generated by 3rd-party tool Refine mixed-clock-data check for inverter/buffer update Verilog write NOT to write equation for non-generic logic cells (e.g. MUXCY) Simulation model update: Add DDRCTRL models for modelsim EBR model update for READ_BEFORE_WRITE mode of both ports SERDES_CH/SERDES_COM_E1 Expose new SERDES ports to users: SERDES_CH.QPLLCLK and SERDES_COM_E1.QPLLOUTCLK IO report: show package pin name instead of inner pad location for seal devices Include IREG/OREG/TREG numbers when reporting IOLOGIC resources. Add checking of IREG/OREG/TREG usage and pairing Report PRADD utilization - STA Support analysis/report for unconstrained clocks Fix a crash bug related with enormous path constraints Enhance validity checking for clock group constraint [02/18/2024] V3.0.3 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.4 Build 021824: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.4/ [11/06/2023] V3.0.2 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.3 Build 110623: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.3/ [06/19/2023] V3.0.1 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.2 Build 061923: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.2/ [02/19/2023] V3.0.0 <============================================ - IDE-look UI - Core components are same as those in HqFpga 2.14.1 Build 021923: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.1/