******************************************************************* * * HqFpga-XIST V3.0.5 Fast Track Release Note * ******************************************************************* * UPDATE HISTORY * [12/27/2024] V3.0.5 FT122724 - Place & Route Fix a bug related with carry chain packing in area optimzation [12/23/2024] V3.0.5 FT122324 - GUI ** Fix regression issue of importing UPC/SDC ** [12/22/2024] V2.14.6 DBFT122224 - Place & Route Ehance routing congestion handling. - Packing Re-enable pass-thru LUT for better area/performance trade-off [12/20/2024] V2.14.6 DBFT122024 - Packing Put more LE in to carry tail Disable pass-thru LUT for single register Prefer LE with same control set - RTL synthesis Move constant LUT input optimization from packer to frontend Adder refine for LUT6 Refine FF merging Refine shift register info to support 2 FFs->SRL (previously 3 at minimum) [12/04/2024] V2.14.6 TST120424 - Place & Route Disable pth-latch-1 and gpk-lut62-pthru - Device modeling Update DSP, IOLOGIC and DQS timing arc [11/19/2024] V2.14.6 TST111924 - Device modeling Fixed a routing wire spanType issue Update FIFO timing arc related with RSTA/B->CLKA/B Update ALU timing arc : R/CO [0:17, 18:53] -> [0:35,36:53] - Packing Add support to optionally using GND for pass-through latch [10/23/2024] V2.14.6 TST102324 - Device modeling Rollback ALU/MULT timing arc. set routing x-wire delay ratio to 1.03 [10/16/2024] V2.14.6 TST101624 - Device modeling Fix timing modeling issue related with Latch-as-passthrough Fix timing arc issue for FIFO CSA/B [09/26/2024] V2.14.6 TST092624 - Place & Route Reduce router runtime by ~30% - RTL synthesis Adjust wide input logic optimization. [09/19/2024] V2.14.6 TST091924 - Place & Route * Router * update of basic timing data and improve Qor for 100k Placer update for delay estimation based on Router's new formula Placer update to use pass-through LUT instead of AX/BX/CX/DX [09/10/2024] V2.14.6 TST091024 - GUI Fix regression issue of unable to select directory when creating new project persist setting of external editor - RTL synthesis Add option to control length lower bound when inferring shift registers. - Place & Route Add loose support in pack effort low mode Refine gpack bus group support Fix AP placer stuck issue related with EBR36 Add -np_npl option for placement Update legalization to remove unroutable GND for ALU - Device Modeling Update FIFO timing arc [09/08/2024] V3.0.5 FT090824 - GUI Support external editor support more file extension for filtering Verilog files Fix issues related with hierarchy refresh, report, project, ...etc. - Bitgen Update related with DSP/Pre-adder for Seal devices Improve SED_CRC calculation related with SERDES/PCIE/PLL fuse for Seal 366 device - Place & Route Fix VCC lut driver assignment issues in Seal router Fix EBR placement stuck issue in AP mode. - Design Interface Update simulation file of PLL and MULT for Seal devices Enhance unrouteable GND legalization for third-party synthesis result -- related with SERDES_CH/ALU54 - RTL synthesis Improve DSP inference/retargeting related with pre-adder and MULT C register Enhance parameter type checking. Support global level parameter, function and task Enhance FSM optimization related with priority inputs Fix unstable issue in SRL inference [09/01/2024] V3.0.5 FT090124 - Device update Add new device/package: SL2-25E-8U324A SA5Z-30-D0-8U324A SA5T-100-D0-8UA324CI SA5T-100-D0-7FA676CI Fix ECLK CLKPAD input issue for SL2V device - IP Creator DDRC IP document update by fixing typos Rename CM33 IP to START - GUI Fix issue related with whitespaces in file path, linux file link, console ".." in file path, design hierarchy, console, file adding, ...etc. - Place & Route Enhance EBR/DSP placement with ~3% QoR improvement for Seal 30k device - Bitgen xfb compress and EBR init-data update for sealion 2K devices - RTL synthesis Refine Verilog Analyzer Fix issue in parameter instantiation with empty list. Error out for non-existing file in $readmemb/h or include Add file info for duplicated instance name Refine error message when passing a variable to $clog; Refine FF optimization on CE handling to reduce runtime. Reduce runtime in MUX optimization for large corner cases Refine RAM infer checking and message prompt - Design Interface update xsDLLDLY xsDELAYDYN simulation file Bank reordering support for Seal 50K device - STA Fix a bug related with set_false_path to a clock source pin [08/28/2024] V3.0.5 TST082824 - Place & Route Gpack: refine bus grouping AP : refine MULT9/PRADD9 support Pack : add LOOSE support - RTL synthesis Disable set/reset extraction for Seal devices. - device modeling Update DSP timing arcs [08/21/2024] V3.0.5 TST082124 - Place & Route Update pack/gpack for 2-pin net attached to EBR/DSP/DDRC Refine FIFO async reset duplication [08/20/2024] V3.0.5 FT082024 - Device update for Sealion devices Accumulative updates for 22K devices from 07/13 to 08/19 Change CIBTEST SEL_Fn parameter if Fn port is float for Sealion devices Device ID update for 2K devices MIPI iotype support for 2K devices [08/18/2024] V3.0.5 FT081824 - GUI Add/remove files in file hierarchy tab page Add hierarchy refresh function Support project clean function Add toolbar button to enable/disable mini-map Fix issues related with EDIF top module, E176 package - IP Creator Change IP Aurora_8b10b to 8b10b_Encoder_Decoder FIFO_Generator IP: fixe reset logic by adding auto-reset FIFO IP: fix an issue related with RDC enable condition - RTL Synthesis Refine DSP infer/map/retargeting related with signedA/B, P connections Update RAM infer/map/retargeting related with PDP RAM with same clock. Fix a corner crash issue in Set/Reset extraction, related with redundant logic. Fix an assertion issue in XOR optimization. Fix a message file-code mismatch issue. Redundant mux connected to FF R/S. - Place & Route Fix looptdo regression issue, add -hold_slack option. - Design Interface Fix wrong PLL number in resource report for Sealion 4K device Fix PIO number in resource report for Sealion 2K device Add checking of mutually exclusive JTAGENB vs JTAG pins for Sealion 2K device. [08/12/2024] V3.0.5 FT081224 - Device update Fix E9 (CCLK) pinmap issue for Seal50K U324 device/package - GUI Fix a corner issue in design hierarchy display, related with conditional generate statement. This issue only affects visual effect, synthesis result is correct. - RTL synthesis Refine DSP support Enhance MULT support for Sealion 22K device (no ALU) [08/09/2024] V3.0.5 FT080924 - Ip Creator FIFO IP: Fix issues related with RDC, address width, AF. DDRC IP: Update PHY IO for Seal 50K devices Fix row address width issue in DDR2 128Mb mode Fix read fifo bug in BL8 mode for Seal 30K device Fix bug on merging cmd_clk into data_clk for Seal 30K device - Downloader Correct device ID and DNA for Sealion 2K device Fix downloading error for Seal 126 device - HqInsight Fix issues with EDIF flow, VLA/VIO, zoom level and fit, signal searching, waveform viewer switch, port connection, ...etc - Design Interface Update xsDDRCTRL_E1.v simulation model Add more Before/After script steps - Place & Route Enhance clock placement for Seal 126/366K devices [08/07/2024] V3.0.5 FT080724 - Design Interface Fix crash problem when warning on fail to absorb reg into IOLOGIC [08/05/2024] V3.0.5 FT080524 - IP Creator EBR IP: Fix issues under configurations: PDP_wr2048x32_rd8192x8 PDP_wr512x256_rd512x256 FIFO IP: fix data connection issue for Seal 30k/100k/366k devices [08/04/2024] V3.0.5 FT080424 - IP Creator DDRC-IP Fixed reset issue in phy_io fixed USR_ADDR_0 mapping issue for Seal 30K/50K devices - Downloader Add support for Sealion 2K device Fix EBR bit file download issue for Seal 126K/366K devices Fix negative error count issue - Bitgen Enhance LVCMOS33 IO setting for Seal 50k/100k devices Open _OP/_BA for user customized setting in UPC - RTL synthesis Reduce runtime for handling array range select, e.g. part = data[W * idx +: W] Fix expression optimization Linux-only long runtime issue Fix memory explosion issue related with constant propagation/sweep - Place & Route Fix issue related with DCS placement for Seal 126/366K devices. - Others Update user manual on debugging chapter. [07/31/2024] V3.0.5 FT073124 - IP Creator DDRC IP Fix issue on TXPR define value in DDR3 mode Add state register description in datasheet FIFO IP update for Seal 100K/126K devices Add 'Almost Full MAX Reference' for almost_full; Refined RDC port display of enable/disable status and range (if enabled); FIFO_Generator IP update related with rdata reset under fwft mode - Place & Route Fix placer issue of DQSI for seal 366K devices - Design Interface Update DDRC simulation models - GUI Refine display of top module (NOT using red color) Refine checking of missing xware executables (e.g. IP Creator is blocked by anti-virus software) [07/29/2024] V3.0.5 FT072924 - IP Creator Fix reconfigure IP issue when ip output file name prefix is not "xsIP" - Design Interface Add string in sealion/seal_syn_prim.v to trigger compilation error, INTENTIONALLY., if the file is used for simulation. - RTL synthesis Add debug support for step running on SDB/CDFG. - hqui Regenerate file for ChipViewer if it is outdated [07/28/2024] V3.0.5 FT072824 - IP Creator/HqInsight * Add independent VLA(Virtual Logic Analyzer) IP and debugger * Fix slow-response issue in VIO debugging Fix issues related partial signal display, unexpected signal deletion, language switch, ...etc. - Design Interface Fix "phyrule.set" command unfunctional in debug mode issue. - RTL synthesis Refine FF asynchronous control conversion flow. Fix issue of function partial selection assignment Refine FSM extraction to skip the ones with too-complex state transistion - Place & Routing Fix IO modeling issue of BANKJ in Seal 126K routing - GUI Refine unused port searching. Fix issues related with design hierarchy, flow, terminal,..etc. Integrates HqInsight in linux platform [07/24/2024] V3.0.5 FT072424 - Place & Route * Fix a bug in combining small-sized-chained LUT - RTL Synthesis Fix a corner Verilog lexer issue Refine partition of large-sized-RAM with OREG - Design Interface Update simulation model files of xsSERDES_CH and xsALU54SA - hqui-v3 Always generate .bit file when generating bitstream. [07/21/2024] V3.0.4 <============================================ - Device support ** New device/packages support ** SL2E-4V-8E144CI SL2E-4V-8U256CI SL2E-2V-8U256CI SA5T-100-D0-8FA676C Fix issue related with external 1.2V VREF support for Seal device Seal 30K IO_TYPE updates Support LVDS18 Disable IO_TYPE under 1.8v, except SSTL15 Add LVTTL33D support for Seal device - GUI Enhance design project migration with relative path handling Fix IO type missing issue in constraint editor for Seal devices Integrate routing heatmap viewer Add option to disable IO insertion Support import RTL with .f list file Enhance stability and usability of IDE-style GUI, fix issues related with editor, terminal, constrained editor, design hierarchy, flow control, special file hierarchy/path, message, list file, ...etc. - HqInsight (debugger) * Support multiple LA core * Improve user interaction performance Enhance handling of large files By default use internal waveform viewer (HqWave) instead of GtkWave Support VIO retargetting flow Keep instrumented signal settings when source file change Enhance source file change detection Enhance save/load of instrumented signal settings Support customized trigger position (pre-stored tap count). Optimize trigger condition Remove 'X' values (wait enough data stored before trigger) Refine VLA setting Refine UI (font, backcolor) Fix various issue related with : signal selection, waveform, color setting, radix, VLA setting, VIO debugger, editor display, EDIF flow, Continuous triggering, combined trigger condition top/sub module change/removal, synthesis directive, linux platform, ..etc. - IP Creator Refine error checking and prompt upon fail-run of an ipgen executable. Add new IPs: CM33 IP for Seal 50K device. SED IP for Seal device FIFO-Generator IP CORDIC IP: fix output data range error in complex modular(translate) mode DDRC IP update: add device checking Refine datasheet, diagram; Add an option to ouput file for simulation; Update for DDR3 mode; Fix clock-frequency setting issue in DDR3-SDRAM mode Add generation status checking and prompt FIFO IP: fix issues related with FULL/EMPTY flag PLL IP: Add PHASESEL bus width info in diagram, fix wrong messages GDDR71 IP: fix issues related with LVDS18 EBR IP: fix USE_XY_DA/DB parameter value issue for Seal 100K device CM3 IP: Fix typo on AHB master config page FFT IP: fix issues related with datawith 18 Filter IP: Update dataSheet on dual-chan-mode's control&data info Fix IP output file rename issue Solved issue related with white-space in path name - Downloader updates related with 50K/100K/4K devices update DNA information detection, bit-verify for sealion devices; refine output message and GUI Fix golden address issue for 4K/7K/12K/30K/50K devices Fix EBR initialization issue for Seal devices Add download support and DNA detection for 100K A2 device Fix svf.log-missing issue when hqfpga invoking cable Enhance dualboot to make primary address customizable Add dualboot primary address entry in GUI Fix EBR data issue when doing bit2bin of Seal 100K device Add dialog box upon multiple HqFpga instances Fixed the problem of deleting bit files by mistake - Bitgen Fix PRADD/MULT C fuse Update package pins related with NCSO/ASDO/MCLK for Seal 50K devices Fix issue for HSTL12D SSTL12D POD12D IO types Support IO PGNG fuse setting for Seal devices. Adjust pgng fuse setting of LVCMOS33 io type for Seal 50K/100K devices Add an argument -dclk for specifying DCLK frequency Fix issues of pnterm fuse on differential IO_TYPE for Seal devices - RTL synthesis Fix an issue related with complex FSM state minimization Reduce runtime for redundant FF removal for corner cases. Enhance check of ROM infer size Improve if statement related with constant value if branch Refine RAM infer, map and retargetting: Support one-write two-read ports, open DO bits Support more complex coding styles using if/case statements Improve distributed PDP RAM inference related with byte-enable Support ROM address size reduction Fix issues related with single port RAM, addr-reg, byte-enable Improve SDP RAM inference related with ADDR-REG, ByteEnable Enhance error checking and message prompt during retargetting Refine DSP infer, map and retargetting: Enhance inference/map related with MULT+REG, DSP driving multiple ADD/SUBs Enhance DSP48 retargetting by supporting more OPMODEs Enhance DSP48 retargetting related with A/BREG mode and C port connection Enhance attribute support and parameter checking Enhance error checking for case statement with more than one default branches Refine error message prompt when instance name is the same as net name Fix analyzer issues related with function, task, multi-driven Refine DSP retargetting Refine big-sized ROM inference. Fix crash issue related with undriven input of MUX. Refine message prompt related with parameter, localparam and partial-selection Add checking for unconnected ports Support empty module which is actually a primitive Support non-blocking assignment in task Enhance constant FF removal Enhance large binary-mux partition handling. Enhance expression optimization on consecutive LSB 0s Refine exception checking and message prompt Check parameter value of primitives at early stage Refine naming of inferred shift-register logic Support one-dimensional reg array write in constant function; Improve constant array index handling Fix abnormal exit on syntax error of parameter by name Fix typos in message file Enhance attribute support for concated values. Reduce runtime for shift register inference. Reduce runtime for binary MUX handling Enhance array index net handling Enhance debug message upon exception in analyzer Fix issue related with array initialization Enhance exception handling in MUX optimization Improving $readmem statement for empty mem init file Fix dead loop issue in expression optimization Fix an cross-probing issue related with macro Add checking of port-redecalration and illegal definition Remove FF dummy control pins Fix issues in FSM state extraction and minimization Fix long runtime issue when parsing encrypted file Fix crash issues related with module without port Unified error message in Chinese and English; Refine error message related with port declaration - Place & Route Enhance routability and congestion handling of router for Seal devices reduce ~10% routing runtime Enhance routability for Seal device with ~10% routing runtime reduction Fix packing crash issue related with abnormal SERDES connection Balance net/slice to avoid congestion for effort-low packing Refine SCLK clock/data sink routing policy for Sealion devices Enhance IOLOGIC packing support IREG and OREG/TREG with inverted clock phase Fix SADC placement issue for Seal 100K device Fix placement issue related with ALU24 for Seal devices Refine Bank ADC VCCIO checking for Seal 30K device - device modeling Fix timing arc missing issue between RSTm and CLKn for Seal DSP cells Update timing information related with DWA of EBR18/36, CLKm->RSTn of DSP Update wide-EBR support and timing info. - Design interface Add differential clock IO checking Set DMP, ECC_EFB, ISCPU as dont-touch to keep it from being swept. More strict checking on string-type parameters of primitives Do EBR/DSP retargetting immediately after EDIF reader. Enhance type/range validity checking to primitive parameters Seal pack update for EDIF lut pairing Report un-used resources in utilization report Support IS_*_INVERTED parameters for primitives generated by 3rd-party tool Refine mixed-clock-data check for inverter/buffer update Verilog write NOT to write equation for non-generic logic cells (e.g. MUXCY) Simulation model update: Add DDRCTRL models for modelsim EBR model update for READ_BEFORE_WRITE mode of both ports SERDES_CH/SERDES_COM_E1 Expose new SERDES ports to users: SERDES_CH.QPLLCLK and SERDES_COM_E1.QPLLOUTCLK IO report: show package pin name instead of inner pad location for seal devices Include IREG/OREG/TREG numbers when reporting IOLOGIC resources. Add checking of IREG/OREG/TREG usage and pairing Report PRADD utilization - STA Support analysis/report for unconstrained clocks Fix a crash bug related with enormous path constraints Enhance validity checking for clock group constraint [02/18/2024] V3.0.3 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.4 Build 021824: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.4/ [11/06/2023] V3.0.2 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.3 Build 110623: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.3/ [06/19/2023] V3.0.1 <============================================ - IDE-look UI Fixed issues in previous release Improved usability - Core components are same as those in HqFpga 2.14.2 Build 061923: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.2/ [02/19/2023] V3.0.0 <============================================ - IDE-look UI - Core components are same as those in HqFpga 2.14.1 Build 021923: http://211.157.136.83/hqfpga_xist/offical_releases/hq_xist_2.14.1/